CN116662246B - Data reading circuit crossing clock domain and electronic device - Google Patents
Data reading circuit crossing clock domain and electronic device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The application discloses a clock domain crossing data reading circuit and an electronic device, which comprise a ping-pong buffer module, a ping-pong asynchronous signal conversion module and a data reading module, wherein the ping-pong signal output end of the ping-pong buffer module is electrically connected with the ping-pong signal input end of the ping-pong asynchronous signal conversion module, the first register data output end and the second register output end of the ping-pong buffer module are respectively electrically connected with the first data input end and the second data input end of the data reading module, the output end of the data reading module is electrically connected with the second clock domain data input end, and the first selection signal input end of the data reading module is electrically connected with the ping-pong asynchronous signal output end of the ping-pong asynchronous signal conversion module. The ping-pong buffer module prolongs the storage time of the first clock domain data, so that the data reading module of the second clock domain can correctly and completely read the stable first clock domain data, the problem of metastable reading of the data across the clock domains is avoided, and the stability of reading the data across the clock domains is improved.
Description
Technical Field
The application belongs to the technical field of digital circuits, and particularly relates to a clock domain-crossing data reading circuit and an electronic device.
Background
With the development of electronic technology, the integrated circuit has higher and higher integration level, and the clock frequency of each module in the integrated circuit is difficult to keep in the same clock domain, so that asynchronous data transmission across the clock domain occurs in the situation; when the integrated circuit is applied to an electronic device with a data bus transmission function, since the data bus protocols follow a fixed clock frequency, it cannot be guaranteed that the clock frequency followed by the data bus protocols is the same as that in the integrated circuit, and asynchronous data transmission across different clock domains also occurs.
In a conventional method for reading data across clock domains, for example, a first clock domain with a relatively high clock frequency reads data in a second clock domain with a relatively low clock frequency, first, a read signal of the first clock domain needs to be first identified, then the read signal is synchronized into the second clock domain through two-stage synchronization, and finally the data in the second clock domain is read through the read signal. Taking the clock frequency of the first clock domain as 400KHz and the clock frequency of the second clock domain as 32KHz as an example, as shown in fig. 1, when the first clock domain reads the second clock domain signal, an in_vld read signal needs to be generated under the first clock domain i2c_400k, the signal is synchronized to the second clock domain to be a sync_vld1 signal through two-stage synchronization, the maximum time required by the two-stage synchronization is 2 clock cycles of 32KHz and is about 61us, the time is long, and the method is not applicable to some occasions with higher performance requirements, for example, the i2c interface is used for reading the data in a chip, and the data needs to be ensured to be read in 8 i2c_400k Hz clock cycles after the read signal in_vld is generated, and the 8 i2c_400k Hz clock cycles are 20us, which is far less than the time required by the two-stage synchronization, and is that the first clock domain cannot read the data of the second clock domain completely.
Disclosure of Invention
In view of this, the present application provides a clock domain crossing data reading circuit and an electronic device, and is mainly aimed at solving the problem that the existing clock domain crossing data reading method cannot completely and correctly read data.
In order to solve the above problems, the present application provides a data reading circuit across clock domains, where the data reading circuit across clock domains includes a ping-pong buffer module, a ping-pong asynchronous signal conversion module, and a data reading module, where a clock signal input end of the ping-pong buffer module is electrically connected to a clock signal output end of a first clock domain clock signal providing terminal, a selection signal input end of the ping-pong buffer module is electrically connected to a second enable signal output end of a second enable signal providing terminal, a ping-pong signal output end of the ping-pong buffer module is electrically connected to a ping-pong signal input end of the ping-pong asynchronous signal conversion module, a first register data output end of the ping-pong buffer module is electrically connected to a first data input end of the data reading module, a second register data output end of the ping-pong buffer module is electrically connected to a second data input end of the data reading module, an output end of the data reading module is electrically connected to a second clock signal input end of the data reading module, and an output end of the data reading module is electrically connected to a second clock domain clock signal providing terminal of the data reading module;
The ping-pong buffer module is used for generating a ping-pong signal, prolonging the storage time of the first clock domain data based on the ping-pong signal, the ping-pong asynchronous signal conversion module is used for converting the ping-pong signal of the first clock domain into the ping-pong asynchronous signal of the second clock domain, and the data reading module is used for reading the first clock domain data after the delay of the storage time according to the ping-pong asynchronous signal, wherein the clock frequency of the first clock domain is smaller than that of the second clock domain.
In an embodiment of the present application, optionally, the ping-pong buffer module includes a ping-pong signal generating unit, a data combining unit, and a data buffer unit, where a selection signal input end of the ping-pong signal generating unit is electrically connected to a second enable signal output end of the second enable signal providing terminal, a ping-pong signal output end of the ping-pong signal generating unit is electrically connected to a ping-pong signal input end of the ping-pong asynchronous signal conversion module, a first selection signal input end of the data combining unit and a selection signal input end of the data buffer unit, a clock signal input end of the ping-pong signal generating unit is electrically connected to a clock signal output end of the first clock domain clock signal providing terminal, a second selection signal input end of the data combining unit is electrically connected to a second enable signal output end of the second enable signal providing terminal, a first data input end of the data combining unit is electrically connected to a first register data output end of the data buffer unit, a second data input end of the data combining unit is electrically connected to a second register data output end of the data buffer unit, and a data input end of the data combining unit is electrically connected to a second register data output end of the data buffer unit.
In one embodiment of the present application, optionally, the ping-pong signal generating unit includes a first selector and a first flip-flop, where a selection signal input end of the first selector is electrically connected to a second enable output end of a second enable signal providing terminal, a first input end of the first selector is electrically connected to a first output end of the first flip-flop, a second input end of the first selector is electrically connected to a second output end of the first flip-flop, an output end of the first selector is electrically connected to an input end of the first flip-flop, a clock signal input end of the first flip-flop is electrically connected to a clock signal output end of a first clock domain clock signal providing terminal, and a first output end of the first flip-flop is further electrically connected to a ping-pong signal input end of the asynchronous signal conversion module, a first selection signal input end of the data combining unit, and a selection signal input end of the data buffering unit, respectively.
In one embodiment of the present application, optionally, the data combining unit includes a second selector, an adder, and a plurality of buffered data selecting branches, where each buffered data selecting branch includes a third selector, the adder is provided with a plurality of second input terminals, a selection signal input terminal of the second selector is electrically connected to a second enable signal output terminal of the second enable signal providing terminal, a first input terminal of the second selector is electrically connected to a positive electrode of a power supply, a second input terminal of the second selector is electrically connected to a negative electrode of the power supply, an output terminal of the second selector is electrically connected to a first input terminal of the adder, a selection signal input terminal of each third selector is electrically connected to a ping-pong signal output terminal of the ping-pong signal generating unit, a first input terminal of each third selector is electrically connected to a first register data output terminal of the ping-pong buffer module, a second input terminal of each third selector is electrically connected to a second register data output terminal of the ping-pong buffer module, and an output terminal of each third selector is electrically connected to the first input terminal of the adder.
In one embodiment of the present application, optionally, the data buffer unit includes a plurality of first register selection branches, a plurality of first registers, a plurality of second register selection branches, and a plurality of second registers, each first register selection branch includes a fourth selector, each first register includes a second flip-flop, each second register selection branch includes a fifth selector, each second register includes a third flip-flop, wherein a selection signal input terminal of each fourth selector is electrically connected to a ping-pong signal output terminal of the ping-pong signal generating unit, a first input terminal of each fourth selector is electrically connected to an output terminal of the second flip-flop, a second input terminal of each fourth selector is electrically connected to an input terminal of one second flip-flop, an output terminal of each second flip-flop is electrically connected to an input terminal of the data reading module and a first input terminal of one third flip-flop, respectively, and each second input terminal of the fourth selector is electrically connected to an output terminal of the clock signal domain;
The selection signal input end of each fifth selector is electrically connected with the ping-pong signal output end of the ping-pong signal generating unit, the first input end of each fifth selector is electrically connected with the output end of the adder, the second input end of each fifth selector is electrically connected with the output end of the third trigger, the output end of each fifth selector is electrically connected with the input end of one third trigger, the output end of each third trigger is respectively electrically connected with the input end of the data reading module and the second input end of one third selector, and the clock signal input end of each third trigger is electrically connected with the clock signal output end of the first clock domain clock signal providing terminal.
In one embodiment of the present application, optionally, the second clock domain data input terminal is multiple, the data reading module includes multiple reading selection branches and multiple reading branches, each reading selection branch includes a sixth selector, each reading branch includes a seventh selector and a fourth flip-flop, where the selection signal input terminal of each sixth selector is electrically connected to the ping-pong asynchronous signal output terminal of the ping-pong asynchronous signal conversion module, the first input terminal of each sixth selector is electrically connected to the output terminal of one second flip-flop, the second input terminal of each sixth selector is electrically connected to the output terminal of one third flip-flop, the output terminal of each sixth selector is electrically connected to the first input terminal of one seventh selector, the second input terminal of each seventh selector is electrically connected to the output terminal of one fourth flip-flop, the output terminal of each seventh selector is electrically connected to the input terminal of one fourth flip-flop, the first input terminal of each seventh selector is electrically connected to the input terminal of one fourth flip-flop, the second input terminal of each fourth selector is electrically connected to the output terminal of the fourth flip-flop, and the second clock domain data can be provided.
In one embodiment of the present application, optionally, the ping-pong asynchronous signal conversion module includes a fifth flip-flop and a sixth flip-flop, where a clock signal input terminal of the fifth flip-flop is electrically connected to a clock signal output terminal of the second clock domain clock signal providing terminal, a data input terminal of the fifth flip-flop is electrically connected to a ping-pong signal output terminal of the ping-pong buffer module, an output terminal of the fifth flip-flop is electrically connected to a data input terminal of the sixth flip-flop, an output terminal of the sixth flip-flop is electrically connected to a first selection signal input terminal of the data reading module, and a clock signal input terminal of the sixth flip-flop is electrically connected to a clock signal output terminal of the second clock domain clock signal providing terminal.
In one embodiment of the present application, optionally, when the ping-pong signal is a low level signal and the second enable signal is a high level, the data combining unit adds one to the first clock domain data stored in the second register of the data buffering unit and stores new first clock domain data in the first register of the data buffering unit, and when the ping-pong signal is a high level signal and the second enable signal is a high level, the data combining unit adds one to the first clock domain data stored in the first register of the data buffering unit and stores new first clock domain data in the second register of the data buffering unit.
In one embodiment of the present application, optionally, when the ping-pong asynchronous signal is a low level signal and the read enable signal is a high level signal, the data reading module outputs the first clock domain data stored in the second register of the ping-pong buffer module to the second clock domain data input terminal, and when the ping-pong asynchronous signal is a high level signal and the read enable signal is a high level signal, the data reading module outputs the first clock domain data stored in the first register of the ping-pong buffer module to the second clock domain data input terminal.
The application also provides an electronic device comprising the data reading circuit crossing clock domains.
The application has the beneficial effects that: according to the data reading circuit and the electronic device for the cross-clock domain, the ping-pong buffer module is used for prolonging the storage time of the data in the first clock domain, so that the data reading module in the second clock domain can correctly and completely read the stable data in the first clock domain, the problem of metastable state of data reading in the cross-clock domain is avoided, the circuit and the electronic device are applicable to occasions with high performance requirements or low performance requirements, and the stability and the applicability of data reading in the cross-clock domain are improved.
The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a signal timing diagram of a prior art cross-clock domain data read circuit;
FIG. 2 is a block diagram of a data read circuit across clock domains in accordance with an exemplary embodiment of the present application;
FIG. 3 is a block diagram of a ping-pong buffer module of a data read circuit across clock domains according to an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of a partial circuit configuration of a data read circuit crossing clock domains according to an exemplary embodiment of the present application;
FIG. 5 is a schematic diagram of a partial circuit configuration of a data combining unit of a data reading circuit crossing clock domains according to an exemplary embodiment of the present application;
Fig. 6 is a schematic circuit diagram of a part of a data buffer unit and a data reading module of a data reading circuit crossing clock domains according to an exemplary embodiment of the present application.
Wherein,,
the reference numerals of fig. 2-6 are as follows: 12-a ping-pong buffer module; 14-a ping-pong asynchronous signal conversion module; 16-a data reading module; 20-a first clock domain clock signal providing terminal; a 30-second enable signal providing terminal; 40-a second clock domain clock signal providing terminal; 50-a second clock domain read enable signal providing terminal; 121-a ping-pong signal generating unit; 122-a data combination unit; 123-a data cache unit; u1-a first selector; u2-a first flip-flop; u3-a second selector; u4-adder; u5-a third selector; u6-fourth selector; u7-a second flip-flop; u8-fifth selector; u9-a third flip-flop; u10-sixth selector; u11-seventh selector; u12-fourth flip-flop; u13-fifth flip-flop; u14-sixth flip-flop.
Detailed Description
The application will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
In order to further describe the technical means and effects adopted for achieving the preset aim of the application, the following detailed description refers to the specific implementation, structure, characteristics and effects according to the application of the application with reference to the accompanying drawings and preferred embodiments. In the following description, different "an embodiment" or "an embodiment" do not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Data read circuits across clock domains according to some embodiments of the present application are described below in conjunction with fig. 2-6.
In one embodiment, as shown in fig. 2, a data reading circuit across clock domains includes a ping-pong buffer module 12, a ping-pong asynchronous signal conversion module 14 and a data reading module 16, where a clock signal input terminal of the ping-pong buffer module 12 is electrically connected to a clock signal output terminal of a first clock domain clock signal providing terminal 20, a selection signal input terminal of the ping-pong buffer module 12 is electrically connected to a second enable signal output terminal of a second enable signal providing terminal 30, a ping-pong signal output terminal of the ping-pong buffer module 12 is electrically connected to a ping-pong signal input terminal of the ping-pong asynchronous signal conversion module 14, a first register data output terminal of the ping-pong buffer module 12 is electrically connected to a first data input terminal of the data reading module 16, a second register data output terminal of the ping-pong buffer module 12 is electrically connected to a second data input terminal of the data reading module 16, an output terminal of the data reading module 16 is electrically connected to a clock signal output terminal of the second clock domain clock signal providing terminal 20, a second selection signal input terminal of the data reading module 16 is electrically connected to a second clock signal output terminal of the second clock domain clock signal providing terminal 40 of the data reading module 16, and a second selection signal input terminal of the data reading module 16 is electrically connected to a second clock signal output terminal of the clock domain clock signal providing terminal 40 of the clock signal providing terminal of the data reading module 14;
The ping-pong buffer module 12 is configured to generate a ping-pong signal, extend the storage time of the data in the first clock domain based on the ping-pong signal, the ping-pong asynchronous signal conversion module 14 is configured to convert the ping-pong signal in the first clock domain into a ping-pong asynchronous signal in the second clock domain, and the data reading module 16 is configured to read the data in the first clock domain after the delay of the storage time according to the ping-pong asynchronous signal, where the clock frequency in the first clock domain is less than the clock frequency in the second clock domain.
Specifically, the asynchronous signal is synchronously processed by using a ping-pong operation, the ping-pong signal is generated in a first clock domain of the slow clock domain, the ping-pong buffer module generates the ping-pong signal based on a second enable signal provided by the second enable signal providing terminal, the ping-pong signal is flipped once every second (the flipping frequency can be adjusted according to the actual circuit function requirement), when the ping-pong signal is 0, the first clock domain data is stored in a second register of the ping-pong buffer module of the first clock domain, and when the ping-pong signal is 1, the first clock domain data is stored in a first register of the ping-pong buffer module of the first clock domain. When the second clock domain of the fast clock domain reads the data of the first clock domain, the ping-pong signal of the first clock domain is firstly required to be synchronized to the second clock domain through two stages, and the ping-pong asynchronous signal conversion module converts the ping-pong signal into a ping-pong asynchronous signal. When the read enable signal under the second clock domain is 1, if the ping-pong asynchronous signal is detected to be 1, the data reading module directly samples the first clock domain data in the first register of the ping-pong buffer module to the data transmission end of the second clock domain, and if the read enable signal is 1 and the ping-pong signal is converted to 0, the data reading module directly samples the first clock domain data in the second register of the ping-pong buffer module to the data transmission end of the second clock domain.
In this embodiment, the first clock domain is a slow clock domain, the second clock domain is a fast clock domain, for example, the first clock domain has a clock frequency of 32KHz and the second clock domain has a clock frequency of 400KHz.
Compared with the prior art, the data reading circuit across clock domains provided by the application has the advantages that the storage time of the data in the first clock domain is prolonged through the ping-pong buffer module, so that the data reading module in the second clock domain can correctly and completely read the stable data in the first clock domain, the problem of metastable state of data reading across clock domains is avoided, the circuit is applicable to occasions with high performance requirements or low performance requirements, and the stability and applicability of data reading across clock domains are improved.
In one embodiment, referring to fig. 3, the ping-pong buffer module 12 includes a ping-pong signal generating unit 121, a data combining unit 122 and a data buffer unit 123, where a selection signal input end of the ping-pong signal generating unit 121 is electrically connected to a second enable signal output end of the second enable signal providing terminal 30, a ping-pong signal output end of the ping-pong signal generating unit 121 is electrically connected to a ping-pong signal input end of the ping-pong asynchronous signal converting module 14, a first selection signal input end of the data combining unit 122 and a selection signal input end of the data buffer unit 123, a clock signal input end of the ping-pong signal generating unit 121 is electrically connected to a clock signal output end of the first clock domain clock signal providing terminal 20, a second selection signal input end of the data combining unit 122 is electrically connected to a second enable signal output end of the second enable signal providing terminal 30, a first data input end of the data combining unit 122 is electrically connected to a first register data output end of the data buffer unit 123, a second data input end of the data combining unit 122 is electrically connected to a second register data output end of the data buffer unit 123, a second data output end of the data combining unit 122 is electrically connected to a second register data output end of the data buffer unit 123, and a second output end of the data buffer unit 123 is electrically connected to a second output end of the data input end of the data buffer unit 16 is electrically connected to a second clock signal input end of the data buffer unit 16.
In this embodiment, the ping-pong signal generating unit generates a ping-pong signal based on the second enable signal provided by the second enable signal providing terminal, and transmits the ping-pong signal to the data combining unit, the data buffering unit, and the ping-pong asynchronous conversion module. When the second enabling signal is 1 and the ping-pong signal is 1, the data combination unit adds 1 to the data stored in the first register of the ping-pong buffer unit and sends the data to the data input end of the ping-pong buffer unit, and the ping-pong buffer unit stores the data transmitted by the data combination unit to the second memory; when the second enabling signal is 1 and the ping-pong signal is 0, the data combination unit adds 1 to the data stored in the second register of the ping-pong buffer unit, and sends the data to the data input end of the ping-pong buffer unit, and the ping-pong buffer unit stores the data transmitted by the data combination unit to the first memory.
In one embodiment, as shown in fig. 4, the ping-pong signal generating unit 121 includes a first selector U1 and a first flip-flop U2, wherein the selection signal input terminal of the first selector U1 is electrically connected to the second enable output terminal of the second enable signal providing terminal 30, the first input terminal of the first selector U1 is electrically connected to the first output terminal of the first flip-flop U2, the second input terminal of the first selector U1 is electrically connected to the second output terminal of the first flip-flop U2, the output terminal of the first selector U1 is electrically connected to the input terminal of the first flip-flop U2, the clock signal input terminal of the first flip-flop U2 is electrically connected to the clock signal output terminal of the first clock domain clock signal providing terminal 20, and the first output terminal of the first flip-flop U2 is also electrically connected to the ping-pong signal input terminal of the asynchronous signal converting module 14, the first selection signal input terminal of the data combining unit 122, and the selection signal input terminal of the ping-pong signal buffering unit 123, respectively.
It should be noted that, in fig. 4-6, the first input terminal of each selector is the pin INA of the selector, the second input terminal of each selector is the pin INB of the selector, the output terminal of each selector is the pin OUT of the selector, ping pong is a ping-pong signal, ping_sync is a ping-pong asynchronous signal, dout is an output signal of the data reading module, the output terminal of the data reading module is connected to the second clock domain data input terminal, cnt_p is the first register data of the data buffering unit, cnt_n is the second register data of the data buffering unit, and in addition, when the same reference numerals are labeled beside the connecting lines according to the well-known circuit drawing, it is represented that the connecting lines are connected together, for example, the connecting lines labeled with the ping signal are connected together.
In FIG. 4, the input terminal of each flip-flop is the pin D of the flip-flop, the clock signal input terminal of each flip-flop is the pin CLK of the flip-flop, the first output terminal of each flip-flop is the pin Q of the flip-flop, and the second output terminal of each flip-flop is the pin of the flip-flop。
Specifically, when the second enable signal provided by the second enable signal providing terminal is 1, the first selector transmits the data of the first input end to the input end of the first trigger, and as the data of the first input end of the first selector is connected with the first output end of the first trigger, if the first output end of the first trigger is 0, the ping-pong signal is 0, and if the first output end of the first trigger is 1, the ping-pong signal is 1; when the second enabling signal provided by the second enabling signal providing terminal is 0, the first selector transmits the data of the second input end to the input end of the first trigger, and as the data of the second input end of the first selector is connected with the second output end of the first trigger, if the second output end of the first trigger is 0, the ping-pong signal is 0, and if the second output end of the first trigger is 1, the ping-pong signal is 1.
In one embodiment, the second enable providing terminal includes an adder, a flip-flop and a comparator, wherein a first input terminal of the adder is electrically connected to an output terminal of the flip-flop, a second input terminal of the adder is connected to a positive power supply, a clock signal input terminal of the flip-flop is electrically connected to the first clock domain clock signal providing terminal, an output terminal of the flip-flop is further electrically connected to a first input terminal of the comparator, a second input terminal of the comparator is connected to the value providing terminal, and the value providing terminal outputs 32768 a value to a second input terminal of the comparator. The output data of the trigger is always added with 1 due to the fact that the output end of the trigger is connected with the first input end of the comparator, when the value of the first input end of the comparator is larger than that of the second input end of the comparator, the comparator outputs 1, namely, the output second enabling signal is 1, and when the value of the first input end of the comparator is smaller than that of the second input end of the comparator, the comparator outputs 0, namely, the output second enabling signal is 0.
In one embodiment, referring to fig. 4 and 5, the data combining unit 122 includes a second selector U3, an adder, and a plurality of buffer data selecting branches, each buffer data selecting branch includes a third selector U5, the adder is provided with a plurality of second inputs, wherein the selection signal input of the second selector U3 is electrically connected to the second enable signal output of the second enable signal providing terminal 30, the first input of the second selector U3 is electrically connected to the positive electrode of the power supply, the second input of the second selector U3 is electrically connected to the negative electrode of the power supply, the output of the second selector U3 is electrically connected to the first input of the adder, the selection signal input of each third selector U5 is electrically connected to the table tennis signal output of the table tennis signal generating unit 121, the first input of each third selector U5 is electrically connected to the first register data output of the table tennis module 12, the second input of each third selector U5 is electrically connected to the second register data output of the table tennis module 12, and the output of each third selector U5 is electrically connected to the output of the adder.
In fig. 5 and 6, cnt_p1, cnt_p2, and cnt_p3 are data sequentially output from the first register data of the data buffer unit in a multi-bit manner, and cnt_n1, cnt_n2, and cnt_n3 are data sequentially output from the second register data of the data buffer unit in a multi-bit manner, and only three groups are drawn as an example.
Specifically, when the second enabling signal is 1, the output end of the second selector is 1 and is transmitted to the first input end of the adder, when the ping-pong signal is 1, the output data of each third selector is the data of the first input end of the third selector, and because the first input end of each third selector respectively obtains the data from the data output end of the first register of the ping-pong buffer module connected with the first input end of each third selector, the second input end of the adder is connected with each third selector through a multi-bit connection mode, the adder reads the data represented by the plurality of third selectors through the multi-bit connection mode, the data of the second input end of the adder is obtained, the data of the second input end is added with the data 1 of the first input end, new output data is obtained, and then the new data is respectively output to the data input end of the ping-pong buffer unit through the multi-bit connection mode, and the number of the preferred third selectors is 6. In the initial state, the data output end data of the first register and the data output end data of the second register of the ping-pong buffer module are 0.
In one embodiment, a power module provides operating power for a data read circuit across a clock domain, the power module being electrically connected to power terminals of chips of a plurality of units or modules, respectively.
In one embodiment, referring to fig. 4, 5 and 6, the data buffer unit 123 includes a plurality of first register selection branches, a plurality of first registers, a plurality of second register selection branches and a plurality of second registers, each first register selection branch includes a fourth selector U6, each first register includes a second flip-flop U7, each second register selection branch includes a fifth selector U8, each second register includes a third flip-flop U9, wherein a selection signal input of each fourth selector U6 is electrically connected to a ping-pong signal output of the ping-pong signal generating unit 121, a first input of each fourth selector U6 is electrically connected to an output of the second flip-flop U7, a second input of each fourth selector U6 is electrically connected to an output of the adder, an output of each fourth selector U6 is electrically connected to an input of one of the second flip-flops U7, an output of each second flip-flop U7 is electrically connected to an output of the clock signal input of the read module 16 and the third flip-flop U7, respectively, and each output of the second flip-flops U7 is electrically connected to an output of the clock signal input of the third flip-flop module 16;
The selection signal input terminal of each fifth selector U8 is electrically connected to the ping-pong signal output terminal of the ping-pong signal generating unit 121, the first input terminal of each fifth selector U8 is electrically connected to the output terminal of the adder, the second input terminal of each fifth selector U8 is electrically connected to the output terminal of the third flip-flop U9, the output terminal of each fifth selector U8 is electrically connected to the input terminal of one third flip-flop U9, the output terminal of each third flip-flop U9 is electrically connected to the input terminal of the data reading module 16 and the second input terminal of one third selector U5, respectively, and the clock signal input terminal of each third flip-flop U9 is electrically connected to the clock signal output terminal of the first clock domain clock signal providing terminal 20.
In fig. 6, the input end of each flip-flop is pin D of the flip-flop, the clock signal input end of each flip-flop is pin CLK of the flip-flop, and the output end of each flip-flop is pin Q of the flip-flop.
Specifically, the output end of the adder is connected with each fourth selector or each fifth selector through a multi-bit connection mode, that is to say, the 1-bit circuit comprises a fourth selector, a second trigger, a third trigger and a fifth selector. Only 1bit is described in detail herein, when the ping-pong signal is 1, since the first input terminal of the fifth selector is connected to the output terminal of the adder, the fifth selector outputs the data output from the adder to the input terminal of the third flip-flop, and when the first clock domain clock signal is 1, the third flip-flop transmits the data of the first input terminal to the output terminal and stores the data, that is, the output terminal of the third flip-flop stores the data output from the adder. When the ping-pong signal is 0, the second input end of the fourth selector is connected with the output end of the adder, the fourth selector outputs the data output by the adder to the input end of the second trigger, and when the clock signal of the first clock domain is 1, the second trigger transmits the data of the input end to the output end and stores the data, that is, the output end of the second trigger stores the data output by the adder. In the initial state, the data of the output end of the third trigger and the output end of the second trigger are 0.
In one embodiment, referring to fig. 4 and 6, the data input terminals of the second clock domain are plural, the data reading module 16 includes plural reading selection branches and plural reading branches, each reading selection branch includes a sixth selector U10, each reading branch includes a seventh selector U11 and a fourth flip-flop U12, where the selection signal input terminal of each sixth selector U10 is electrically connected to the ping-pong asynchronous signal output terminal of the ping-pong asynchronous signal conversion module 14, the first input terminal of each sixth selector U10 is electrically connected to the output terminal of one second flip-flop U7, the second input terminal of each sixth selector U10 is electrically connected to the output terminal of one third flip-flop U9, the output terminal of each sixth selector U10 is electrically connected to the first input terminal of one seventh selector U11, the second input terminal of each seventh selector U11 is electrically connected to the output terminal of one fourth flip-flop U12, the first input terminal of each seventh selector U11 is electrically connected to the output terminal of the fourth flip-flop U12, the second input terminal of each seventh selector U11 is electrically connected to the output terminal of the fourth flip-flop U7, and the second clock domain is electrically connected to the output terminal of the fourth clock domain is electrically, and the output signal is provided between the second input terminal of each seventh selector U10 and the output terminal of the fourth clock domain is electrically connected to the output terminal of the fourth clock signal is provided.
In this embodiment, since the data of the data buffer unit is transmitted in bits, the data of the data reading module also needs to be read in bits. Only 1bit is described herein, when the ping-pong asynchronous signal is 1, the output data of the sixth selector is the data of the first input terminal of the sixth selector, and since the data of the first input terminal of the sixth selector is the data stored in the second flip-flop, the output data of the sixth selector is the data stored in the second flip-flop and is transmitted to the first input terminal of the seventh selector, when the read enable signal is 1, the output data of the seventh selector is the data of the first input terminal of the seventh selector, that is, the data stored in the second flip-flop and is transmitted to the input terminal of the fourth flip-flop, and when the second clock domain clock signal is 1, the fourth flip-flop outputs the data stored in the second flip-flop; when the ping-pong asynchronous signal is 0, the output data of the sixth selector is the data of the second input end of the sixth selector, and since the data of the second input end of the sixth selector is the data stored in the third flip-flop, the output data of the sixth selector is the data stored in the third flip-flop and is transmitted to the first input end of the seventh selector, when the read enable signal is 1, the output data of the seventh selector is the data of the first input end of the seventh selector, namely the data stored in the third flip-flop and is transmitted to the input end of the fourth flip-flop, and when the second clock domain clock signal is 1, the fourth flip-flop outputs the data stored in the third flip-flop.
In one embodiment, as shown in fig. 4, the ping-pong asynchronous signal conversion module 14 includes a fifth flip-flop U13 and a sixth flip-flop U14, where the clock signal input terminal of the fifth flip-flop U13 is electrically connected to the clock signal output terminal of the second clock domain clock signal providing terminal 40, the data input terminal of the fifth flip-flop U13 is electrically connected to the ping-pong signal output terminal of the ping-pong buffer module 12, the output terminal of the fifth flip-flop U13 is electrically connected to the data input terminal of the sixth flip-flop U14, the output terminal of the sixth flip-flop U14 is electrically connected to the first selection signal input terminal of the data reading module 16, and the clock signal input terminal of the sixth flip-flop U14 is electrically connected to the clock signal output terminal of the second clock domain clock signal providing terminal 40.
Specifically, when the second clock domain clock signal is 1, the output data of the fifth flip-flop is the input data of the fifth flip-flop, and since the input data of the fifth flip-flop is the ping-pong signal, the fifth flip-flop outputs the ping-pong signal to the input terminal of the sixth flip-flop, and the output data of the sixth flip-flop is the input signal of the sixth flip-flop, that is, whether the sixth flip-flop outputs the ping-pong signal or not. Since the clock signals of the fifth trigger and the sixth trigger are connected with the clock signals of the second clock domain, the ping-pong signals passing through the fifth trigger and the sixth trigger are converted into the second clock domain from the first clock domain, so that the asynchronization of the ping-pong signals is realized, and the second clock domain is called as ping-pong asynchronization signals.
In one embodiment, the data combining unit 122 increments the first clock domain data stored in the second register of the data buffering unit 123 by one and stores the new first clock domain data in the first register of the data buffering unit 123 when the ping-pong signal is a low level signal and the second enable signal is a high level signal, and the data combining unit 122 increments the first clock domain data stored in the first register of the data buffering unit 123 and stores the new first clock domain data in the second register of the data buffering unit 123 when the ping-pong signal is a high level signal and the second enable signal is a high level signal.
In one embodiment, the data read module 16 outputs the first clock domain data stored in the second register of the ping pong buffer module 12 to the second clock domain data input when the ping pong asynchronous signal is a low level signal and the read enable signal is a high level signal, and the data read module 16 outputs the first clock domain data stored in the first register of the ping pong buffer module 12 to the second clock domain data input when the ping pong asynchronous signal is a high level signal and the read enable signal is a high level signal.
In a specific embodiment, when the ping-pong signal is 0, the first clock domain data is stored in the first register of the data buffer unit, when the ping-pong signal is 1, the first clock domain data is stored in the second register of the data buffer unit, and when the read enable signal arrives, the data of the first register of the data buffer unit and the data of the second register of the data buffer unit are read according to the ping-pong asynchronous signal, but the data of the register of which the data is being updated are not read, so that the metastable state problem can be avoided perfectly.
The data is read when the ping-pong signal goes from low to high, i.e. the first clock domain data is updating a value, the read enable signal is 1, and the first clock domain data is an updating signal, whereas the ping-pong operation is used to essentially double the first clock domain data storage time into the first register of the data cache unit and the second register of the data cache unit. For example, "46" in the first clock domain data is doubled and stored in the second register of the data buffer unit, when the read enable signal performs data sampling, the ping-pong asynchronous signal is detected to be 0, and the acquired data is actually stored in the second register of the data buffer unit. Therefore, when data is read in the first clock domain data updating process, the metastable state problem can be avoided by reading the stable data after the extension.
When the ping-pong signal reads data from high to low, the first clock domain data is updated, for example, 45' in the first clock domain data is prolonged by one time and is stored in the first register of the data buffer unit, and when the reading enabling signal performs data sampling, the ping-pong asynchronous signal is detected to be 1, and the acquired data is actually the data in the first register of the data buffer unit, so that the problem of metastability can be avoided by the ping-pong mode.
In one embodiment, the application also provides an electronic device, which comprises the data reading circuit crossing clock domains
Compared with the prior art, the electronic device provided by the application has the advantages that the storage time of the first clock domain data is prolonged through the ping-pong buffer module, so that the data reading module of the second clock domain can correctly and completely read the stable first clock domain data, the problem of metastable state of data reading across clock domains is avoided, the electronic device is applicable to occasions with high performance requirements or low performance requirements, and the stability and applicability of data reading across clock domains are improved.
It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the application will occur to persons of ordinary skill in the art.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above, and the detailed description of the embodiments given below, serve to explain the principles of the application.
These and other characteristics of the application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.
It is also to be understood that, although the application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the application.
The above and other aspects, features and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.
Specific embodiments of the present application will be described hereinafter with reference to the accompanying drawings; however, it is to be understood that the disclosed embodiments are merely exemplary of the application, which can be embodied in various forms. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.
The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.
The above embodiments are only exemplary embodiments of the present application and are not intended to limit the present application, the scope of which is defined by the claims. Various modifications and equivalent arrangements of this application will occur to those skilled in the art, and are intended to be within the spirit and scope of the application.
Claims (10)
1. A clock domain crossing data reading circuit is characterized by comprising a ping-pong buffer module, a ping-pong asynchronous signal conversion module and a data reading module, wherein,
the clock signal input end of the ping-pong buffer module is electrically connected with the clock signal output end of the first clock domain clock signal providing terminal, the selection signal input end of the ping-pong buffer module is electrically connected with the second enabling signal output end of the second enabling signal providing terminal, the ping-pong signal output end of the ping-pong buffer module is electrically connected with the ping-pong signal input end of the ping-pong asynchronous signal converting module, the first register data output end of the ping-pong buffer module is electrically connected with the first data input end of the data reading module, the second register data output end of the ping-pong buffer module is electrically connected with the second data input end of the data reading module, the output end of the data reading module is electrically connected with the asynchronous signal output end of the asynchronous signal converting module, the second selection signal input end of the data reading module is electrically connected with the reading enabling signal output end of the second clock domain reading enabling signal providing terminal, and the clock signal input end of the clock domain reading module is electrically connected with the clock signal output end of the clock domain converting module;
The ping-pong buffer module is used for generating a ping-pong signal, prolonging the storage time of the first clock domain data based on the ping-pong signal, the ping-pong asynchronous signal conversion module is used for converting the ping-pong signal of the first clock domain into the ping-pong asynchronous signal of the second clock domain, and the data reading module is used for reading the first clock domain data after the delay of the storage time according to the ping-pong asynchronous signal, wherein the clock frequency of the first clock domain is smaller than that of the second clock domain.
2. The data read circuit across clock domains as recited in claim 1, wherein the ping-pong buffer module comprises a ping-pong signal generation unit, a data combining unit, and a data buffer unit, wherein,
the selection signal input end of the ping-pong signal generating unit is electrically connected with the second enabling signal output end of the second enabling signal providing terminal, the ping-pong signal output end of the ping-pong signal generating unit is respectively electrically connected with the ping-pong signal input end of the ping-pong asynchronous signal converting module, the first selection signal input end of the data combining unit and the selection signal input end of the data caching unit, the clock signal input end of the ping-pong signal generating unit is electrically connected with the clock signal output end of the first clock domain clock signal providing terminal, the second selection signal input end of the data combining unit is electrically connected with the second enabling signal output end of the second enabling signal providing terminal, the first data input end of the data combining unit is electrically connected with the first register data output end of the data caching unit, the second data input end of the data combining unit is electrically connected with the second register data output end of the data caching unit, the data output end of the data combining unit is electrically connected with the data input end of the data caching unit, the first register data output end of the data combining unit is electrically connected with the first register data output end of the data caching unit, and the data input end of the data reading module is electrically connected with the second clock signal output end of the data caching unit.
3. The data read circuit across clock domains as recited in claim 2, wherein the ping-pong signal generating unit comprises a first selector and a first flip-flop, wherein,
the second enable signal input end of the second enable signal providing terminal is electrically connected with the second enable output end of the second enable signal providing terminal, the first input end of the second selector is electrically connected with the first output end of the second trigger, the second input end of the second selector is electrically connected with the second output end of the second trigger, the output end of the second selector is electrically connected with the input end of the second trigger, the clock signal input end of the second trigger is electrically connected with the clock signal output end of the second clock domain clock signal providing terminal, and the first output end of the second trigger is also electrically connected with the ping-pong signal input end of the ping-pong asynchronous signal conversion module, the first selection signal input end of the data combination unit and the selection signal input end of the data buffer unit respectively.
4. The data read circuit of claim 2, wherein the data combining unit comprises a second selector, an adder, and a plurality of buffered data selection branches, each buffered data selection branch comprising a third selector, the adder having a plurality of second inputs, wherein,
The second selector's selection signal input with second enable signal provides the second enable signal output of terminal and is connected electrically, the first input of second selector is connected with the positive electricity of power, the second input of second selector is connected with the negative electricity of power, the output of second selector is connected with the first input of adder, the selection signal input of every third selector with the ping-pong signal output of ping-pong signal generating element is connected electrically, the first input of every third selector respectively with the first register data output of ping-pong buffer module is connected electrically, the second input of every third selector respectively with the second register data output of ping-pong buffer module is connected electrically, the output of every third selector respectively with one second input of adder is connected electrically, the output of adder is connected electrically with the data input of data buffer unit.
5. The clock domain crossing data read circuit of claim 4, wherein the data buffer unit comprises a plurality of first register select branches, a plurality of first registers, a plurality of second register select branches, and a plurality of second registers, each first register select branch comprising a fourth selector, each first register comprising a second flip-flop, each second register select branch comprising a fifth selector, each second register comprising a third flip-flop, wherein,
The selection signal input end of each fourth selector is electrically connected with the ping-pong signal output end of the ping-pong signal generating unit, the first input end of each fourth selector is electrically connected with the output end of the second trigger, the second input end of each fourth selector is electrically connected with the output end of the adder, the output end of each fourth selector is electrically connected with the input end of one second trigger, the output end of each second trigger is respectively electrically connected with the input end of the data reading module and the first input end of one third selector, and the clock signal input end of each second trigger is electrically connected with the clock signal output end of the first clock domain clock signal providing terminal;
the selection signal input end of each fifth selector is electrically connected with the ping-pong signal output end of the ping-pong signal generating unit, the first input end of each fifth selector is electrically connected with the output end of the adder, the second input end of each fifth selector is electrically connected with the output end of the third trigger, the output end of each fifth selector is electrically connected with the input end of one third trigger, the output end of each third trigger is respectively electrically connected with the input end of the data reading module and the second input end of one third selector, and the clock signal input end of each third trigger is electrically connected with the clock signal output end of the first clock domain clock signal providing terminal.
6. The data read circuit of claim 5, wherein the second clock domain data input is plural, the data read module comprises a plurality of read select branches and a plurality of read branches, each read select branch comprises a sixth selector, each read branch comprises a seventh selector and a fourth flip-flop, wherein,
the selection signal input end of each sixth selector is electrically connected with the ping-pong asynchronous signal output end of the ping-pong asynchronous signal conversion module, the first input end of each sixth selector is electrically connected with the output end of one second trigger, the second input end of each sixth selector is electrically connected with the output end of one third trigger, the output end of each sixth selector is electrically connected with the first input end of one seventh selector, the second input end of each seventh selector is electrically connected with the output end of one fourth trigger, the output end of each seventh selector is electrically connected with the input end of one fourth trigger, the selection signal input end of each seventh selector is electrically connected with the read enable signal output end of the second clock domain read enable signal providing terminal, the output end of each fourth trigger is also electrically connected with the second clock domain data input end, and the clock signal input end of each fourth trigger is electrically connected with the clock signal output end of the second clock domain clock signal providing terminal.
7. The data read circuit across clock domains as recited in claim 1, wherein the ping-pong asynchronous signal conversion module comprises a fifth flip-flop and a sixth flip-flop, wherein,
the clock signal input end of the fifth trigger is electrically connected with the clock signal output end of the second clock domain clock signal providing terminal, the data input end of the fifth trigger is electrically connected with the ping-pong signal output end of the ping-pong buffer module, the output end of the fifth trigger is electrically connected with the data input end of the sixth trigger, the output end of the sixth trigger is electrically connected with the first selection signal input end of the data reading module, and the clock signal input end of the sixth trigger is electrically connected with the clock signal output end of the second clock domain clock signal providing terminal.
8. The data read circuit according to claim 2, wherein the data combining unit increments the first clock domain data stored in the second register of the data buffer unit and stores new first clock domain data in the first register of the data buffer unit when the ping-pong signal is a low level signal and the second enable signal is a high level signal, and the data combining unit increments the first clock domain data stored in the first register of the data buffer unit and stores new first clock domain data in the second register of the data buffer unit when the ping-pong signal is a high level signal and the second enable signal is a high level signal.
9. The data read circuit according to any one of claims 1 to 7, wherein the data read module outputs the first clock domain data stored in the second register of the ping-pong buffer module to the second clock domain data input terminal when the ping-pong asynchronous signal is a low level signal and the read enable signal is a high level signal, and outputs the first clock domain data stored in the first register of the ping-pong buffer module to the second clock domain data input terminal when the ping-pong asynchronous signal is a high level signal and the read enable signal is a high level signal.
10. An electronic device comprising a clock domain crossing data reading circuit as claimed in any one of claims 1 to 7.
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