CN116662238A

CN116662238A - Motherboard and computing device

Info

Publication number: CN116662238A
Application number: CN202310498365.0A
Authority: CN
Inventors: 吕旋; 张波
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-04-28
Filing date: 2023-04-28
Publication date: 2023-08-29

Abstract

The embodiment of the application provides a mainboard and computing equipment, relates to the technical field of computing, and is used for reducing the cost of the computing equipment. The main board comprises: the device comprises a board body, a south bridge chip, a central processing unit and a first conversion connector. The first transfer connector includes a first pin set and a second pin set. When the first transfer connector is connected to the through board, the first pin group and the second pin group are coupled through the through board, and SATA protocol signals output by the south bridge chip are transmitted to the storage component through the first pin group, the through board and the second pin group in sequence. When the first transfer connector is connected with the independent hard disk redundant array board, the central processing unit sends PCIE protocol signals to the independent hard disk redundant array board, and the independent hard disk redundant array board converts the PCIE protocol signals into SAS protocol signals which are transmitted to the storage component through the second pin group. The main board is used in the computing equipment.

Description

Motherboard and computing device

Technical Field

The present application relates to the field of computing technologies, and in particular, to a motherboard and a computing device.

Background

Servers typically support many hard disks, and there are differences in the manner in which hard disks are managed from server to server. For example, some servers support a RAID (Redundant Array of Independent Disks ) management scheme in which a CPU (Central Processing Unit, central processing unit) is electrically connected to a RAID chip that is electrically connected to a hard disk. At this time, the CPU may send PCIE (Peripheral Component Interconnect Express, peripheral interconnect bus) protocol signals to the RAID chip, and the RAID chip may convert PCIE protocol signals into SAS (Serial Attached SCSI ) protocol signals, and send SAS protocol signals to the hard disk, so as to manage the hard disk. For another example, some servers support a pass-through management mode, in which a south bridge chip is electrically connected to a hard disk, and the south bridge chip may output SATA (Serial Advanced Technology Attachment, serial ATA) protocol signals, and the SATA protocol signals may be transmitted to the hard disk, so as to manage the hard disk. In order to enable the server to support the two hard disk management modes, two signal transmission links are usually set in the server, and the server can support the two hard disk management modes, but one of the two hard disk management modes is adopted in a server product to manage the hard disk. The signal transmission links corresponding to the two hard disk management modes are completely different, so that the cost of the server is high.

Disclosure of Invention

The embodiment of the application provides a mainboard and computing equipment, which can reduce the cost of the computing equipment.

In one aspect, embodiments of the present application provide a motherboard. The main board comprises: the device comprises a board body, a south bridge chip, a central processing unit and a first conversion connector. The south bridge chip is arranged on the board body; the central processing unit is arranged on the plate body; the first transfer connector is arranged on the board body and comprises a first pin group and a second pin group; the first pin set is connected to the south bridge chip, and the second pin set is used for coupling with the storage component. When the first transfer connector is connected to the through board, the first pin group and the second pin group are coupled through the through board, the south bridge chip is used for outputting SATA protocol signals, and the SATA protocol signals can be transmitted to the storage component through the first pin group, the through board and the second pin group in sequence. When the first transfer connector is connected to the independent hard disk redundant array board, the central processing unit is coupled with the independent hard disk redundant array board, and the independent hard disk redundant array board is coupled with the second pin group, wherein the central processing unit is used for sending PCIE protocol signals to the independent hard disk redundant array board, the independent hard disk redundant array board can convert the PCIE protocol signals into SAS protocol signals, and the SAS protocol signals can be transmitted to the storage component through the second pin group.

Under the condition that the first transfer connector is connected to the through board card, SATA protocol signals output by the south bridge chip can be sequentially transmitted to the storage component through the first pin group, the through board card and the second pin group, and at the moment, the south bridge chip can manage the storage component. Under the condition that the first conversion connector is connected with the independent hard disk redundant array board, PCIE protocol signals output by the central processing unit can be sent to the independent hard disk redundant array board, the independent hard disk redundant array board can convert the PCIE protocol signals into SAS protocol signals, the SAS protocol signals can be transmitted to the storage component through the second pin group, and at the moment, the central processing unit can manage the storage component. Therefore, under the two conditions that the first transfer connector is connected with the through board card or the independent hard disk redundant array board card, the main board can manage the storage component, and the main board has higher compatibility. Therefore, the need of redesigning the motherboard due to changing the target board card can be avoided, so that the cost can be saved. In addition, in the case that the first conversion connector is connected to the through board card or the independent hard disk redundant array board card, signals received by the through board card or the independent hard disk redundant array board card can be transmitted to the second pin group and transmitted to the storage component through the second pin group. Therefore, the second pin group and the connection link between the second pin group and the memory component can be multiplexed in both cases, so that the cost of the motherboard can be reduced.

In some implementations, the motherboard further comprises: the second switching connector is arranged on the plate body and is connected with the central processing unit. When the first transfer connector is connected with the independent hard disk redundant array board, the independent hard disk redundant array board is also connected with the second transfer connector, and PCIE protocol signals output by the central processing unit can be transmitted to the independent hard disk redundant array board through the second transfer connector.

The second switching connector is electrically connected to the central processing unit, and the second switching connector can be electrically connected to the redundant array board of the independent hard disk, so that PCIE protocol signals generated by the central processing unit can be transmitted to the redundant array board of the independent hard disk through the second switching connector. Furthermore, the independent hard disk redundant array board can convert PCIE protocol signals into SAS protocol signals, and the SAS protocol signals can be transmitted to the storage component through the second pin group, so that the central processing unit and the management of the storage component are realized.

In some implementations, the first transit connector further includes a first in-place pin and the second transit connector further includes a second in-place pin. The motherboard further comprises: voltage circuit and programmable logic device set on the board body. The voltage circuit is connected to the first in-place pin and the second in-place pin, and can enable the voltage of the first in-place pin to be within a second voltage threshold range under the condition that the first in-place pin is not connected to the target board card; under the condition that the first in-place pin is connected with the target board card, the voltage circuit and the target board card jointly enable the voltage of the first in-place pin to be in a first voltage threshold range; under the condition that the second in-place pin is not connected with the target board card, the voltage circuit can enable the voltage of the second in-place pin to be in a second voltage threshold range; under the condition that the second in-place pin is connected with the target board card, the voltage circuit and the target board card jointly enable the voltage of the second in-place pin to be within a first voltage threshold range; the target board card is one of a through board card and an independent hard disk redundant array board card. The programmable logic device is connected to the first bit pin and the second bit pin; the programmable logic device is used for: detecting the voltage of the first bit pin and the voltage of the second bit pin; under the condition that the voltage of the first in-place pin and the voltage of the second in-place pin are both in a first voltage threshold range, determining that the board card connected with the first transfer connector is an independent hard disk redundant array board card; and under the condition that the voltage of the first bit pin is in a first voltage threshold range and the voltage of the second bit pin is in a second voltage threshold range, determining that the board card connected with the first transfer connector is a through board card.

The programmable logic device is provided with the first in-place pin on the first transfer connector and the second in-place pin on the second transfer connector, so that the type of the target board card (namely, the through board card or the independent hard disk redundant array board card) can be automatically detected when the target board card is connected to the first transfer connector.

In some implementations, the motherboard further comprises: the basic input/output unit is arranged on the plate body; the basic input/output unit is connected with the programmable logic device and the south bridge chip; the basic input/output unit is used for: and under the condition that the programmable logic device determines that the target board card connected with the first transfer connector is an independent hard disk redundant array board card, controlling the south bridge chip to stop outputting the SATA protocol signal.

Therefore, the second pin group does not receive the SATA protocol signal output by the south bridge chip, and the SAS protocol signal output by the independent hard disk redundant array board and the SATA protocol signal output by the south bridge chip can be prevented from collision on the second pin group, and interference is generated on signals on other pin groups.

In some implementations, the second transit connector includes a third pin set connected to the central processor and a fourth pin set for coupling with the redundant array of independent disks board card. The main board further comprises a first field programmable gate array chip arranged on the board body, and the first field programmable gate array chip is connected to the fourth pin group and can be electrically connected with the storage component. When the first transfer connector is connected to the redundant array of independent hard disk board, the fourth pin group is used for receiving the first low-speed signal output by the redundant array of independent hard disk board and transmitting the first low-speed signal to the first field programmable gate array chip. The first field programmable gate array chip is used for transmitting a first low-speed signal to the storage component.

The first pin group can be electrically connected with the first field programmable gate array chip, and further a first low-speed signal output by the independent hard disk redundant array chip can be transmitted to the first field programmable gate array chip through the fourth pin group, and then the first field programmable gate array chip can forward the first low-speed signal to the storage component, so that the independent hard disk redundant array chip can interact with the storage component in a low-speed signal.

In some implementations, the motherboard further includes a second field programmable gate array chip disposed on the board body and connected to the south bridge chip and the memory component. When the first transit connector is connected to the through board card, the south bridge chip is further configured to: and outputting a second low-speed signal. The second field programmable gate array chip is used for receiving a second low-speed signal and transmitting the second low-speed signal to the storage component.

The second field programmable gate array chip can be electrically connected with the south bridge chip and the storage component, so that the south bridge chip can transmit second low-speed signals to the second field programmable gate array chip, and the second field programmable gate array chip can transmit second low-speed signals to the storage component, so that interaction of the low-speed signals can be further performed between the south bridge chip and the storage component.

In another aspect, embodiments of the present application provide a computing device comprising: memory components, target boards, and motherboards provided by some of the implementations above. The target board card is a through board card or an independent hard disk redundant array board card. The first transfer connector of the main board is connected to the target board card. When the target board card connected with the first transfer connector is a through board card, the first pin group and the second pin group of the first transfer connector are coupled through the through board card, the south bridge chip of the main board is used for outputting SATA protocol signals, and the SATA protocol signals can be transmitted to the storage component through the first pin group, the through board card and the second pin group in sequence. When the target board card connected with the first transfer connector is an independent hard disk redundant array board card, the central processing unit of the main board is coupled with the independent hard disk redundant array board card, and the independent hard disk redundant array board card is coupled with the second pin group, wherein the central processing unit is used for sending PCIE protocol signals to the independent hard disk redundant array board card, the independent hard disk redundant array board card can convert the PCIE protocol signals into SAS protocol signals, and the SAS protocol signals can be transmitted to the storage component through the second pin group.

Under the condition that the target board card is a through board card or an independent hard disk redundant array board card, the main board can manage the storage component, so that the main board has higher compatibility. Therefore, the need to redesign the motherboard due to changing the target board card can be avoided, so that the cost can be saved. In addition, under the condition that the target board card is a through board card or the condition that the target board card is an independent hard disk redundant array board card, signals received by the target board card can be transmitted to the second pin group and transmitted to the storage component through the second pin group. Therefore, the second pin group and the connection link between the second pin group and the memory component can be multiplexed in both cases, so that the cost of the motherboard can be reduced.

In some implementations, the motherboard further includes a second adapter connector disposed on a board body of the motherboard and connected to the central processor. When the target board card connected with the first transfer connector is an independent hard disk redundant array board card, the independent hard disk redundant array board card is also connected with the second transfer connector, and PCIE protocol signals output by the central processing unit are sent to the independent hard disk redundant array board card through the second transfer connector.

In some implementations, the target board includes a switch circuit board, a first input pin set and a first output pin set, the first input pin set and the first output pin set are coupled and all disposed on the switch circuit board, and the first output pin set is connected to the second pin set. When the first transfer connector is connected to the through board card, the first input pin set is connected to the first pin set. When the first transfer connector is connected to the redundant array of independent hard disk board, the first input pin group is connected to the second transfer connector.

When the first transfer connector is connected to the redundant array of independent hard disk board, the first input pin set is connected to the second transfer connector. The second transfer connector is electrically connected to the central processor, and the first input pin set is electrically connected to the first pin set, so that PCIE protocol signals output by the central processor can be sequentially transmitted to the redundant array chip of the independent hard disk through the second transfer connector and the first input pin set. The independent hard disk redundant array chip can process PCIE protocol signals and convert the PCIE protocol signals into SAS protocol signals. When the central processing unit manages the hard disks through the independent hard disk redundant array chip, the independent hard disk redundant array chip can enable a plurality of hard disks to work in parallel, so that the data transmission rate is improved, and the safety of data can be improved.

When the first transfer connector is connected to the through board, the first input pin set is connected to the first pin set, and SATA protocol signals output by the south bridge chip can be sequentially transmitted to the storage component through the first pin set, the first input pin set, the first output pin set and the second pin set. At this time, the south bridge chip can manage a plurality of hard disks on the storage component, and the cost of the computing device is low.

In some implementations, when the target board is a redundant array of independent hard disks board, the target board further includes: the second output pin group is arranged on the switching circuit board and is electrically connected with the independent hard disk redundant array chip and the first pin group. And after the PCIE protocol signals are converted into SAS protocol signals by the independent hard disk redundant array chip, the SAS protocol signals are transmitted to the first output pin group and the second output pin group.

The SAS protocol signals received by the second output pin group are not required to be transmitted to the storage component through the second pin group, so that the SAS protocol signals output by the redundant array chip of the independent hard disk can be redundant, and the redundant SAS protocol signals can be transmitted to the first pin group through the second pin group.

In some implementations, the first transit connector further includes a first in-place pin, and the second transit connector further includes a second in-place pin; the target board card comprises a first voltage end and a third in-place pin which are arranged on the switching circuit board, and the first voltage end is connected with the third in-place pin; when the target board card is a through board card, the target board card comprises a third in-place pin which is connected with the first in-place pin. When the target board card is an independent hard disk redundant array board card, the target board card comprises two third in-place pins, wherein one third in-place pin is connected with the first in-place pin, and the other third in-place pin is electrically connected with the second in-place pin. The motherboard further comprises: voltage circuit and programmable logic device set on the board body. The voltage circuit is connected to the first in-place pin and the second in-place pin; the voltage circuit can enable the voltage of the first bit pin to be within a second voltage threshold range under the condition that the first bit pin is not connected to the third bit pin; under the condition that the first in-place pin is connected with the third in-place pin, the voltage circuit and the first voltage end jointly enable the voltage of the first in-place pin to be in a first voltage threshold range; in the case that the second bit pin is not connected to the third bit pin, the voltage circuit can enable the voltage of the second bit pin to be within a second voltage threshold range; the voltage circuit and the first voltage terminal together bring the voltage of the second bit pin within a first voltage threshold range under the condition that the second bit pin is connected with the third bit pin. The programmable logic device is connected to the first bit pin and the second bit pin, and the programmable logic device is used for: detecting the voltage of the first bit pin and the voltage of the second bit pin; under the condition that the voltage of the first in-place pin and the voltage of the second in-place pin are both in a first voltage threshold range, determining that the target board card connected with the first transfer connector is an independent hard disk redundant array board card; and under the condition that the voltage of the first bit pin is in a first voltage threshold range and the voltage of the second bit pin is in a second voltage threshold range, determining that the target board card connected with the first transfer connector is a through board card.

When the target board card connected with the first transfer connector of the main board is a through board card, the third in-place pin of the through board card can be electrically connected with the first in-place pin, and the second in-place pin is in a suspension state. At this time, the first bit pin may be electrically connected to the first voltage terminal through the third bit pin. In addition, the first bit pin may be electrically connected to the second voltage terminal through a resistor, and the voltage of the first bit pin may be the same as the voltage of the first voltage terminal under the combined action of the voltage circuit and the first voltage terminal. While the voltage of the second in-bit pin is within a second voltage threshold range. When the target board card connected with the first transfer connector of the main board is an independent hard disk redundant array board card, two third in-place pins of the independent hard disk redundant array board card are respectively and electrically connected with the first in-place pin and the second in-place pin. At this time, the first bit pin and the second bit pin may be electrically connected to the first voltage terminal and the voltage circuit. At this time, the voltages of the first bit pin and the second bit pin are both within the first voltage threshold range. Therefore, when the target board card is connected to the first transfer connector, the programmable logic device can automatically detect the type of the target board card.

In some implementations, the second transit connector includes a third pin set and a fourth pin set, the third pin set being connected to the central processor. The main board also comprises a first field programmable gate array chip arranged on the board body, and the first field programmable gate array chip is connected with the fourth pin group and the storage component. When the target board card is an independent hard disk redundant array board card, the target board card further comprises: the independent hard disk redundant array chip is arranged on the switching circuit board and connected with the first input pin group, the first output pin group and the second input pin group, and the second input pin group is electrically connected with the fourth pin group. The independent hard disk redundant array chip is used for outputting a first low-speed signal, and the first low-speed signal can be transmitted to the first field programmable gate array chip through the second input pin group and the fourth pin group. The first field programmable gate array chip is used for transmitting a first low-speed signal to the storage component.

The switching circuit board is provided with a second input pin group which is electrically connected with the independent hard disk redundant array chip, the board body is provided with a fourth pin group and a first field programmable gate array chip, and the first field programmable gate array chip can be electrically connected with the storage component, wherein the second input pin group can be electrically connected with the fourth pin group, so that a first low-speed signal output by the independent hard disk redundant array chip can be transmitted to the first field programmable gate array chip through the second input pin group and the fourth pin group, and then the first field programmable gate array chip can forward the first low-speed signal to the storage component, so that the independent hard disk redundant array chip can interact with the storage component through the low-speed signal.

In some implementations, when the target board is a redundant array of independent hard disks board, the target board further includes: the first input pin group is arranged on the fourth transfer connector; the third transfer connector is used for being plugged with the first transfer connector, and the fourth transfer connector is used for being plugged with the second transfer connector.

The third transfer connector is inserted with the first transfer connector, so that the connection relation between the third transfer connector and the first transfer connector is more stable, and the reliability of connection between the transfer circuit board and the board body can be improved. The fourth switching connector is inserted with the second switching connector, so that the connection relation between the fourth switching connector and the second switching connector is more stable, and the reliability of connection between the switching circuit board and the board body can be improved.

In some implementations, when the target board is a through board, the target board further includes a conductive member disposed on the transit circuit board, where one end of the conductive member is electrically connected to the first input pin set and the other end of the conductive member is electrically connected to the first output pin set.

The two ends of the conductive piece are respectively and electrically connected with the first input pin group and the first output pin group, so that SATA protocol signals received by the first input pin group from the first pin group can be transmitted to the first output pin group through the conductive piece.

In some implementations, when the target board is a pass-through board, the target board further includes a fifth switching connector, and the first input pin set and the first output pin set are both disposed on the fifth switching connector, where the fifth switching connector is configured to plug with the first switching connector.

The fifth transfer connector is inserted with the first transfer connector, so that the connection relationship between the fifth transfer connector and the first transfer connector is reliable, and the connection reliability of the target board card and the first transfer connector can be improved.

In some implementations, the motherboard further includes a second field programmable gate array chip disposed on the board body, connected to the south bridge chip and the memory component; the south bridge chip is used for: outputting a second low-speed signal and transmitting the second low-speed signal to a second field programmable gate array chip; the second field programmable gate array chip is configured to: the second low-speed signal is received and sent to the memory component.

In some implementations, the motherboard further comprises: the sixth switching connector is arranged on the main board and is connected with the second pin group. The storage component comprises a hard disk backboard and a plurality of hard disks, wherein the plurality of hard disks are spliced with the hard disk backboard, and the hard disk backboard is spliced with the sixth switching connector.

The second pin group is electrically connected with the sixth switching connector, and signals received by the second pin group can be transmitted to the hard disk backboard through the sixth switching connector. The sixth switching connector is spliced with the hard disk backboard, and the connection relationship between the sixth switching connector and the hard disk backboard is reliable.

Drawings

In order to more clearly illustrate the technical solutions of the present application, the drawings that are required to be used in some embodiments of the present application will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present application, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. according to the embodiments of the present application.

FIG. 1 is a schematic structural diagram of a computing device according to some embodiments;

FIG. 2 is a block diagram of a structure in which a target board in a computing device is a pass-through board, in accordance with some embodiments;

FIG. 3 is a block diagram of a configuration of a target board in a computing device as a redundant array of independent disks board in accordance with some embodiments;

FIG. 4 is another block diagram of the computing device of FIG. 3;

FIG. 5 is yet another block diagram of the computing device of FIG. 3;

FIG. 6 is yet another block diagram of the computing device of FIG. 4;

FIG. 7 is a further block diagram of the computing device of FIG. 4;

FIG. 8 is another block diagram of the computing device of FIG. 4;

FIG. 9 is another block diagram of the computing device of FIG. 2;

FIG. 10 is yet another block diagram of the computing device of FIG. 2;

FIG. 11 is a further block diagram of the computing device of FIG. 2;

FIG. 12 is a block diagram of a computing device with a first transit connector connected to a pass-through board;

FIG. 13 is a block diagram illustrating a configuration of a computing device when a first switch connector connects to a redundant array of independent disks chip;

FIG. 14 is another block diagram of a computing device according to some embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, unless the context requires otherwise, the word "comprise" and its other forms such as the third person referring to the singular form "comprise" and the present word "comprising" are to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "some embodiments," "example embodiments (exemplary embodiments)", "examples" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

FIG. 1 is a schematic structural diagram of a computing device according to some embodiments.

Referring to FIG. 1, some embodiments of the application provide a computing device 1000, which computing device 1000 may be a general purpose computing device or a special purpose computing device, for example. By way of example, computing device 1000 may be a server, desktop, or the like. Embodiments of the application are not limited to the type of computing device 1000.

Computing device 1000 is illustrated in fig. 1 by taking computing device 1000 as a server.

Referring to fig. 1, a computing device 1000 includes a housing 110, a switching power supply, and a plurality of loads (not shown in fig. 1). The case 110 includes an accommodating space, and the switching power supply and the plurality of loads may be disposed in the accommodating space of the case 110.

For example, the case 110 may include a case body and a cover body coupled to each other to enclose the receiving space. The connection mode between the box main body and the cover body can be detachable connection, and at the moment, all parts in the box main body can be exposed by opening the cover body. The connection mode between the box main body and the cover body can be clamping connection. Besides, the box main body and the cover body can be detachably connected through structures such as screws, bolts and pins.

For example, the case body may include a bottom plate and a plurality of side plates, wherein the plurality of side plates may be disposed along edges of the bottom plate, and the plurality of side plates may be perpendicular to the bottom plate, and the bottom plate and the cover are disposed at opposite sides of the plurality of side plates, respectively.

The switching power supply can be electrically connected with an alternating current power grid, can convert alternating current received by the alternating current power grid into direct current and transmit the direct current to a plurality of loads, and therefore the loads are powered.

By way of example, loads may include CPU (Central Processing Unit ), DIMM (Dual Inline Memory Modules, dual in-line memory module) memory, GPU (Graphics Processing Unit, graphics processor), hard disk 120, fan, network card, PCIE (Peripheral Component Interconnect Express, peripheral interconnect bus) tag card, CPLD (Complex Programmable Logic Device ) and BMC (Baseboard Manager Controller, baseboard management controller), PCH (Platform Controller Hub, south bridge chip) and RAID (Redundant Array of Independent Disks ) chips, etc., not to mention.

As shown in fig. 1, the computing device 1000 may include a plurality of hard disks 120, where a plurality of hard disk mounting slots are provided on the case 110, and the hard disks 120 may be located in the hard disk mounting slots, and the number of the hard disks 120 may be 2, 4, 6, 8, or the like, which is not specifically mentioned herein, and in some embodiments of the present application, the number of the hard disks 120 is not limited.

Wherein the storage capacity of the computing device 1000 may be increased by providing a plurality of hard disks 120 in the computing device 1000.

The manner in which different computing devices 1000 manage the hard disk 120 may be different.

For example, some computing devices 1000 may support a RAID management approach in which a CPU may be electrically connected to a RAID chip that is electrically connected to the hard disk 120, thereby enabling the CPU to manage the hard disk 120.

For another example, some computing devices 100 support a pass-through management scheme in which a south bridge chip is electrically connected to a hard disk, so that the south bridge chip can manage the hard disk.

In the related art, two kinds of signal transmission links may be provided in the computing device 1000, so that the computing device 1000 can support two management modes, but the cost of a server is high due to the completely different signal transmission links of the two management modes.

Based thereon, embodiments of the present application provide a computing device 1000.

Fig. 2 is a block diagram of a structure when a target board 400 in a computing device 1000 is a pass-through board 401, according to some embodiments.

Referring to fig. 2, a computing device 1000 includes a motherboard 300, a target board card 400, and a storage component 500.

In some examples, storage component 500 may include hard disk backplane 150 and a plurality of hard disks 120, wherein hard disk backplane 150 may be electrically connected to second pin set 342 and plurality of hard disks 120 may be plugged with hard disk backplane 150. By way of example, the number of hard disks 120 may be 2, 3, 4, 5, 6 or even more, which are not listed here. In fig. 2, only 4 hard disks 120 are taken as an example, and some embodiments of the present application are illustrated, which do not limit the number of hard disks 120.

The motherboard 300 includes a board body 310, a south bridge chip 320 disposed on the board body 310, a central processing unit 330 and a first conversion connector 340. Wherein the first transit connector 340 includes a first pin group 341 and a second pin group 342; the first pin set 341 is connected to the south bridge chip 320, and the second pin set 342 may be coupled to the memory module 500.

In some examples, the board 310 is provided with conductive wires, and the south bridge chip 320 is electrically connected to the first pin group 341, so that signals output by the south bridge chip 320 can be transmitted to the first pin group 341.

The target board 400 may be a pass-through board 401 or a redundant array of independent hard disks board (not shown in fig. 2).

The first conversion connector 340 of the motherboard 300 may be used to couple with the target board 400, and the management of the computing device 1000 may be different when the types of the target boards 400 connected by the first conversion connector 340 are different.

For example, when the target board 400 connected to the first conversion connector 340 is the pass-through board 401, the hard disk management mode of the computing device 1000 is the pass-through management mode, and at this time, the south bridge chip 320 can manage the plurality of hard disks 120 of the storage component 500.

For another example, when the target board 400 connected to the first conversion connector 340 is an independent hard disk redundancy array board, the hard disk management mode of the computing device 1000 is a RAID management mode, and at this time, the central processor 330 may manage the plurality of hard disks 120 of the storage assembly 500.

When the target board 400 connected to the first conversion connector 340 is the through board 401, the first pin group 341 and the second pin group 342 of the first conversion connector 340 are coupled through the through board 401, and the south bridge chip 320 of the motherboard 300 is configured to output SATA protocol signals, which can be sequentially transmitted to the storage component 500 through the first pin group 341, the through board 401 and the second pin group 342. At this time, the south bridge chip 320 may manage the plurality of hard disks 120 of the storage assembly 500.

Fig. 3 is a block diagram of a configuration of a computing device 1000 in which a target board 400 is a redundant array of independent disks board 402, in accordance with some embodiments.

Referring to fig. 3, when the target board 400 connected to the first conversion connector 340 is the hdd redundancy array board 402, the central processor 330 of the motherboard 300 is coupled to the hdd redundancy array board 402, and the hdd redundancy array board 402 is coupled to the second pin set 342, wherein the central processor 330 is configured to send PCIE protocol signals to the hdd redundancy array board 402, and the hdd redundancy array board 402 is capable of converting PCIE protocol signals into SAS protocol signals, and the SAS protocol signals are capable of being transmitted to the storage component 500 through the second pin set 342.

The PCIE protocol signal, the SAS protocol signal, and the SATA protocol signal are all high-speed signals.

Referring to fig. 2 and fig. 3, in the case where the target board 400 is the through board 401 or the target board 400 is an independent hard disk redundancy array board, the motherboard 300 can manage the storage component 500, so that the motherboard 300 has higher compatibility. Accordingly, redesigning the motherboard 300 due to changing the target board 400 can be avoided, whereby costs can be saved.

In addition, in the case where the target board 400 is the through board 401, or in the case where the target board 400 is an independent hard disk redundancy array board, the signals received by the target board 400 may be transmitted to the second pin group 342, and transmitted to the memory assembly 500 through the second pin group 342. Accordingly, the second pin group 342, and the connection link between the second pin group 342 and the memory assembly 500 can be multiplexed in both cases, so that the cost of the motherboard 300 can be reduced.

Fig. 4 is another block diagram of the computing device 1000 of fig. 3.

Referring to fig. 4, the motherboard 300 further includes: the second adaptor connector 350 is disposed on the board 310, and the second adaptor connector 350 is connected to the cpu 330.

For example, the cpu 330 may be electrically connected to the second transit connector 350 through conductive traces on the board 310.

When the first switch connector 340 is connected to the hdd redundancy array board 402, the hdd redundancy array board 402 is further connected to the second switch connector 350, and PCIE protocol signals output by the cpu 330 can be transmitted to the hdd redundancy array board 402 through the second switch connector 350.

The second switch connector 350 is electrically connected to the cpu 330, and the second switch connector 350 may be electrically connected to the redundant array of independent disks board 402, so that PCIE protocol signals generated by the cpu 330 may be transmitted to the redundant array of independent disks board 402 through the second switch connector 350.

Fig. 5 is a further block diagram of a structure of the computing device 1000 of fig. 3.

Referring to fig. 5, in some implementations, the target board 400 includes a switch circuit board 410, a first input pin set 420 and a first output pin set 430, the first input pin set 420 and the first output pin set 430 are coupled and are disposed on the switch circuit board 410, and the first output pin set 430 is connected to the second pin set 342.

If the target board 400 is the hdd redundancy array board 402, the target board 400 may further include an hdd redundancy array chip 440, and the hdd redundancy array chip 440 is electrically connected between the first input pin set 420 and the first output pin set 430.

When the first transit connector 340 is connected to the redundant array of independent disks board 402, the first input pin set 420 is connected to the second transit connector 350. The second switch connector 350 is electrically connected to the cpu 330, and the first input pin set 420 is electrically connected to the first input pin set 420, so that PCIE protocol signals output by the cpu 330 can be sequentially transmitted to the redundant array of independent hard disks chip 440 through the second switch connector 350 and the first input pin set 420. The redundant array of independent disks chip 440 may process PCIE protocol signals to convert PCIE protocol signals to SAS protocol signals.

When the central processor 330 manages the hard disks 120 through the redundant array of independent disks chip 440, the redundant array of independent disks chip 440 can make multiple hard disks 120 work in parallel, improving the data transmission rate and improving the security of data.

Fig. 6 is a further block diagram of a structure of the computing device 1000 of fig. 4.

Referring to fig. 6, in one implementation, the second transit connector 350 includes a third pin set 351 and a fourth pin set 352, where the third pin set 351 is connected to the cpu 330.

Motherboard 300 further includes a first field programmable gate array chip 360 disposed on board body 310, first field programmable gate array chip 360 being connected to fourth pin set 352 and memory assembly 500.

When the target board 400 is the redundant array of independent hard disks board 402, the target board 400 further includes: the second input pin group 450 is electrically connected to the redundant array of independent disks chip 440, and the second input pin group 450 is electrically connected to the fourth pin group 352.

The redundant array of independent disks chip 440 is configured to output a first low-speed signal, which can be transmitted to the first field programmable gate array chip 360 through the second input pin set 450 and the fourth pin set 352.

The first field programmable gate array chip 360 is used to transmit a first low-speed signal to the memory assembly 500.

The fourth pin group 352 may include a plurality of fourth pins, a portion of the fourth pins are electrically connected to the first field programmable gate array chip 360, the second input pin group 450 includes a plurality of low-speed pins, the plurality of low-speed pins are all electrically connected to the redundant array of independent hard disks chip 440, and the plurality of low-speed pins are in one-to-one correspondence with and electrically connected to the plurality of fourth pins.

In some examples, the storage assembly 500 may further include a third field programmable gate array chip and light emitting devices in one-to-one correspondence with the plurality of hard disks 120, and the third field programmable gate array chip and the plurality of light emitting devices may be disposed on the hard disk back plate 150. The third field programmable gate array chip may be electrically connected with the first field programmable gate array chip 360.

In some examples, motherboard 300 may further include a first low-speed interface disposed on board body 310 and electrically connected to first field programmable gate array chip 360. The storage assembly 500 further includes a second low-speed interface, which may be disposed on the hard disk backplate 150 and electrically connected to the third field programmable gate array chip, wherein the first low-speed interface may be electrically connected to the second low-speed interface, and further the first field programmable gate array chip 360 may send the first low-speed signal to the first low-speed interface and to the third field programmable gate array chip through the second low-speed interface. The third field programmable gate array chip may process the first low-speed signal.

The first low-speed interface may be plugged with the second low-speed interface, or the first low-speed interface and the second low-speed interface may be connected through a cable.

In some examples, the first low-speed signal Output by the redundant array of independent hard disks chip 440 may include a hard disk lighting signal, a hard disk in-place signal, and the like, and the hard disk lighting signal may be an SGPIO (Serial General Purpose Input/Output, serial universal input Output) protocol signal, for example.

For example, the redundant array of independent hard disks chip 440 may send the lighting signal to the first field programmable gate array chip 360, and the first field programmable gate array chip 360 may forward the lighting signal to the third field programmable gate array chip, and the third field programmable gate array chip may process the lighting signal to generate a plurality of sub-lighting signals, and transmit the plurality of sub-lighting signals to the light emitting devices corresponding to the plurality of hard disks 120, respectively, where the sub-lighting signals may be used to light the light emitting devices, and if the hard disk 120 corresponding to the light emitting device is in place, the sub-lighting signal outputted by the third field programmable gate array chip may light the light emitting device, and if the hard disk 120 corresponding to the light emitting device is not in place, the sub-lighting signal may not light the light emitting device.

By providing the second input pin group 450 electrically connected to the redundant array of independent hard disks chip 440 on the switch circuit board 410, providing the fourth pin group 352 on the second switch connector 350 and providing the first field programmable gate array chip 360 on the board 310, the first field programmable gate array chip 360 may be electrically connected to the memory module 500, wherein the second input pin group 450 may be electrically connected to the fourth pin group 352, so that the first low-speed signal output by the redundant array of independent hard disks chip 440 may be transmitted to the first field programmable gate array chip 360 through the second input pin group 450 and the fourth pin group 352, and then the first field programmable gate array chip 360 may forward the first low-speed signal to the memory module 500, so that the redundant array of independent hard disks chip 440 may perform interaction of the low-speed signal with the memory module 500.

In some examples, the fourth pin set 352 includes a plurality of fourth pins of the first type that are electrically connected to the first field programmable gate array chip 360; the second input pin group 450 includes a plurality of first type second input pins, and the plurality of first type second input pins are used for being in one-to-one correspondence with and electrically connected to a plurality of first type fourth pins.

In some examples, fourth pin set 352 may further include a plurality of fourth pins of the second class; the board 310 may further be provided with a power supply end, where the plurality of second class fourth pins may be electrically connected to the power supply end, and further the plurality of second class fourth pins may receive a power supply signal provided by the power supply end.

Correspondingly, the second input pin group 450 may further include a plurality of second type second input pins, and the plurality of second type second input pins may be electrically connected to the redundant array of independent disks chip 440. In addition, the plurality of second-type second input pins may be electrically connected to the plurality of second-type fourth pins, so that the power supply signal received by the second-type fourth pins may be transmitted to the second-type second input pins, and transmitted to the redundant array of independent hard disks chip 440 through the second-type second input pins, thereby supplying power to the redundant array of independent hard disks chip 440.

Fig. 7 is a further block diagram of a structure of the computing device 1000 of fig. 4.

Referring to fig. 7, in some implementations, when the target board 400 is a redundant array of independent hard disks board 402, the target board 400 further includes: a second set of output pins 460. The second output pin group 460 is electrically connected to the redundant array of independent hard disks chip 440 and the first pin group 341.

After the redundant array of independent disks chip 440 converts the PCIE protocol signal into the SAS protocol signal, the SAS protocol signal may be transmitted to the first output pin group 430 and the second output pin group 460.

In some implementations, the south bridge chip 320 is configured to: when the target board 400 connected to the first conversion connector 340 is the redundant array of independent hard disk board 402, the SATA protocol signal is stopped from being outputted.

When the target board 400 connected to the first transit connector 340 is the redundant array of independent hard disks board 402, the second output pin set 460 may be electrically connected to the first pin set 341, and further SAS protocol signals may be transmitted from the second output pin set 460 to the first pin set 341. In addition, the first pin set 341 may be electrically connected to the south bridge chip 320, and further, SATA protocol signals output by the south bridge chip 320 may also be transmitted to the first pin set 341. When the target board 400 connected to the first conversion connector 340 is the hdd redundancy array board 402, the south bridge chip 320 can stop outputting SATA protocol signals, so as to avoid collision between the SAS protocol signals output by the hdd redundancy array chip 440 and the SATA protocol signals output by the south bridge chip 320 on the first pin group 341, and generate interference to signals on other pin groups.

In addition, the SAS protocol signals received by the second output pin set do not need to be transmitted to the storage component through the second pin set 342, so that the SAS protocol signals output by the redundant array of independent hard disks chip 440 can be redundant, and the redundant SAS protocol signals can be transmitted to the first pin set 341 through the second pin set 342, and at this time, the first pin set 341 can receive not only the redundant SAS protocol signals transmitted by the second output pin set 460, but also SATA protocol signals transmitted by the south bridge chip 320, so that at least some pins in the first pin set 341 can be multiplexed, thereby reducing the number of pins on the first conversion connector 340.

In other implementations, all SAS protocol signals output by the redundant array of independent hard disk chip 440 may be transmitted to the first output pin group 430.

Fig. 8 is another block diagram of a configuration of the computing device 1000 of fig. 4.

Referring to fig. 8, when the target board 400 is the redundant array of independent hard disks board 402, the target board 400 further includes: the third transfer connector 403 and the fourth transfer connector 404, the first output pin set 430 is disposed on the third transfer connector 403, and the first input pin set 420 is disposed on the fourth transfer connector 404.

The third transfer connector 403 is configured to be plugged with the first transfer connector 340, and the fourth transfer connector 404 is configured to be plugged with the second transfer connector 350.

When the third transfer connector 403 is plugged with the first transfer connector 340, the plurality of pins in the first output pin set 430 are electrically connected to the plurality of pins in the second pin set 342 in a one-to-one correspondence.

In some examples, the target board card 400 further includes a second set of output pins 460, the second set of output pins 460 may be provided for the third transit connector 403.

The third transferring connector 403 is plugged with the first transferring connector 340, so that the connection relationship between the third transferring connector 403 and the first transferring connector 340 is more stable, and the reliability of the connection between the transferring circuit board 410 and the board body 310 can be improved.

When the fourth transit connector 404 is plugged with the second transit connector 350, the plurality of pins in the first input pin group 420 are electrically connected to the plurality of pins in the third pin group 351 in a one-to-one correspondence manner, and the plurality of pins in the second input pin group 450 are electrically connected to the plurality of pins in the fourth pin group 352 in a one-to-one correspondence manner.

The fourth adaptor connector 404 is plugged with the second adaptor connector 350, so that the connection relationship between the fourth adaptor connector 404 and the second adaptor connector 350 is more stable, and the reliability of the connection between the adaptor circuit board 410 and the board body 310 can be improved.

By way of example, the third transition connector 403 and the fourth transition connector 404 may be one of a connector male and connector female, while the first transition connector 340 and the second transition connector 350 may be the other of a connector male and connector female.

Next, the structure of the connector female and connector male will be described.

Wherein, the female head of the connector includes a connector base and a plurality of pins, wherein, the connector base sets up on the plate 310, and is provided with the grafting recess on the connector base, and a plurality of pins set up in the grafting recess.

The connector male head comprises a plug-in part and a plurality of pins arranged on the plug-in part, the pins are arranged on the plug-in parts, and when the plug-in parts are plugged in the plug-in grooves, the pins on the plug-in parts are in one-to-one correspondence with the pins in the plug-in grooves and are electrically connected.

In some examples, the third transit connector 403 and the fourth transit connector 404 may be disposed on one side of the transit circuit board 410, so that the third transit connector 403 may be plugged with the first transit connector 340, and the fourth transit connector 404 may be plugged with the second transit connector 350. The interposer circuit board 410 may be perpendicular to the board body 310.

By way of example, the first transit connector 340, the second transit connector 350, the third transit connector 403, and the fourth transit connector 404 may all be AIRMAX connectors.

By way of example, an AIRMAX connector may have 72 pins, 96 pins, or even more pins.

In some examples, the first and second transit connectors 340, 350 may be an air max connector female, while the third and fourth transit connectors 403, 404 may be an air max connector male.

For example, the third and fourth transit connectors 403 and 404 may be AIRMAX connector male heads and the first and second transit connectors 340 and 350 may be AIRMAX connector female heads. By the arrangement, the plug-in connection of the AIRMAX connector male head and the AIRMAX connector female head can be facilitated.

In some examples, the third pin group 351 includes a plurality of third pins, each of the plurality of third pins is electrically connected to the central processor 330, and each of the plurality of third pins is configured to transmit one PCIE protocol signal. For example, a set of third pins may include 4 third pins.

In some examples, the third pin group 351 further includes a ground pin, and the ground pin is disposed between two adjacent third pins, so as to reduce interference generated by PCIE protocol signals transmitted on the two adjacent third pins.

PCIE protocol signals may be transmitted from third pin group 351 to first input pin group 420, where corresponding first input pin group 420 includes multiple groups of first input pins, each group of first input pins may be used to transmit one PCIE protocol signal, and each group of first input pins may include 4 first input pins. The plurality of first input pins are electrically connected to the redundant array of independent hard disks chip 440, so that PCIE protocol signals received by the plurality of first input pins can be transmitted to the redundant array of independent hard disks chip 440.

In some examples, the first input pin group 420 further includes a ground pin, and a ground pin may be disposed between two adjacent first input pins, so that interference generated between PCIE protocol signals transmitted on the two adjacent first input pins may be reduced.

The redundant array of independent disks chip 440 may convert one PCIE protocol signal into one SAS protocol signal, and for example, after the redundant array of independent disks chip 440 receives 8 PCIE protocol signals, the redundant array of independent disks chip 440 may convert the 8 PCIE protocol signals into 8 SAS protocol signals.

SAS protocol signals generated by the redundant array of independent disks chip 440 may be transmitted to the first output pin set 430. The first output pin set 430 may include multiple sets of first output pins, one SAS protocol signal occupying 4 first output pins, and one set of first output pins including four first output pins.

In some examples, the first output pin group 430 further includes a plurality of ground pins, and the ground pins are disposed between two adjacent first output pins, so as to reduce interference between SAS protocol signals transmitted on the two adjacent first output pins.

In some examples, SAS protocol signals generated by the redundant array of independent hard disks chip 440 may also be transmitted to a second output pin group 460, where the second output pin group 460 may include multiple sets of second output pins, and one set of second output pins may include 4 second output pins.

In some examples, the second output pin group 460 may further include a plurality of ground pins, and a ground pin may be disposed between two adjacent second output pins, so as to reduce interference generated between two adjacent second output pins.

The second pin group 342 includes a plurality of second pins, and the second pin group 342 may be used to transmit SAS protocol signals, one set of second pins is used to transmit one SAS protocol signal, and one set of second pins includes 4 second pins. The plurality of sets of second pins may be electrically connected to the hard disk backplate 150.

In some examples, the first conversion connector 340 is further provided with a ground pin, so that interference generated between SAS protocol signals transmitted on two adjacent sets of second pins may be reduced.

One PCIE protocol signal may control one hard disk 120, in some examples, the number of PCIE protocol signals generated by the central processing 330 may be the same as the number of hard disks 120, and in other examples, the number of PCIE protocol signals generated by the central processing 330 may be greater than the number of hard disks 120.

Some embodiments of the present application are described below with respect to the example that the number of PCIE protocol signals generated by the central processing unit 330 may be greater than the number of hard disks 120.

For example, the central processing 330 may generate 8 PCIE protocol signals, and the number of hard disks 120 is 6.

At this time, the third pin group 351 may be provided with 8 groups of third pins, the first input pin group 420 includes 8 groups of first input pins, the 8 PCIE protocol signals generated by the central processing unit 330 may be transmitted to the 8 groups of third pins, and the 8 groups of third pins may respectively transmit the 8 PCIE protocol signals to the 8 groups of first input pins, and are transmitted to the redundant array chip 440 of the independent hard disk through the 8 groups of first input pins.

The redundant array of independent disks chip 440 may convert 8 PCIE protocol signals to 8 SAS protocol signals.

The first output pin set 430 may include 6 sets of first output pins and the second output pin set 460 may include at least 2 sets of second output pins, wherein 6 SAS protocol signals may be transmitted to 6 sets of first output pins in the first output pin set 430 and 2 SAS protocol signals may be transmitted to two sets of second output pins in the second output pin set 460. The 2 SAS protocol signals do not correspond to the hard disk 120 to be controlled.

The second pin set 342 may include 6 sets of second pins, the 6 SAS protocol signals transmitted to the 6 sets of first output pins may be transmitted to the 6 sets of second pins, and the 6 sets of second pins may transmit the 6 SAS protocol signals to the storage component 500, so as to manage the 6 hard disks 120 in the SAS protocol signals.

In the related art, the redundant array of independent disks chip 440 may convert 8 PCIE protocol signals into 8 SAS protocol signals. The above-mentioned redundant array of independent hard disk board 402 may also be applied to the computing device 1000 having 8 hard disks 120 by transmitting the 8 SAS protocol signals generated by the redundant array of independent hard disks chip 440 to the first output pin group 430 and the second output pin group 460, respectively, so that the versatility of the redundant array of independent hard disks board 402 may be improved.

In the above embodiments, the target board 400 is an independent hard disk redundant array board 402, and some embodiments of the present application are described below, and when the target board 400 is a pass-through board 401, some embodiments of the present application are described below.

Fig. 9 is another block diagram of the computing device 1000 of fig. 2.

Referring to fig. 9, in some implementations, the target board 400 includes a switch circuit board 410, a first input pin set 420 and a first output pin set 430, the first input pin set 420 and the first output pin set 430 are coupled and are disposed on the switch circuit board 410, and the first output pin set 430 is connected to the second pin set 342. When the first transit connector 340 is connected to the through board 401 (i.e., when the target board 400 is the through board 401), the first input pin group 420 is connected to the first pin group 341.

The SATA protocol signal output by the south bridge chip 320 may be sequentially transmitted to the storage module 500 through the first pin set 341, the first input pin set 420, the first output pin set 430, and the second pin set 342. At this time, the south bridge chip 320 may manage the plurality of hard disks 120 on the storage component 500, and the cost of the computing device 1000 is low.

With continued reference to fig. 9, in some implementations, when the target board 400 is a through board 401, the target board 400 further includes a conductive member 470 disposed on the transit circuit board 410, where one end of the conductive member 470 is electrically connected to the first input pin set 420 and the other end is electrically connected to the first output pin set 430.

The two ends of the conductive member 470 are electrically connected to the first input pin set 420 and the first output pin set 430, respectively, so that SATA protocol signals received by the first input pin set 420 from the first pin set 341 can be transmitted to the first output pin set 430 through the conductive member 470.

In some examples, the first input pin set 420 includes a plurality of first input pins, the first output pin set 430 includes a plurality of first output pins, and the conductive member 470 may include a plurality of conductive connection lines. The plurality of first input pins can be electrically connected with the plurality of first output pins through the plurality of conductive connecting wires respectively, so that signals received by the first input pins can be transmitted to the corresponding first output pins.

In some examples, each SATA protocol signal may occupy 4 pins, and one SATA protocol signal may control one hard disk 120.

For example, the first pin group 341 may include a plurality of first pins, and each of the plurality of first pins may be electrically connected to the south bridge chip 320. A set of first pins may be used to transmit one SATA protocol signal and a set of first pins may include 4 first pins.

The first pin group 341 further includes a plurality of grounding pins, and one grounding pin is disposed between two adjacent first pin groups. By the arrangement, interference generated between SATA protocol signals transmitted on two adjacent groups of first pins can be reduced.

In some examples, the first input pin group 420 may include a plurality of first input pins, which are in one-to-one correspondence with and electrically connected to the plurality of first pins, and for example, the number of first input pins may be the same as the number of first pins.

The first input pin set 420 may include a plurality of sets of first input pins, one set of first input pins may include 4 first input pins, and one set of first input pins may be used to transmit one SATA protocol signal.

In some examples, the first input pin group 420 further includes a plurality of ground pins, and one ground pin is disposed between two adjacent first input pins. The ground pin in the first input pin set 420 is electrically connected to the first input pin in the first pin set 341. The interference generated between SATA protocol signals transmitted by two adjacent groups of first input pins can be reduced by arranging the grounding pins.

The first output pin set 430 may include a plurality of sets of first output pins, one set of first output pins may include 4 first output pins, and one set of first output pins may be used to transmit one SATA protocol signal.

In some examples, the second pin set 342 includes a plurality of second pins, and the plurality of second pins may be in one-to-one correspondence with and electrically connected to the plurality of first output pins, where the number of first output pins is the same as the number of second pins, and SATA protocol signals received by the first output pin set 430 may be all transmitted to the second pin set 342.

In some examples, one SATA protocol signal may control the same number of SATA protocol signals as the hard disk 120, and the number of SATA protocol signals output by the south bridge chip 320 may be the same as the number of hard disks 120.

For example, when the number of hard disks 120 is 6, the south bridge chip 320 may output 6 SATA protocol signals, and the 6 SATA protocol signals need to occupy 6 groups of pins. At this time, the number of the first pins is 24, the number of the first input pins is 24, the number of the first output pins is 24, and the number of the second pins is 24.

In some examples, the south bridge chip 320 may include a first output unit and a second output unit, wherein the first output unit may be electrically connected to 8 first pins, and the first output unit is configured to output 2 SATA protocol signals. And the second output unit can be electrically connected with 16 first pins and is used for outputting 4 SATA protocol signals.

Fig. 10 is a further block diagram of a structure of the computing device 1000 of fig. 2.

Referring to fig. 10, in some implementations, when the target board 400 is a through board 401, the target board 400 further includes a fifth switching connector 405, and the first input pin group 420 and the first output pin group 430 are disposed on the fifth switching connector 405, where the fifth switching connector 405 is configured to plug with the first switching connector 340.

The fifth transfer connector 405 is plugged with the first transfer connector 340, so that the connection relationship between the fifth transfer connector 405 and the first transfer connector 340 is reliable, and the reliability of the connection between the target board 400 and the first transfer connector 340 can be improved.

In some examples, the fifth transit connector 405 may be disposed on one side of the transit circuit board 410, such that the fifth transit connector 405 may be conveniently plugged with the first transit connector 340.

When the fifth transferring connector 405 is plugged with the first transferring connector 340, the first pin group 341 is electrically connected with the first input pin group 420, and the second pin group 342 is electrically connected with the first output pin group 430.

Illustratively, the first transit connector 340 may be a connector female and the fifth transit connector 405 may be a connector male. For example, the first transit connector 340 is an AIRMAX connector female and the fifth transit connector 405 is an AIRMAX connector male.

Fig. 11 is a further block diagram of a structure of the computing device 1000 of fig. 2.

Referring to fig. 11, in some implementations, the motherboard 300 further includes a second field programmable gate array chip 370 disposed on the board body 310 and connected to the south bridge chip 320 and the memory module 500. The south bridge chip is used for: the second low-speed signal is output and transmitted to the second field programmable gate array chip 370. The second field programmable gate array chip 370 is for: the second low-speed signal is received and transmitted to the memory assembly 500.

In some examples, the storage assembly 500 may further include a third field programmable gate array chip and light emitting devices in one-to-one correspondence with the plurality of hard disks 120, and the third field programmable gate array chip and the plurality of light emitting devices may be disposed on the hard disk back plate 150. The third field programmable gate array chip may be electrically connected to the second field programmable gate array chip 370. The third field programmable gate array chip has been processed above and will not be described here.

In some examples, the second low-speed signal may include a hard disk lighting signal, a hard disk in-place signal, etc., and the lighting signal may be an SGPIO (Serial General Purpose Input/Output, serial universal input Output) protocol signal, for example.

For example, the south bridge chip 320 may send the lighting signal to the second field programmable gate array chip 370, and the second field programmable gate array chip 370 may forward the lighting signal to the memory component 500.

The third field programmable gate array chip of the storage assembly 500 may process the light-emitting signal to generate a plurality of sub-lighting signals, and transmit the sub-lighting signals to the light emitting devices corresponding to the plurality of hard disks 120, respectively, where the sub-lighting signals may be used to light the light emitting devices, and if the hard disk 120 corresponding to the light emitting device is in place, the sub-lighting signals may light the light emitting devices, and if the hard disk 120 corresponding to the light emitting device is not in place, the sub-lighting signals may not light the light emitting devices.

In some examples, the second field programmable gate array chip 370 provided in fig. 11 may be the same FPGA chip as the first field programmable gate array chip 360 in fig. 6, which may be electrically connected to the south bridge chip 320 and the central processor 330. By this arrangement, the number of chips and interfaces on the board 310 may be reduced, thereby reducing the cost of the computing device 1000.

The connection manner between the first field programmable gate array chip 360 and the second field programmable gate array chip is described above, and will not be described herein.

The second field programmable gate array chip 370 is configured, and the second field programmable gate array chip 370 can be electrically connected with the south bridge chip 320 and the storage component 500, so that the south bridge chip 320 can transmit the second low-speed signal to the second field programmable gate array chip 370, and the second field programmable gate array chip 370 can transmit the second low-speed signal to the storage component 500, so that interaction of the low-speed signal between the south bridge chip 320 and the storage component 500 can be performed.

Fig. 12 is a block diagram of a computing device 1000 with a first transit connector 340 connected to a pass-through board 401; fig. 13 is a block diagram of a computing device 1000 when the first switch connector 340 is connected to the redundant array of independent disks chip 440.

Referring to fig. 12 and 13, in some implementations, the first transit connector 340 further includes a first in-place pin 343 and the second transit connector 350 further includes a second in-place pin 353.

The target board 400 includes a first voltage terminal 490 and a third in-place pin 480 disposed on the interposer circuit board 410, and the first voltage terminal 490 is connected to the third in-place pin 480.

Referring to fig. 12, when the target board 400 is a pass-through board 401, the target board 400 includes a third in-place pin 480, and the third in-place pin 480 is connected to the first in-place pin 343. At this time, the number of the first bit pins 343 may be one or more, and in fig. 12, the number of the first bit pins 343 is taken as an example, and some implementations of the present application are described.

Referring to fig. 13, when the target board 400 is the redundant array of independent hard disks board 402, the target board 400 includes two third in-place pins 480, wherein one third in-place pin 480 is connected to the first in-place pin 343, and the other third in-place pin 480 is electrically connected to the second in-place pin 353. For example, two third in-place pins 480 may be disposed on the third transit connector 403 and the fourth transit connector 404, respectively.

The plate 310 further includes: a voltage circuit 380 and a programmable logic device 390 disposed on the board 310.

The voltage circuit 380 is connected to the first bit pin 343 and the second bit pin 353; wherein, in a case where the first bit pin 343 is not connected to the third bit pin 480, the voltage circuit 380 is capable of making the voltage of the first bit pin 343 within the second voltage threshold range; with the first bit pin 343 connected to the third bit pin 480, the voltage circuit 380 and the first voltage terminal 490 together bring the voltage of the first bit pin 343 within a first voltage threshold range; in the event that the second bit pin 353 is not connected to the third bit pin 480, the voltage circuit 380 can bring the voltage of the second bit pin 353 within a second voltage threshold range; with the second bit pin 353 connected to the third bit pin 480, the voltage circuit 380 and the first voltage terminal 490 together bring the voltage of the second bit pin 353 within a first voltage threshold range.

For example, any voltage value in the second voltage threshold range is greater than any voltage value in the first voltage threshold range.

For example, the first voltage terminal 490 may be a ground terminal.

For example, the voltage circuit 380 may include a second voltage terminal and a resistor having one end electrically connected to the second voltage terminal and the other end electrically connected to the first bit pin 343 and the second bit pin 353. For example, the voltage of the voltage signal provided by the second voltage terminal is greater than the voltage of the voltage signal provided by the first voltage terminal 490.

For example, the first voltage terminal 490 may be a power terminal.

The programmable logic device 390 is connected to the first bit pin 343 and the second bit pin 353, and the programmable logic device 390 is configured to: detecting a voltage of the first bit pin 343 and a voltage of the second bit pin 353; in addition, in the case that the voltage of the first in-place pin 343 and the voltage of the second in-place pin 353 are both within the first voltage threshold range, it is determined that the target board 400 connected to the first conversion connector 340 is the independent hard disk redundant array board 402; in the case that the voltage of the first bit pin 343 is within the first voltage threshold range and the voltage of the second bit pin 353 is within the second voltage threshold range, the target board 400 to which the first conversion connector 340 is connected is determined to be the through board 401.

When the target board 400 connected to the first conversion connector 340 of the motherboard 300 is the through board 401, the third in-place pin 480 of the through board 401 may be electrically connected to the first in-place pin 343, and the second in-place pin 353 is in a suspended state. At this time, the first bit pin 343 may be electrically connected to the first voltage terminal 490 through the third bit pin 480. In addition, the first bit pin 343 may be electrically connected to the second voltage terminal through a resistor, and the voltage of the first bit pin 343 may be the same as the voltage of the first voltage terminal 490 under the combined action of the voltage circuit 380 and the first voltage terminal 490, where the voltage of the first bit pin 343 is within the first voltage threshold range. While the voltage of the second bit pin 353 is within the second voltage threshold range.

When the target board 400 connected to the first conversion connector 340 of the motherboard 300 is the redundant array of independent hard disks board 402, two third in-place pins 480 of the redundant array of independent hard disks board 402 are electrically connected to the first in-place pins 343 and the second in-place pins 353, respectively. At this time, the first bit pin 343 and the second bit pin 353 may be electrically connected to the first voltage terminal 490 and the voltage circuit 380. At this time, the voltages of the first bit pin 343 and the second bit pin 353 are both within the first voltage threshold range.

Thus, the programmable logic device 390 may determine the type of the target board 400 to which the first conversion connector 340 is connected based on the voltage of the first bit pin 343 and the voltage of the second bit pin 353.

So configured, the programmable logic device 390 can automatically detect the type of the target board 400 when the target board 400 is connected to the first conversion connector.

In some examples, programmable logic device 390 may include a plurality of registers including a first register and a second register. Wherein the first register is electrically connected to the first bit pin 343 and the second register is connected to the second bit pin 353. The register value of the first register is 0 when the voltage of the first bit pin 343 is within the first voltage threshold range, and 1 when the voltage of the first bit pin 343 is within the second voltage threshold range. The register value of the second bit pin 353 is 0 when the second bit pin 353 is within the first voltage threshold range, and the register value of the second bit pin 353 is 1 when the second bit pin 353 is within the second voltage threshold range. Accordingly, the register value of the first register may be changed when the voltage of the first bit pin 343 is changed, and the register value of the second register may be changed when the voltage of the second bit pin 353 is changed. Thus, programmable logic device 390 may obtain a threshold range in which the voltage value of first bit pin 343 is based on the register value of the first register and a threshold range in which the voltage value of second bit pin 353 is based on the register value of the second register.

In some examples, programmable logic device 390 may be an FPGA (Field-Programmable Gate Array, field programmable gate array) or a CPLD (Complex Programmable Logic Device ). The FPGA is programmable, high in flexibility and low in power consumption. The CPLD has the advantages of low cost on the basis of high programmability and flexibility and low power consumption.

In one implementation, the voltage at the second voltage terminal is higher than the voltage at the first voltage terminal 490.

Hereinafter, for convenience of description, a voltage within the first voltage threshold range is referred to as a low voltage, and a voltage within the second voltage threshold range is referred to as a high voltage.

When the through board 401 is connected to the first transit connector 340, the first in-place pin 343 on the first transit connector 340 is at a low voltage, and the voltage on the second in-place pin 353 on the second transit connector 350 is at a high voltage, however, only the first transit connector 340 is used for transmitting SATA protocol signals output by the south bridge chip 320, and the second transit connector 350 does not need to transmit PCIE protocol signals output by the central processor 330, so that the second in-place pin 353 at a high level does not affect transmission of other signals. At this time, the first bit pin 343 is at a low voltage, so that the influence of the first bit pin 343 on the transmission of SATA protocol signals by the first conversion connector 340 can be reduced, and the influence of the third bit pin 480 on the transmission of SATA protocol signals can be reduced.

Similarly, when the redundant array of independent disks card 402 is connected to the first adapter connector 340,

when the through board 401 is connected to the first transit connector 340, the first bit pin 343 on the first transit connector 340 is at a low voltage, and the voltage of the second bit pin 353 on the second transit connector 350 is at a low voltage, so that the effect of the first bit pin 343 and the second bit pin 353 on the transmission of PCIE protocol signals can be reduced.

In some examples, the number of first bit pins 343 may be one or more.

The number of second bit pins 353 may be one or more.

In some implementations, motherboard 300 may also include a basic input output (Basic Input Output System, BIOS) unit connected to programmable logic device 390 for: in the case that the programmable logic device 390 determines that the target board 400 connected to the first conversion connector 340 is the independent hard disk redundancy array board 402, the south bridge chip 320 is controlled to stop outputting SATA protocol signals. By the arrangement, the collision of the SAS protocol signal output by the redundant array of independent hard disk chip 440 and the SATA protocol signal output by the south bridge chip 320 on the first pin group 341 can be avoided, and the signals on other pin groups can be prevented from being interfered.

In some examples, the computing device 1000 may further include a BMC, the programmable logic device 390 is electrically connected to the BMC, and the BMC is electrically connected to the bios, the programmable logic device 390 may send the board type information of the target board 400 to the BMC, and the BMC may send the board type information of the target board 400 to the bios. The BMC may determine the type of the target board 400 in the computing device according to the board type information.

Fig. 14 is another block diagram of a computing device 1000, according to some embodiments.

Referring to fig. 14, in some implementations, the motherboard 300 further includes: the sixth adapter connector 391 disposed on the board 310 is electrically connected to the second pin set 342, and the hard disk back plate 150 can be plugged and electrically connected to the sixth adapter connector 391.

The second pin set 342 includes a plurality of second pins, and the sixth adapter connector 391 includes a plurality of sixth pins, and the plurality of second pins are electrically connected to the plurality of sixth pins in a one-to-one correspondence.

Illustratively, a second pin is electrically connected to a sixth pin by a wire.

For example, in the case where the number of the second pins is 24, the number of the sixth pins is also 24.

In some examples, the hard disk backplate 150 may include a circuit board and a plurality of hard disk slots, the plurality of hard disk slots may be disposed on the circuit board, and the plurality of hard disks 120 may be respectively plugged into the plurality of hard disk slots.

In some examples, the sixth adapter connector 391 may be disposed on the edge of the board 310, so as to facilitate the plugging of the sixth adapter connector 391 with the hard disk backplate 150.

Referring to fig. 2 and 3 again, the present application further provides a motherboard 300. The main board 300 includes: a board 310, a south bridge chip 320, a central processor 330 and a first transfer connector 340. Wherein, the south bridge chip 320 is disposed on the board 310; the central processor 330 is disposed on the board 310. The first transferring connector 340 is disposed on the board 310, and the first transferring connector 340 includes a first pin group 341 and a second pin group 342; the first pin set 341 is connected to the south bridge chip 320, and the second pin set 342 is used for coupling with the memory module 500.

When the first transit connector 340 is connected to the through board 401, the first pin set 341 and the second pin set 342 are coupled through the through board 401, and the south bridge chip 320 is configured to output SATA protocol signals, which can be sequentially transmitted to the storage assembly 500 through the first pin set 341, the through board 401 and the second pin set 342.

When the first switch connector 340 is connected to the hdd redundancy array board 402, the central processor 330 is coupled to the hdd redundancy array board 402, and the hdd redundancy array board 402 is coupled to the second pin set 342, where the central processor 330 is configured to send PCIE protocol signals to the hdd redundancy array board 402, and the hdd redundancy array board 402 is capable of converting PCIE protocol signals into SAS protocol signals, and the SAS protocol signals are capable of being transmitted to the storage component 500 through the second pin set 342.

Wherein, the main board 300 has been described in detail above, and will not be described herein. Wherein, the liquid crystal display device comprises a liquid crystal display device,

in the case where the first transit connector 340 is connected to the through board 401, or in the case where the first transit connector 340 is connected to the redundant array of independent hard disks board 402, the motherboard 300 can manage the storage assembly 500, so that the motherboard 300 has higher compatibility. Accordingly, redesigning the motherboard 300 due to changing the target board 400 can be avoided, whereby costs can be saved.

In addition, in both cases where the first conversion connector 340 is connected to the through board 401 or the redundant array of independent hard disks board 402, signals received by the through board 401 or the redundant array of independent hard disks board 402 may be transmitted to the second pin group 342 and transmitted to the memory assembly 500 through the second pin group 342. Accordingly, the second pin group 342, and the connection link between the second pin group 342 and the memory assembly 500 can be multiplexed in both cases, so that the cost of the motherboard 300 can be reduced.

Referring again to fig. 4, in some implementations, motherboard 300 further includes: the second adaptor connector 350 is disposed on the board 310, and the second adaptor connector 350 is connected to the cpu 330. When the first switch connector 340 is connected to the hdd redundancy array board 402, the hdd redundancy array board 402 is further connected to the second switch connector 350, and PCIE protocol signals output by the cpu 330 can be transmitted to the hdd redundancy array board 402 through the second switch connector 350.

Referring again to fig. 12 and 13, in some implementations, the first transit connector 340 further includes a first in-place pin 343 and the second transit connector 350 further includes a second in-place pin 353. Motherboard 300 also includes: a voltage circuit 380 and a programmable logic device 390 disposed on the board 310; the voltage circuit 380 is connected to the first bit pin 343 and the second bit pin 353, and in the case that the first bit pin 343 is not connected to the target board 400, the voltage circuit 380 can make the voltage of the first bit pin 343 within the second voltage threshold range; in the case that the first bit pin 343 is connected to the target board 400, the voltage circuit 380 and the target board 400 together make the voltage of the first bit pin 343 within the first voltage threshold range; in the case where the second bit pin 353 is not connected to the target board 400, the voltage circuit 380 can make the voltage of the second bit pin 353 within the second voltage threshold range; in the case where the second in-place pin 353 is connected to the target board 400, the voltage circuit 380 and the target board 400 together make the voltage of the second in-place pin 353 within the first voltage threshold range; the target board 400 is one of a pass-through board 401 and an independent hard disk redundant array board 402.

The programmable logic device 390 is connected to the first bit pin 343 and the second bit pin 353; the programmable logic device 390 is for: detecting a voltage of the first bit pin 343 and a voltage of the second bit pin 353; in addition, in the case that the voltage of the first in-place pin 343 and the voltage of the second in-place pin 353 are both within the first voltage threshold range, it is determined that the board connected to the first conversion connector 340 is the independent hard disk redundant array board 402; in the case that the voltage of the first bit pin 343 is within the first voltage threshold range and the voltage of the second bit pin 353 is within the second voltage threshold range, the board connected to the first conversion connector 340 is determined to be the through board 401.

Wherein, when the target board 400 is connected to the first conversion connector, the programmable logic device 390 can automatically detect the kind of the target board 400.

In some implementations, motherboard 300 further includes: the basic input/output unit is arranged on the board body 310 and is connected with the programmable logic device 390 and the south bridge chip 320; the basic input/output unit is used for: in the case that the programmable logic device 390 determines that the target board 400 connected to the first conversion connector 340 is the independent hard disk redundancy array board 402, the south bridge chip 320 is controlled to stop outputting SATA protocol signals.

By the arrangement, the collision of the SAS protocol signal output by the redundant array of independent hard disk chip 440 and the SATA protocol signal output by the south bridge chip 320 on the first pin group 341 can be avoided, and the signals on other pin groups can be prevented from being interfered.

In some implementations, the second transit connector 350 includes a third pin set 351 and a fourth pin set 352, the third pin set 351 being connected to the central processor 330, the fourth pin set 352 being for coupling with the redundant array of independent disks card 402.

The motherboard 300 further includes a first field programmable gate array chip 360 disposed on the board body 310, wherein the first field programmable gate array chip 360 is connected to the fourth pin group 352 and can be electrically connected to the memory assembly 500. When the first switch connector 340 is connected to the redundant array of independent hard disk board 402, the fourth pin set 352 is configured to receive the first low-speed signal output by the redundant array of independent hard disk board 402 and transmit the first low-speed signal to the first field programmable gate array chip 360. The first field programmable gate array chip 360 is used to transmit a first low-speed signal to the memory assembly 500.

The second input pin group 450 electrically connected to the redundant array of independent hard disk chip 440 is disposed on the switch circuit board 410, and the fourth pin group 352 and the first field programmable gate array chip 360 are disposed on the board 310, and the first field programmable gate array chip 360 may be electrically connected to the memory component 500, where the second input pin group 450 may be electrically connected to the fourth pin group 352, so that the first low-speed signal output by the redundant array of independent hard disk chip 440 may be transmitted to the first field programmable gate array chip 360 through the second input pin group 450 and the fourth pin group 352, and then the first field programmable gate array chip 360 may forward the first low-speed signal to the memory component 500, so that the redundant array of independent hard disk chip 440 may perform interaction of the low-speed signal with the memory component 500.

In some implementations, motherboard 300 further includes: a second field programmable gate array chip 370 disposed on the board 310 and connected to the south bridge chip 320 and the memory assembly 500. When the first transit connector 340 is connected to the through board 401, the south bridge chip 320 is further configured to: outputting a second low-speed signal; the second field programmable gate array chip 370 is configured to receive the second low-speed signal and transmit the second low-speed signal to the memory assembly 500.

The foregoing is merely illustrative of the embodiments of the present application, and the present application is not limited thereto, and any person skilled in the art will recognize that changes and substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A motherboard, comprising:

a plate body;

the south bridge chip is arranged on the board body;

the central processing unit is arranged on the plate body;

the first conversion connector is arranged on the board body and comprises a first pin group and a second pin group; the first pin group is connected to the south bridge chip, and the second pin group is used for coupling with a storage component;

when the first conversion connector is connected to the through board, the first pin group and the second pin group are coupled through the through board, the south bridge chip is used for outputting SATA protocol signals, and the SATA protocol signals can be transmitted to the storage component through the first pin group, the through board and the second pin group in sequence;

when the first transfer connector is connected to the independent hard disk redundancy array board card, the central processing unit is coupled with the independent hard disk redundancy array board card, and the independent hard disk redundancy array board card is coupled with the second pin group, wherein the central processing unit is used for sending PCIE protocol signals to the independent hard disk redundancy array board card, the independent hard disk redundancy array board card can convert the PCIE protocol signals into SAS protocol signals, and the SAS protocol signals can be transmitted to the storage component through the second pin group.

2. The motherboard of claim 1, further comprising:

the second transfer connector is arranged on the board body and is connected with the central processing unit;

when the first transfer connector is connected to the independent hard disk redundant array board, the independent hard disk redundant array board is also connected to the second transfer connector, and PCIE protocol signals output by the central processing unit can be transmitted to the independent hard disk redundant array board through the second transfer connector.

3. The motherboard according to claim 2, wherein,

the first transfer connector further comprises a first in-place pin, and the second transfer connector further comprises a second in-place pin;

the motherboard further comprises: the voltage circuit and the programmable logic device are arranged on the board body;

the voltage circuit is connected with the first in-place pin and the second in-place pin, and can enable the voltage of the first in-place pin to be within a second voltage threshold range under the condition that the first in-place pin is not connected with a target board card; the voltage circuit and the target board card jointly enable the voltage of the first in-place pin to be in a first voltage threshold range under the condition that the first in-place pin is connected with the target board card; the voltage circuit can enable the voltage of the second in-place pin to be within a second voltage threshold range under the condition that the second in-place pin is not connected to the target board; the voltage circuit and the target board card jointly enable the voltage of the second in-place pin to be within a first voltage threshold range under the condition that the second in-place pin is connected with the target board card; the target board card is one of the through board card and the independent hard disk redundant array board card;

The programmable logic device is connected with the first in-place pin and the second in-place pin; the programmable logic device is used for:

detecting the voltage of the first in-bit pin and the voltage of the second in-bit pin; and, in addition, the processing unit,

under the condition that the voltage of the first in-place pin and the voltage of the second in-place pin are both in a first voltage threshold range, determining that the board card connected with the first transfer connector is the independent hard disk redundant array board card; and determining that the board card connected with the first transfer connector is the through board card under the condition that the voltage of the first in-place pin is in a first voltage threshold range and the voltage of the second in-place pin is in a second voltage threshold range.

4. A motherboard according to claim 3, further comprising:

the basic input/output unit is arranged on the plate body; the basic input/output unit is connected with the programmable logic device and the south bridge chip; the basic input/output unit is used for: and under the condition that the programmable logic device determines that the target board card connected with the first transfer connector is the independent hard disk redundant array board card, controlling the south bridge chip to stop outputting the SATA protocol signal.

5. The motherboard according to claim 2, wherein,

the second transfer connector comprises a third pin group and a fourth pin group, the third pin group is connected with the central processing unit, and the fourth pin group is used for being coupled with the independent hard disk redundant array board card;

the main board further comprises a first field programmable gate array chip arranged on the board body, and the first field programmable gate array chip is connected to the fourth pin group and can be electrically connected with the storage component;

when the first transfer connector is connected to the independent hard disk redundant array board, the fourth pin group is used for receiving a first low-speed signal output by the independent hard disk redundant array board and transmitting the first low-speed signal to the first field programmable gate array chip;

the first field programmable gate array chip is configured to transmit the first low-speed signal to the memory component.

6. The motherboard of claim 1, further comprising:

the second field programmable gate array chip is arranged on the plate body and is connected with the south bridge chip and the storage component;

when the first conversion connector is connected to the through board, the south bridge chip is further configured to: outputting a second low-speed signal;

The second field programmable gate array chip is configured to receive the second low-speed signal and transmit the second low-speed signal to the storage component.

7. A computing device, comprising:

a storage component;

the target board card is a through board card or an independent hard disk redundant array board card;

the motherboard of any one of claims 1-6; the first transfer connector of the main board is connected with the target board card;

when the target board card connected with the first conversion connector is the through board card, the first pin group and the second pin group of the first conversion connector are coupled through the through board card, and the south bridge chip of the main board is used for outputting SATA protocol signals, and the SATA protocol signals can be transmitted to the storage component through the first pin group, the through board card and the second pin group in sequence;

when the target board card connected with the first conversion connector is an independent hard disk redundancy array board card, the central processing unit of the main board is coupled with the independent hard disk redundancy array board card, and the independent hard disk redundancy array board card is coupled with the second pin group, wherein the central processing unit is used for sending PCIE protocol signals to the independent hard disk redundancy array board card, the independent hard disk redundancy array board card can convert the PCIE protocol signals into SAS protocol signals, and the SAS protocol signals can be transmitted to the storage component through the second pin group.

8. The computing device of claim 7, wherein the computing device is configured to,

the main board also comprises a second transfer connector which is arranged on the board body of the main board and is connected with the central processing unit;

when the target board card connected with the first transfer connector is an independent hard disk redundant array board card, the independent hard disk redundant array board card is also connected with the second transfer connector, and PCIE protocol signals output by the central processing unit are sent to the independent hard disk redundant array board card through the second transfer connector.

9. The computing device of claim 8, wherein the computing device is configured to,

the target board card comprises a transfer circuit board, a first input pin group and a first output pin group, wherein the first input pin group and the first output pin group are coupled and are arranged on the transfer circuit board, and the first output pin group is connected with the second pin group;

when the first transfer connector is connected to the through board, the first input pin group is connected to the first pin group;

when the first transfer connector is connected to the redundant array of independent hard disk board, the first input pin group is connected to the second transfer connector.

10. The computing device of claim 8 or 9, wherein the computing device is configured to,

the target board card comprises a first voltage end and a third in-place pin which are arranged on the switching circuit board, and the first voltage end is connected with the third in-place pin;

when the target board card is the through board card, the target board card comprises a third in-place pin, and the third in-place pin is connected with the first in-place pin;

when the target board card is the independent hard disk redundant array board card, the target board card comprises two third in-place pins, wherein one third in-place pin is connected with the first in-place pin, and the other third in-place pin is electrically connected with the second in-place pin;

the voltage circuit is connected with the first in-place pin and the second in-place pin; wherein the voltage circuit is capable of causing the voltage of the first bit pin to be within a second voltage threshold range if the first bit pin is not connected to the third bit pin; the voltage circuit and the first voltage terminal jointly enable the voltage of the first in-place pin to be in a first voltage threshold range under the condition that the first in-place pin is connected with the third in-place pin; the voltage circuit is capable of enabling a voltage of the second in-place pin to be within a second voltage threshold range if the second in-place pin is not connected to the third in-place pin; the voltage circuit and the first voltage terminal jointly enable the voltage of the second in-place pin to be within a first voltage threshold range under the condition that the second in-place pin is connected with the third in-place pin;

The programmable logic device is connected to the first bit pin and the second bit pin, and the programmable logic device is configured to:

under the condition that the voltage of the first in-place pin and the voltage of the second in-place pin are both in a first voltage threshold range, determining that a target board card connected with the first transfer connector is the independent hard disk redundant array board card; and determining a target board card connected with the first transfer connector as the through board card under the condition that the voltage of the first in-place pin is in a first voltage threshold range and the voltage of the second in-place pin is in a second voltage threshold range.