CN218848703U

CN218848703U - Double-control storage device system and temperature control circuit of double-control storage device

Info

Publication number: CN218848703U
Application number: CN202222968513.4U
Authority: CN
Inventors: 左北国; 孟坤; 梁裕培
Original assignee: Guangdong Lvsuan Technology Co ltd
Current assignee: Guangdong Lvsuan Technology Co ltd
Priority date: 2022-11-08
Filing date: 2022-11-08
Publication date: 2023-04-11
Anticipated expiration: 2032-11-08

Abstract

The application relates to a double-control storage device system and a temperature control circuit of the double-control storage device, which comprise a main control board, a slave control board and a control switching back board, wherein the main control board is provided with a main controller and a main control network plug in electrical signal connection with the main controller; the control switching back plate is provided with a first network socket and a second network socket, and the first network socket and the second network socket are connected through an electric signal so that a network signal can be transmitted between the first network socket and the second network socket; the master control network plug is used for being connected with the first network socket, and the slave control network plug is used for being connected with the second network socket. The temperature control circuit can provide electric signal connection for the two controllers of the double-control storage device, so that the temperature control of the storage device can be coordinated between the two controllers, and the temperature control of the storage device is balanced.

Description

Double-control storage device system and temperature control circuit of double-control storage device

Technical Field

The present application relates to the field of storage device technologies, and in particular, to a dual-control storage device system and a temperature control circuit of a dual-control storage device.

Background

For the storage device with higher reliability requirement, two control boards are mostly adopted, i.e. a dual-control strategy, and both the two control boards can be connected with and control the storage device at the back end. The dual-control storage device increases the power consumption of the device while improving the reliability of the device. The higher the power consumption, the higher the heat release, and the higher the temperature, and the excessive temperature may cause the data access and transmission of the memory device to malfunction, and in a serious case, may cause the damage of a part of devices of the memory device. For a memory device with strict reliability requirements, it is very important and necessary to ensure the normal operating temperature of each device in the device. Therefore, temperature control is critical to memory devices, especially dual-control memory devices that consume more power than a typical single-control memory device.

In the temperature control system of the double-control storage device in the prior art, network information of two control panels is not communicated, and a controller on each control panel only detects the temperature of the control panel and controls the temperature according to the temperature of the control panel. Therefore, a temperature control coordination failure and a temperature control runaway of the dual-control storage device are caused.

SUMMERY OF THE UTILITY MODEL

Therefore, it is necessary to provide a dual-control storage device system and a temperature control circuit of a dual-control storage device, which can provide electrical signal connection for two controllers of the dual-control storage device, and the two controllers can transmit network signals through the electrical signal connection, so that the temperature control of the storage device can be coordinated between the two controllers, and the temperature control of the storage device can be balanced.

A temperature control circuit of a double-control storage device comprises a master control board, a slave control board and a control switching back board, wherein the master control board is provided with a master controller and a master control network plug in electrical signal connection with the master controller; the control switching back plate is internally provided with a first network socket and a second network socket, and the first network socket and the second network socket are connected by electric signals so as to transmit network signals between the first network socket and the second network socket; the master control network plug is used for being connected with the first network socket, and the slave control network plug is used for being connected with the second network socket.

In one embodiment, a first control socket and a second control socket are further arranged in the control adapter backplane, and an electric signal connection is configured between the first control socket and the second control socket so that a detection signal is transmitted between the first control socket and the second control socket; the master control board is further provided with a master control plug in electrical signal connection with the master controller, the slave control board is further provided with a slave control plug in electrical signal connection with the slave controller, the master control plug is used for being connected with the first control socket, and the slave control plug is used for being connected with the second control socket.

In one embodiment, the master control plug is provided with a first pin, the slave control plug is provided with a second pin, the master control plug is provided with a first card presence detection pin, and the slave control plug is provided with a second card presence detection pin; one end of the first pin is connected with the ground in the main control board, and the other end of the first pin is used for being connected with the second card existence detection pin; one end of the second pin is connected to the ground in the slave control board, and the other end of the second pin is used for being connected with the first card existence detection pin.

In one embodiment, the master control plug is further configured with a first communication pin, the first control socket is respectively connected with the drive controllers of the one or more fans, and when the master control plug is connected with the first control socket, the master control plug transmits a fan drive signal to the first control socket through the first communication pin; the slave control plug is also provided with a second communication pin, the second control socket is respectively connected with the driving controllers of one or more fans, and when the slave control plug is connected with the second control socket, the slave control plug transmits a fan driving signal to the second control socket through the second communication pin; wherein one or more fans are used to regulate the temperature of the storage device.

In one embodiment, the control adapter backplane is further provided with a master control board slot and a slave control board slot; the main control board slot is used for loading the main control board and providing a main control card slot position signal for the main control board so that a main controller of the main control board can identify a main control identity; the slave control board slot is used for loading the slave control board and providing a slave control card slot position signal for the slave control board so that the slave controller of the slave control board can identify the slave control identity.

In one embodiment, the storage device is an NVME storage device, the main control board is further configured with a first NVME conversion chip, a first PCIE bridge chip and a first substrate management controller, the first PCIE bridge chip is used for being in electrical signal connection with the first NVME storage device, the first PCIE bridge chip is connected to the first NVME conversion chip through a PCIE bus, the first NVME conversion chip is configured with a first pair of external network interfaces, the first substrate management controller is respectively in electrical signal connection with the first NVME conversion chip and the first PCIE bridge chip to read the temperature of the first NVME conversion chip and the temperature of the first PCIE bridge chip, and the first substrate management controller is in electrical signal connection with the main controller to send the temperature of the first NVME conversion chip and the temperature of the first PCIE bridge chip to the main controller; and the slave control board is also provided with a second NVME conversion chip, a second PCIE bridge piece and a second substrate management controller, the second PCIE bridge piece is used for being in electrical signal connection with second NVME storage equipment, the second PCIE bridge piece is connected with the second NVME conversion chip through a PCIE bus, the second NVME conversion chip is provided with a second pair of external network interfaces, the second substrate management controller is respectively in electrical signal connection with the second NVME conversion chip and the second PCIE bridge piece so as to read the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge piece, and the second substrate management controller is in electrical signal connection with the slave controller so as to send the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge piece to the slave controller.

In one embodiment, the main control board is further configured with a first hardware monitoring chip, the first hardware monitoring chip is respectively in electrical signal connection with the first baseboard management controller and the main controller, and the first hardware monitoring chip is used for receiving a first fan speed regulation signal sent by the first baseboard management controller, generating a first fan driving signal based on the first fan speed regulation signal, and sending the first fan driving signal to the main controller; and/or the slave control board is also provided with a second hardware monitoring chip, the second hardware monitoring chip is respectively in electric signal connection with the second substrate management controller and the slave controller, and the second hardware monitoring chip is used for receiving a second fan speed regulation signal sent by the second substrate management controller, generating a second fan driving signal based on the second fan speed regulation signal and sending the second fan driving signal to the master controller.

In one embodiment, the first hard monitoring chip and/or the second hard monitoring chip is a chip of the NCT7904 model; and/or the master controller and/or the slave controller are chips of GW1N-9K-UBGA256 type.

In one embodiment, the NVME storage device is a u.2 storage disk array, and the u.2 storage disk array is electrically connected to the first PCIE bridge chip and the second PCIE bridge chip through PCIE interfaces, respectively.

A dual-control storage device system comprising one or more fans, storage devices, and the temperature control circuit of any of the above embodiments; the master controller and the slave controller of the temperature control circuit are respectively in electric signal connection with the driving controllers of the one or more fans so as to send driving control signals to the driving controllers of the one or more fans, and the driving controllers of the one or more fans are used for driving the rotating speed of the one or more fans; one or more fans are used to regulate the temperature of the storage device.

Therefore, the control switching back plate is configured, a first network socket and a second network socket are arranged in the control switching back plate, and electric signal connection is configured between the first network socket and the second network socket so that network signals can be transmitted between the first network socket and the second network socket. When a master control network plug of the master control board is connected with a first network socket and a slave control network plug of the slave control board is connected with a second network socket, the master controller can perform network signal communication with the slave controller through the master control network plug, receive network signals sent by the slave controller, the slave controller can perform network signal communication with the master controller through the slave control network plug, receive network signals sent by the master controller, thereby providing electric signal connection for two controllers of the double-control storage device, the two controllers can transmit the network signals through the electric signal connection, so that the temperature control of the storage device can be coordinated between the two controllers, and the temperature control of the storage device is balanced.

Drawings

FIG. 1 is a block diagram of a temperature control circuit of a dual-control storage device according to an embodiment of the present disclosure;

FIG. 2 is a circuit diagram illustrating the connection relationship between the master network plug and the first network socket and between the slave network plug and the second network socket according to an embodiment of the present application;

FIG. 3 is a circuit diagram illustrating the connection relationship between a master control plug and a first control socket and between a slave control plug and a second control socket according to an embodiment of the present application;

FIG. 4 is a block diagram of a dual-managed storage device system according to one embodiment of the present application;

FIG. 5 is a circuit diagram of an embodiment of a chip model NCT7904 of the present application;

FIG. 6 is a circuit diagram of a GW1N-9K-UBGA256 chip of the present application in one embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides a temperature control circuit of double-control storage equipment. In one embodiment, as shown in fig. 1, a temperature control circuit of a dual-control storage device includes a master control board 100, a slave control board 200, and a control adapter backplane 300, where the master control board 100 is provided with a master controller 101 and a master control network plug 102 in electrical signal connection with the master controller 101, the slave control board 200 is provided with a slave controller 201 and a slave control network plug 202 in electrical signal connection with the slave controller 201, and both the master controller 101 and the slave controller 201 are used to control the temperature of the storage device 20; a first network socket 3011 and a second network socket 3012 are arranged in the control switching backplane 300, and an electrical signal connection is configured between the first network socket 3011 and the second network socket 3012, so that a network signal is transmitted between the first network socket 3011 and the second network socket 3012; the master network jack 102 is configured to connect to a first network jack 3011, and the slave network jack 202 is configured to connect to a second network jack 3012.

Specifically, the circuits and the connection modes of the master network plug 102, the slave network plug 202, the first network socket 3011 and the second network socket 3012 are shown in fig. 2. As shown in fig. 2, the master network jack 102, the slave network jack 202, the first network jack 3011 and the second network jack 3012 constitute network connectors of a master controller and a slave controller. The master network plug 102 includes 8 signal lines 1021, and the 8 signal lines 1021 form 4 pairs of differential signal lines. The first network socket 3011 includes corresponding signal lines of 8 signal lines 1021. The slave network control plug 202 comprises 8

signal lines

2021, and 8 signal lines 2021 form 4 pairs of differential signal lines. The second network socket 3012 includes corresponding signal lines of 8 signal lines 2021. The 8 signal lines 2021 and the 8 signal lines 1021 are each used to transmit gigabit signals. Therefore, the master control board 100 and the slave control board 200 can transmit gigabit network signals by controlling the switching backplane 300, and then network signals can be transmitted between the two controllers, so that the temperature control of the storage device can be coordinated between the two controllers, and the temperature control of the storage device can be balanced.

The temperature control circuit of the double-control storage device is configured with the control switching back plate, the control switching back plate is provided with the first network socket and the second network socket, and the first network socket and the second network socket are configured with electric signal connection so that network signals are transmitted between the first network socket and the second network socket. When a master control network plug of the master control board is connected with a first network socket and a slave control network plug of the slave control board is connected with a second network socket, the master controller can perform network signal communication with the slave controller through the master control network plug, receive network signals sent by the slave controller, the slave controller can perform network signal communication with the master controller through the slave control network plug, receive network signals sent by the master controller, thereby providing electric signal connection for two controllers of the double-control storage device, the two controllers can transmit the network signals through the electric signal connection, so that the temperature control of the storage device can be coordinated between the two controllers, and the temperature control of the storage device is balanced.

In one embodiment, a first control socket 3013 and a second control socket 3014 are further disposed in the control patch back panel, and an electrical signal connection is configured between the first control socket 3013 and the second control socket 3014, so that a detection signal is transmitted between the first control socket 3013 and the second control socket 3014; the master control board 100 is further provided with a master control plug 103 in electrical signal connection with the master controller 101, the slave control board 200 is further provided with a slave control plug 203 in electrical signal connection with the slave controller 201, the master control plug 103 is used for being connected with the first control socket 3013, and the slave control plug 203 is used for being connected with the second control socket 3014.

In one embodiment, the master control plug 103 is provided with a first pin, the slave control plug 203 is provided with a second pin, the master control plug 103 is provided with a first card presence detection pin, and the slave control plug 203 is provided with a second card presence detection pin; one end of the first pin is connected to the ground in the main control board 100, and the other end of the first pin is used for being connected to the second card presence detection pin; one end of the second pin is connected to ground in the slave control board 200, and the other end of the second pin is used for connection with the first card presence detection pin.

In one embodiment, the master control plug 103 is further configured with a first communication pin, the first control socket 3013 is respectively connected to the drive controllers of one or more fans, and when the master control plug 103 is connected to the first control socket 3013, the master control plug 103 transmits a fan drive signal to the first control socket 3013 through the first communication pin; the slave control plug 203 is also provided with a second communication pin, the second control socket 3014 is respectively connected with the drive controllers of one or more fans, and when the slave control plug 203 is connected with the second control socket 3014, the slave control plug 203 transmits a fan drive signal to the second control socket 3014 through the second communication pin; wherein one or more fans are used to regulate the temperature of the storage device.

Specifically, as shown in FIG. 3, the master control plug 103 and the slave control plug 203 are both HDTF-6-06-S type plugs, and the first control socket 3013 and the second control socket 3014 are both HDTM-6_06_1 type sockets. The first pin of the main control plug 103 is a pin 1031 shown in fig. 3, and the first card presence detection pin of the main control plug 103 is a pin 1032 shown in fig. 2. The second pin of the slave control plug 203 is the pin 2031 shown in fig. 3, and the second card presence detection pin of the slave control plug 203 is the pin 2032 shown in fig. 2. As shown in fig. 3, the first control socket 3013 includes a pin corresponding to a first pin and a pin corresponding to a first card presence detection pin, and the second control socket 3014 includes a pin corresponding to a second pin and a pin corresponding to a second card presence detection pin.

As shown in fig. 3, when the master control plug 103 is inserted into the first control socket 3013 and the slave control plug 203 is inserted into the second control socket 3014, the pins 1031 are connected to corresponding pins of the first control socket 3013, and the pins 2031 are connected to pins of the second control socket 3014, so that the master control board 10 can detect the presence of the slave control board 200 through the pins 1032, and the slave control board 200 can detect the presence of the slave control board 200 through the pins 2032.

Specifically, as shown in fig. 3, the first communication pins include a pin A1 and a pin B1 in the master control plug 103, and the first control socket 3013 transmits a fan driving signal to the driving controllers of the four fans through the pin A1 and the pin B1 in the first control socket 3013. The second communication pins include a pin A1 and a pin B1 in the slave control plug 203, and the second control socket 3014 transmits a fan driving signal to the driving controllers of the four fans through the pin A1 and the pin B1 in the second control socket 3014.

In one embodiment, as shown in fig. 1, the control patch backplane 300 is further provided with a master board slot 3015 and a slave board slot 3016; the main control board slot 3015 is used to load the main control board 100 and provide a slot location signal for main control to the main control board 100, so that the main controller 101 of the main control board 100 recognizes a main control identity; the slave controller slot 3016 is used to load the slave controller 200 and provide a slave controller slot signal to the slave controller 200, so that the slave controller 201 of the slave controller 200 recognizes the slave controller identity.

Specifically, the master control board 100 and the slave control board 200 can detect whether the board belongs to the master control board or the slave control board from the slot position signal. As shown in fig. 3, the main control board slot 3015 provides a slot location signal to the main control board 100 through pin J1 of the first control socket 3013. The main control board 100 receives a slot position signal from the pin J1 of the first control socket 3013 through the pin J1 of the main control plug 103 and sends the slot position signal to the main controller 101 to identify the main control identity of the main control board 100. The slave control board slot 3016 provides a slot location signal to the slave control board 200 through pin J1 of the second control socket 3014. The slave board 200 recognizes the slave identity of the slave controller 201 by receiving a slot position signal from pin J1 of the second control socket 3014 from pin J1 of the slave control plug 203 and transmitting the slot position signal to the slave controller 201.

In one embodiment, the storage device 20 is an NVME storage device, the main control board 100 is further configured with a first NVME conversion chip, a first PCIE bridge chip and a first substrate management controller, the first PCIE bridge chip is used for electrically connecting with the first NVME storage device, the first PCIE bridge chip is connected to the first NVME conversion chip through a PCIE bus, the first NVME conversion chip is configured with a first pair of external network interfaces, the first substrate management controller is respectively electrically connected to the first NVME conversion chip and the first PCIE bridge chip to read the temperature of the first NVME conversion chip and the temperature of the first PCIE bridge chip, and the first substrate management controller is electrically connected to the main control device 101 to send the temperature of the first NVME conversion chip and the temperature of the first PCIE bridge chip to the main control device; and the slave control board 200 is further configured with a second NVME conversion chip, a second PCIE bridge chip, and a second substrate management controller, the second PCIE bridge chip is used for being electrically connected to the second NVME storage device, the second PCIE bridge chip is connected to the second NVME conversion chip through a PCIE bus, the second NVME conversion chip is configured with a second pair of external network interfaces, the second substrate management controller is respectively electrically connected to the second NVME conversion chip and the second PCIE bridge chip to read the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge chip, and the second substrate management controller is electrically connected to the slave controller to send the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge chip to the slave controller 201.

Specifically, as shown in fig. 4, on the control board, a BMC (baseboard management controller) and a PCIE (peripheral component interconnect express, a high speed serial computer expansion bus standard) bridge chip are directly connected through an Inter-integrated circuit (IICBus) and obtain a temperature thereof, the BMC and an NVME (non-volatile memory host controller interface specification) conversion chip are directly connected through the IIC and obtain a temperature thereof and a temperature of a rear NVME disk, and the NVME conversion chip temperature and the PCIE bridge chip temperature of another control board are obtained through the above control adapter backplane.

In one embodiment, the main control board 100 is further configured with a first hardware monitoring chip, the first hardware monitoring chip is electrically connected to the first baseboard management controller and the main controller 101, and the first hardware monitoring chip is configured to receive a first fan speed regulation signal sent by the first baseboard management controller, generate a first fan driving signal based on the first fan speed regulation signal, and send the first fan driving signal to the main controller 101; and/or the slave control board 200 is further configured with a second hardware monitoring chip, the second hardware monitoring chip is electrically connected to the second baseboard management controller and the slave controller 201, and the second hardware monitoring chip is configured to receive a second fan speed regulation signal sent by the second baseboard management controller, generate a second fan driving signal based on the second fan speed regulation signal, and send the second fan driving signal to the master controller.

Specifically, referring to fig. 4, a BMC (baseboard management Controller) on the control motherboard controls the operation of the fan through a HWM (hardware monitor chip) to dissipate heat. And the hardware monitoring chip generates a corresponding driving signal according to the fan speed regulating signal output by the BMC through the I2C bus so as to drive the fan to operate.

In one embodiment, the first hard monitor chip and/or the second hard monitor chip is a model NCT7904 chip. The NVME storage device is a U.2 storage disk array, and the U.2 storage disk array is in electrical signal connection with the first PCIE bridge piece and the second PCIE bridge piece through PCIE interfaces respectively. The master controller and/or the slave controller are chips of GW1N-9K-UBGA256 type.

Specifically, the first hard monitoring chip and/or the second hard monitoring chip is a chip of NCT7904 model, and a corresponding circuit diagram thereof is shown in fig. 5. The master controller and/or the slave controller are chips of GW1N-9K-UBGA256 type, the master controller and the slave controller both adopt corresponding FPGA chips, and corresponding circuit diagrams thereof are shown in FIG. 6.

The present application further provides a dual-control storage device system, including one or more fans, a storage device, and the temperature control circuit of any of the above embodiments; the master controller and the slave controller of the temperature control circuit are respectively in electric signal connection with the driving controllers of the one or more fans so as to send driving control signals to the driving controllers of the one or more fans, and the driving controllers of the one or more fans are used for driving the rotating speed of the one or more fans; one or more fans are used to regulate the temperature of the storage device.

Specifically, the storage device is a U.2 storage disk array. Both the master control board and the slave control board are NVME storage control boards as shown in fig. 4. The front end is the U.2 storage disk array of PCIE interface, and the centre is two kinds of switching backplate, cable and fan, and the rear end is two NVME storage control boards. The U.2 storage disk array is composed of a plurality of U.2 hard disks with PCIE interfaces. The two adapter backplanes are divided into a control adapter backplane and a U.2 storage adapter backplane, and a high-speed cable and a plurality of fans are arranged between the two adapter backplanes. The control switching back plate is connected with the NVME storage control plate, two NVME storage control plate slots are arranged on the control switching back plate, one slot is a main control plate slot, and the other slot is a slave control plate slot. The two NVME storage control boards are composed of an NVME conversion chip, a PCIE bridge chip, a BMC monitoring circuit, an FPGA and the like. The maximum power of the NVME conversion chip, the PCIE bridge chip and the U.2 storage disk is higher, which can reach dozens of to dozens of watts, but the power of the NVME conversion chip, the PCIE bridge chip and the U.2 storage disk is different from each other sometimes when the external end storage requirements are different. The BMC monitoring circuits on the two NVME storage control boards can read the NVME conversion chip temperature of the board, the PCIE bridge piece temperature and the U.2 storage disk temperature at the front end, the two boards have network communication through the control switching back board, and the NVME conversion chip temperature and the PCIE bridge piece temperature of the opposite board can be known mutually. The NVME storage control board inserted in the main control board slot of the control switching back board is the main control board, and the NVME storage control board inserted in the slave control board slot of the control switching back board is the slave control board. The master control board slot and the slave control board slot are in signal connection, and whether the other side exists or not can be detected from the connection signals. Therefore, the two control boards can intelligently adjust the rotating speed of the fan based on whether the other control board exists or not and according to the configuration of the equipment, different moments and the temperature of each part so as to adjust the temperature of the equipment in the U.2 storage disk array.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. The temperature control circuit of the double-control storage device is characterized by comprising a master control board, a slave control board and a control switching back board, wherein the master control board is provided with a master controller and a master control network plug in electrical signal connection with the master controller;

the control switching back plate is provided with a first network socket and a second network socket, and the first network socket and the second network socket are connected through an electric signal so that a network signal is transmitted between the first network socket and the second network socket;

the master control network plug is used for being connected with the first network socket, and the slave control network plug is used for being connected with the second network socket.

2. The temperature control circuit according to claim 1, wherein a first control socket and a second control socket are further disposed in the control patch backplane, and an electrical signal connection is configured between the first control socket and the second control socket, so that a detection signal is transmitted between the first control socket and the second control socket;

the master control board is further provided with a master control plug in electrical signal connection with the master controller, the slave control board is further provided with a slave control plug in electrical signal connection with the slave controller, the master control plug is used for being connected with the first control socket, and the slave control plug is used for being connected with the second control socket.

3. The temperature control circuit according to claim 2, wherein the master control plug is provided with a first pin, the slave control plug is provided with a second pin, the master control plug is provided with a first card presence detection pin, and the slave control plug is provided with a second card presence detection pin;

one end of the first pin is connected to the ground in the main control board, and the other end of the first pin is used for being connected with the second card existence detection pin;

one end of the second pin is connected to the ground in the slave control board, and the other end of the second pin is used for being connected with the first card existence detection pin.

4. The temperature control circuit of claim 2, wherein the master control plug is further configured with a first communication pin, the first control sockets are respectively connected to one or more fan driving controllers, and when the master control plug is connected to the first control socket, the master control plug transmits a fan driving signal to the first control socket through the first communication pin;

the slave control plug is also provided with a second communication pin, the second control socket is respectively connected with the driving controllers of one or more fans, and when the slave control plug is connected with the second control socket, the slave control plug transmits a fan driving signal to the second control socket through the second communication pin;

wherein the one or more fans are to regulate a temperature of the storage device.

5. The temperature control circuit according to claim 1, wherein the control adapter backplane is further provided with a master control board slot and a slave control board slot;

the main control board slot is used for loading the main control board and providing a main control slot position signal for the main control board so that a main controller of the main control board can identify a main control identity;

the slave control board slot is used for loading the slave control board and providing a slave control card slot position signal for the slave control board so as to enable the slave controller of the slave control board to identify the slave control identity.

6. The temperature control circuit according to claim 1, wherein the storage device is an NVME storage device, the main control board is further configured with a first NVME conversion chip, a first PCIE bridge chip, and a first substrate management controller, the first PCIE bridge chip is configured to be electrically connected to the NVME storage device, the first PCIE bridge chip is connected to the first NVME conversion chip through a PCIE bus, the first NVME conversion chip is configured with a first pair of external network interfaces, the first substrate management controller is electrically connected to the first NVME conversion chip and the first PCIE bridge chip, respectively, so as to read a temperature of the first NVME conversion chip and a temperature of the first PCIE bridge chip, and the first substrate management controller is electrically connected to the main controller, so as to send the temperature of the first NVME conversion chip and the temperature of the first PCIE bridge chip to the main controller;

and the number of the first and second groups,

the slave control board is further provided with a second NVME conversion chip, a second PCIE bridge piece and a second substrate management controller, the second PCIE bridge piece is used for being in electric signal connection with the NVME storage device, the second PCIE bridge piece is connected with the second NVME conversion chip through a PCIE bus, the second NVME conversion chip is provided with a second external-to-external network interface, the second substrate management controller is respectively in electric signal connection with the second NVME conversion chip and the second PCIE bridge piece to read the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge piece, and the second substrate management controller is in electric signal connection with the slave controller to send the temperature of the second NVME conversion chip and the temperature of the second PCIE bridge piece to the slave controller.

7. The temperature control circuit according to claim 6, wherein the main control board is further configured with a first hardware monitoring chip, the first hardware monitoring chip is electrically connected to the first baseboard management controller and the main controller, respectively, and the first hardware monitoring chip is configured to receive a first fan speed regulation signal sent by the first baseboard management controller, generate a first fan driving signal based on the first fan speed regulation signal, and send the first fan driving signal to the main controller;

and/or the presence of a gas in the gas,

the slave control board is also provided with a second hardware monitoring chip, the second hardware monitoring chip is respectively in electric signal connection with the second substrate management controller and the slave controller, and the second hardware monitoring chip is used for receiving a second fan speed regulation signal sent by the second substrate management controller, generating a second fan driving signal based on the second fan speed regulation signal and sending the second fan driving signal to the master controller.

8. The temperature control circuit of claim 7, wherein the first hardware monitor chip and/or the second hardware monitor chip is a model NCT7904 chip;

and/or the presence of a gas in the gas,

the master controller and/or the slave controller are chips of GW1N-9K-UBGA256 model.

9. The temperature control circuit according to claim 6, wherein the NVME storage device is a u.2 storage disk array, and the u.2 storage disk array is electrically connected to the first PCIE bridge chip and the second PCIE bridge chip through PCIE interfaces, respectively.

10. An on-premises storage device system, comprising one or more fans, a storage device, and the temperature control circuit of any of claims 1-9;

the master controller and the slave controller of the temperature control circuit are respectively in electric signal connection with the driving controllers of the one or more fans so as to send driving control signals to the driving controllers of the one or more fans, and the driving controllers of the one or more fans are used for driving the rotating speed of the one or more fans;

the one or more fans are used to regulate the temperature of the storage device.