CN116662124A - Computer working state display system and method - Google Patents

Computer working state display system and method Download PDF

Info

Publication number
CN116662124A
CN116662124A CN202310436225.0A CN202310436225A CN116662124A CN 116662124 A CN116662124 A CN 116662124A CN 202310436225 A CN202310436225 A CN 202310436225A CN 116662124 A CN116662124 A CN 116662124A
Authority
CN
China
Prior art keywords
connector
bmc
display
gpio
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202310436225.0A
Other languages
Chinese (zh)
Other versions
CN116662124B (en
Inventor
杨占
申明伟
茅振宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hexin Technology Co ltd
Hexin Technology Suzhou Co ltd
Original Assignee
Hexin Technology Co ltd
Hexin Technology Suzhou Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hexin Technology Co ltd, Hexin Technology Suzhou Co ltd filed Critical Hexin Technology Co ltd
Priority to CN202310436225.0A priority Critical patent/CN116662124B/en
Publication of CN116662124A publication Critical patent/CN116662124A/en
Application granted granted Critical
Publication of CN116662124B publication Critical patent/CN116662124B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/328—Computer systems status display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • G06F11/324—Display of status information
    • G06F11/325—Display of status information by lamps or LED's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The application relates to the technical field of computers, in particular to a computer working state display system and a method, wherein the system comprises the following components: BMC controller and connector; each display lamp is arranged on the connector; the BMC controller is respectively connected with each display lamp through a GPIO bus; the BMC controller is used for acquiring the working state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp can perform state display according to the working state information. According to the scheme, the working state of the computer can be displayed through the display lamp on the connector, the space of the main board or the chassis is not required to be occupied, the space occupation of the main board or the chassis and the waste of resources are reduced, and the working state of the computer can be seen without opening the case, so that the computer is more visual and convenient.

Description

Computer working state display system and method
Technical Field
The application relates to the technical field of computers, in particular to a computer working state display system and a computer working state display method.
Background
When a computer (computer/server, etc.) product performs numerical calculation, logic calculation or memory storage functions, massive data needs to be processed at high speed, so that it is particularly important to quickly and intuitively locate a problem node when the computer product fails.
At present, when the working state of each node of the computer is displayed, an LED display module is often adopted to perform state display so as to locate and monitor the working state of each node of the computer. When the LED display module is arranged, the LED display module is used, or the LED display module is arranged on a main board in the case, or the LED display module is externally connected with an additional independent LED display module on the case; if the LED display module provided on the main board in the case is used, the case is opened for viewing in the state display, so that the case is inconvenient to view, and in general, only one group of display state lamps are used, and the displayed state process is not detailed and comprehensive enough; if the LED display module is directly externally connected to the chassis, the additional space is required, and a professional person is required to operate the LED display module, which is troublesome.
Therefore, when the working state of the computer is displayed by using the LED display module, the prior scheme is not only visual and convenient, but also occupies extra space, and causes waste of resources.
Disclosure of Invention
In view of this, the embodiment of the application provides a system and a method for displaying the working state of a computer, so as to solve the problems that the existing scheme is not intuitive and convenient enough, and additionally occupies the space of a main board or a case, thereby wasting resources when the LED module is used for displaying the starting self-checking state of the computer.
In a first aspect, an embodiment of the present application provides a computer working status display system, the system including: BMC controller and connector; each display lamp is arranged on the connector;
the BMC controller is respectively connected with each display lamp through a GPIO bus;
the BMC controller is used for acquiring working state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp can perform state display according to the working state information.
According to the scheme, the working state information of the computer is displayed through the display lamps on the connector, the LED display module is not required to be installed on the main board in the case, or the additional independent LED display module is installed outside the case to display, so that the display is visual and convenient, and additional space and resources are saved.
With reference to the first aspect, in one implementation manner, the system further includes a CPU chip and a first memory BIOS ROM; the connector includes a first connector;
the CPU chip is connected with the BMC controller through an LPC bus, and the BMC controller is connected with the first memory BIOS ROM through an SPI bus;
the BMC controller is connected with the first connector through a UART bus, and is also connected with each display lamp of the first connector through a GPIO bus;
the BMC is used for acquiring a host power-on self-checking program of the CPU chip, adjusting the level of a GPIO bus between the BMC and the first connector according to the host power-on self-checking program, and lighting each display lamp on the first connector so that each display lamp on the first connector displays a state according to the host power-on self-checking program.
According to the scheme, the working state of the computer can be displayed through the display lamp on the first connector, and the CPU chip is connected with the BMC controller through the LPC bus and the BMC controller is connected with the BIOS ROM of the first memory through the SPI bus, so that the working state of the computer can be a host machine starting self-checking state, the scheme does not need to occupy the space of a main board or a case to set an additional LED module, the space occupation of the main board or the case and the waste of resources are reduced, and the display state of the host machine starting self-checking state can be seen without opening the case, so that the scheme is more visual and convenient.
With reference to the corresponding implementation manner of the first aspect, the first connector is provided with a first display lamp to a fourth display lamp;
a first state interface BMC_GPIO_L1 of the BMC controller is connected to a first display interface L1 of the first connector through a GPIO bus; the first display interface L1 of the first connector is positioned at the negative electrode of the first display lamp, and the positive electrode of the second display lamp;
a second state interface BMC_GPIO_L2 of the BMC controller is connected to a second display interface L2 of the first connector through a GPIO bus; the second display interface L2 of the first connector is positioned at the positive electrode of the first display lamp and the negative electrode of the second display lamp;
a third state interface BMC_GPIO_L3 of the BMC controller is connected to a third display interface L3 of the first connector through a GPIO bus; the third display interface L3 of the first connector is positioned at the negative electrode of the third display lamp, and the positive electrode of the fourth display lamp;
a fourth state interface BMC_GPIO_L4 of the BMC controller is connected to a fourth display interface L4 of the first connector through a GPIO bus; the fourth display interface L4 of the first connector is positioned at the positive electrode of the third display lamp and the negative electrode of the fourth display lamp.
According to the scheme, the first state interfaces BMC_GPIO_L1 to the fourth state interfaces BMC_GPIO_L4 of the BMC controller can be respectively connected to different display interfaces on the first connector, so that the starting-up self-checking state of the host is displayed through different display lamps on the first connector, and the starting-up self-checking state and the working process of the host are displayed more intuitively and conveniently. Furthermore, the positional relationship between the interface positions of the first display interface L1 of the first connector to the fourth display interface L4 of the first connector and the four display lamps of the first connector is defined; the working states of the computer are further displayed through the four display lamps on the first connector respectively, different working states of the starting self-checking state of the host computer are displayed more intuitively and conveniently, and the starting self-checking state of various host computers can be displayed only by lighting different display lamps on the first connector and setting the lighting rules of the display lamps.
With reference to the first aspect, in one implementation manner, the system further includes a second memory BMC ROM; the connector includes a second connector;
the BMC controller is connected with the BMC ROM of the second memory through an SPI bus;
the BMC controller is connected with the second connector through a UART bus, and is also connected with each display lamp of the second connector through a GPIO bus;
The BMC controller is used for adjusting the level of the GPIO bus between the BMC controller and the second connector according to the working state information of the BMC controller so as to control each display lamp on the second connector to be lightened and twinkle, and each display lamp on the second connector is used for carrying out state display according to the working state information of the BMC controller.
According to the scheme, the working state of the computer can be displayed through the display lamp on the second connector, and the BMC controller is connected with the BMC ROM of the second memory through the SPI bus; and the non-professional person can also provide information to the rear maintenance personnel according to the display state of the display lamp on the second connector.
With reference to the implementation manner corresponding to the first aspect, the second memory BMC ROM includes a second main memory BMC ROM1 and a second backup memory BMC ROM2;
the BMC controller is respectively connected with the second main memory BMC ROM1 and the second backup memory BMC ROM2 through SPI buses.
In the above scheme, the second memory BMC ROM is limited, and the second memory BMC ROM includes the second main memory BMC ROM1 and the second backup memory BMC ROM2, so that the operating state of the BMC controller under the second main memory BMC ROM1 and the operating state of the BMC controller under the second backup memory BMC ROM2 can be displayed by the display lamp on the second connector.
With reference to the corresponding implementation manner of the first aspect, the second connector is provided with fifth to eighth display lamps;
a fifth state interface BMC_GPIO_L5 of the BMC controller is connected to a first display interface L5 of the second connector through a GPIO bus; the first display interface L5 of the second connector is positioned at the negative electrode of the fifth display lamp, and the positive electrode of the sixth display lamp;
a sixth state interface BMC_GPIO_L6 of the BMC controller is connected to a second display interface L6 of the second connector through a GPIO bus; the second display interface L6 of the second connector is positioned at the positive electrode of the fifth display lamp and the negative electrode of the sixth display lamp;
a seventh state interface BMC_GPIO_L7 of the BMC controller is connected to a third display interface L7 of the second connector through a GPIO bus; the third display interface L7 of the second connector is positioned at the negative electrode of the seventh display lamp, and the positive electrode of the eighth display lamp;
An eighth state interface BMC_GPIO_L8 of the BMC controller is connected to a fourth display interface L8 of the second connector through a GPIO bus; the fourth display interface L8 of the second connector is positioned at the positive electrode of the seventh display lamp and the negative electrode of the eighth display lamp.
According to the scheme, the sixth state interfaces BMC_GPIO_L6 to eighth state interfaces BMC_GPIO_L8 of the BMC controller are respectively connected to different display interfaces on the second connector, so that the working state of the BMC controller is displayed through different display lamps on the second connector, and the working state and the working process of the BMC controller are displayed more intuitively and conveniently. In addition, the positional relationship between the interface positions of the first display interface L5 of the second connector to the fourth display interface L8 of the first connector and the four display lamps of the second connector is defined; the working states of the computer are further displayed through the four display lamps on the second connector, different working states of the BMC controller are displayed more intuitively and conveniently, and the working states of various BMC controllers can be displayed only by lighting the different display lamps on the second connector and setting the lighting rules of the display lamps.
With reference to the corresponding implementation manner of the first aspect, the connector is an RJ45 connector; the left and right sides of the RJ45 connector are respectively provided with a double lamp; the working state information of the computer is displayed through each display lamp on the RJ45 connector, an LED display module is not required to be installed on a main board in the case, or an additional independent LED display module is installed outside the case to display, so that the computer is visual and convenient, and additional space and resources are saved.
In a second aspect, an embodiment of the present application provides a method for displaying a working state of a computer, where the method is applied to a BMC controller of a working state display system of a computer, where the method includes:
and acquiring working state information of a computer, and adjusting the level of a GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp performs state display according to the working state information.
According to the scheme, the working state information of the computer is displayed through the display lamps on the connector, the LED display module is not required to be installed on the main board in the case, or the additional independent LED display module is installed outside the case to display, so that the display is visual and convenient, and additional space and resources are saved.
With reference to the second aspect, in an implementation manner, the acquiring the working state information of the computer, and adjusting, according to the working state information, the level of the GPIO bus between the BMC controller and the connector to control each display lamp on the connector, so that each display lamp performs state display according to the working state information, includes:
And acquiring a host power-on self-checking program of the CPU chip, and adjusting the level of a GPIO bus between the BMC controller and the first connector according to the host power-on self-checking program so as to light each display lamp on the first connector, so that each display lamp on the first connector displays the state according to the host power-on self-checking program.
According to the scheme, the display lamp on the first connector can display the state of the starting-up self-check of the host, the space of the main board or the chassis is not required to be additionally occupied, the space occupation of the main board or the chassis and the waste of resources are reduced, and the display state can be seen without opening the chassis, so that the display device is visual and convenient.
With reference to the second aspect, in an implementation manner, the acquiring the working state information of the computer, and adjusting, according to the working state information, the level of the GPIO bus between the BMC controller and the connector to control each display lamp on the connector, so that each display lamp performs state display according to the working state information, includes:
and acquiring working state information of the BMC controller, and adjusting the level of a GPIO bus between the BMC controller and the second connector according to the working state information of the BMC controller so as to control each display lamp on the second connector to be lightened and flash, so that each display lamp on the second connector performs state display according to the working state information of the BMC controller.
According to the scheme, the working state of the BMC controller is displayed through the display lamp on the second connector, so that the display state can be seen without unpacking, and the use of external diagnostic tools is reduced; and the non-professional person can also provide information to the rear maintenance personnel according to the state of the display lamp.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a computer work status display system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another computer work status display system according to some embodiments of the application;
FIG. 3 is a waveform diagram of various state interfaces for high, low, and high-low transitions according to some embodiments of the application;
FIG. 4 is a schematic diagram of another computer work status display system according to some embodiments of the application;
FIG. 5 is a schematic diagram of another computer work status display system according to some embodiments of the application;
FIG. 6 is a flow chart of a method for displaying the operating state of a computer according to an embodiment of the present application;
FIG. 7 is a schematic view of the illumination of the individual display lights of the first connector according to an embodiment of the present application;
fig. 8 is a schematic view of the lighting of the respective display lamps of the second connector according to the embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
According to the embodiment of the application, the embodiment of the computer working state display system is provided, the additional LED module is not required to occupy the space of the main board or the chassis to display the working state of the computer, the display is more visual and convenient, and the occupation of the space and the waste of resources can be reduced; fig. 1 is a schematic structural view of a computer working status display system according to an embodiment of the present application, as shown in fig. 1, the system includes: BMC controller and connector; each display lamp is arranged on the connector;
The BMC controller is respectively connected with each display lamp through a GPIO bus;
the BMC controller is used for acquiring the working state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp can perform state display according to the working state information.
According to the scheme, the working state information of the computer is displayed through the display lamps on the connector, the LED display module is not required to be installed on the main board in the case, or the additional independent LED display module is installed outside the case to display, so that the display is visual and convenient, and additional space and resources are saved.
FIG. 2 is a schematic diagram of another computer work status display system according to some embodiments of the application; the system also includes a CPU chip (CPU in FIG. 2) and a first memory BIOS ROM (BIOS ROM in FIG. 2); the connector comprises a first connector (the connector in this embodiment is preferably an RJ45 connector, that is, the first connector may be a first RJ45 connector, which is the HOST COM PORT in fig. 2);
the CPU chip is connected with the BMC controller through an LPC bus, and the BMC controller is connected with the first memory BIOS ROM through an SPI bus;
The BMC controller is connected with the first connector through a UART bus, and is also connected with each display lamp of the first connector through a GPIO bus;
the BMC controller is used for acquiring a host power-on self-checking program of the CPU chip, and adjusting the level of a GPIO bus between the BMC controller and the first connector according to the host power-on self-checking program so as to light up each display lamp on the first connector, so that each display lamp on the first connector displays the state according to the host power-on self-checking program.
Further, as shown in FIG. 2, the first connector is HOST COM PORT
The PORT is an RJ45 connector PORT with two lamps (a first lamp on the left is a green lamp, a second lamp is an orange lamp, and a first lamp on the right is a green lamp, and a second lamp is an orange lamp) respectively on the left and right, and is applied to a complete machine system (comprising a CPU chip, a memory, PCIE equipment and other working states), the BMC controller is connected to the HOST COMPORT (namely the HOST COM PORT), and GPIO buses between the BMC controller and the first connector are regulated according to a HOST starting self-checking program so as to achieve the purpose of lighting the corresponding display lamp, thereby realizing the purpose of displaying the HOST starting self-checking state through the starting and the extinguishing of the left and right double lamps of the HOST COMPORT.
Further, as shown in fig. 2, the BMC controller is also communicatively connected to the first connector (HOST COM PORT) through a UART bus.
Further, the UART bus is a communication data bus between the BMC controller and the first connector, and is used for implementing data read-write transmission between the BMC controller and the first connector.
According to the scheme, the working state of the computer can be displayed through the display lamp on the first connector, and the CPU chip is connected with the BMC controller through the LPC bus and the BMC controller is connected with the BIOS ROM of the first memory through the SPI bus, so that the working state of the computer can be a host machine starting self-checking state, the scheme does not need to occupy the space of a main board or a case to set an additional LED module, the space occupation of the main board or the case and the waste of resources are reduced, and the display state of the host machine starting self-checking state can be seen without opening the case, so that the scheme is more visual and convenient.
In some alternative embodiments, as shown in fig. 2, the first connector is provided with first to fourth display lamps;
the first state interface BMC_GPIO_L1 of the BMC controller is connected to the first display interface L1 of the first connector through a GPIO bus;
The second state interface BMC_GPIO_L2 of the BMC controller is connected to the second display interface L2 of the first connector through a GPIO bus;
the third state interface BMC_GPIO_L3 of the BMC controller is connected to the third display interface L3 of the first connector through a GPIO bus;
the fourth state interface bmc_gpio_l4 of the BMC controller is connected to the fourth display interface L4 of the first connector through a GPIO bus.
Further, the first to fourth state interfaces bmc_gpio_l1 to bmc_gpio_l4 are general purpose input/output interfaces of the BMC controller, and may be set to low level or high level output by an internal code of the BMC controller.
Code for setting the first to fourth state interfaces bmc_gpio_l1 to bmc_gpio_l4 to be high or low inside the BMC controller as follows:
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L1); setting the first state interface bmc_gpio_l1 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L1); setting the first state interface bmc_gpio_l1 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L2); setting the second state interface bmc_gpio_l2 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L2); setting the second state interface bmc_gpio_l2 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L3); setting the third state interface bmc_gpio_l3 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L3); setting the third state interface bmc_gpio_l3 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L4); setting the fourth state interface bmc_gpio_l4 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L4); setting the fourth state interface bmc_gpio_l4 to a high level;
fig. 3 is a waveform diagram of the high level, low level and high-low level transition of each state interface according to some embodiments of the present application, wherein the control voltage is 3.3v when the state interface is high, 0v when the state interface is low, and the control voltage is also switched between 0v and 3.3v when the state interface is high.
According to the scheme, the first state interfaces BMC_GPIO_L1 to the fourth state interfaces BMC_GPIO_L4 of the BMC controller can be respectively connected to different display interfaces on the first connector, so that the starting-up self-checking state of the host is displayed through different display lamps on the first connector, and the starting-up self-checking state and the working process of the host are displayed more intuitively and conveniently.
In some alternative embodiments, as shown in fig. 2, the first display interface L1 of the first connector is located at the negative electrode of the first display lamp of the first connector (i.e., the Green closest to the first display interface L1 in fig. 2), and the positive electrode of the second display lamp (i.e., the Orange closest to the first display interface L1 in fig. 2);
The second display interface L2 of the first connector is positioned at the positive electrode of the first display lamp of the first connector and at the negative electrode of the second display lamp;
the third display interface L3 of the first connector is located at the negative electrode of the third display lamp of the first connector (i.e. the Green closest to the third display interface L3 in fig. 2), and the positive electrode of the fourth display lamp (i.e. the Orange closest to the third display interface L3 in fig. 2);
the fourth display interface L4 of the first connector is located at the positive electrode of the third display lamp of the first connector and at the negative electrode of the fourth display lamp.
Further, as shown in fig. 2, the first display interface L1 of the first connector is an L1 interface of a left lamp of the first connector, and the first state interface bmc_gpio_l1 of the BMC controller is connected to the L1 interface of the left lamp of the first connector through a GPIO bus, that is, a negative electrode of a green light of the left lamp of the first connector and a positive electrode of an orange light;
the second display interface L2 of the first connector is an anode of a Green light (i.e., green closest to the first display interface L1 in fig. 1) of the first connector, and a cathode of an Orange light (i.e., orange closest to the first display interface L1 in fig. 1) of the first connector;
The third display interface L3 of the first connector is on the L3 interface of the right lamp of the first connector, the third state interface bmc_gpio_l3 of the BMC controller is connected to the L3 interface of the right lamp of the first connector through a GPIO bus, that is, the negative electrode of the right lamp Green light (i.e., the Green closest to the third display interface L3 in fig. 1) of the first connector, and the positive electrode of the Orange light (i.e., the Orange closest to the third display interface L3 in fig. 1);
the fourth display interface L4 of the first connector is on the L4 interface of the right lamp of the first connector, and the fourth state interface bmc_gpio_l4 of the BMC controller is connected to the L4 interface of the right lamp of the first connector through the GPIO bus, that is, the positive electrode of the green light of the right lamp of the first connector and the negative electrode of the orange light.
Further, as shown in fig. 2, the communication interface of the HOST COM PORT includes R1 to R8, and the communication data output interface host_uart_txd1 of the BMC controller is connected to R3 of the HOST COM PORT for inputting communication data to the first connector in consideration of the versatility of an external cable (external cable); the communication data output interface HOST_UART_RXD1 of the BMC is accessed to R6 of the HOST COMPORT and is used for receiving the output communication data of the first connector, and the signal GND corresponding to the first connector is R4 and R5 connected to the HOST COMPORT; thereafter, G1 to G3 of the first connector are GND of the first connector itself (i.e., GND-UART1 in fig. 2), and are ground of the first connector itself against static electricity or the like. The model of the first connector may be rt15_ns_0005.
The above scheme defines the positional relationship between the interface positions of the first display interface L1 of the first connector to the fourth display interface L4 of the first connector and the four display lamps of the first connector; the working states of the computer are further displayed through the four display lamps on the first connector respectively, different working states of the starting self-checking state of the host computer are displayed more intuitively and conveniently, and the starting self-checking state of various host computers can be displayed only by lighting different display lamps on the first connector and setting the lighting rules of the display lamps.
FIG. 4 is a schematic diagram of another computer work status display system according to some embodiments of the application; in some alternative embodiments, as shown in fig. 4, the system further comprises a second memory BMC ROM; the connector includes a second connector (the connector in this embodiment is preferably an RJ45 connector, that is, the second connector may be a second RJ45 connector, which is the BMC COM PORT in fig. 2);
the BMC controller is connected with the BMC ROM of the second memory through an SPI bus;
the BMC controller is connected with the second connector through a UART bus, and is also connected with each display lamp of the second connector through a GPIO bus;
The BMC controller is used for adjusting the level of the GPIO bus between the BMC controller and the second connector according to the working state information of the BMC controller so as to control each display lamp on the second connector to be lightened and flash, so that each display lamp on the second connector can perform state display according to the working state information of the BMC controller.
Further, the second connector is a BMC COM PORT, and like the first connector, the BMC COM PORT is a connector having two lamps (the first lamp on the left is a green light, the second lamp on the right is an orange light, the first lamp on the right is a green light, and the second lamp on the right is an orange light) respectively on the left and right, and is applied to the BMC controller to display the working state of the BMC controller.
Further, as shown in fig. 4, the BMC controller is also communicatively connected to the second connector (BMC COM PORT) through a UART bus.
Further, the UART bus is a communication data bus between the BMC controller and the second connector, and is used for implementing data read-write transmission between the BMC controller and the second connector.
According to the scheme, the working state of the computer can be displayed through the display lamp on the second connector, and the BMC controller is connected with the BMC ROM of the second memory through the SPI bus; and the non-professional person can also provide information to the rear maintenance personnel according to the display state of the display lamp on the second connector.
Further, as shown in fig. 4, the second memory BMC ROM includes a second main memory BMC ROM1 and a second backup memory BMC ROM2;
the BMC controller is respectively connected with the second main memory BMC ROM1 and the second backup memory BMC ROM2 through SPI buses.
In the above scheme, the second memory BMC ROM is limited, and the second memory BMC ROM includes the second main memory BMC ROM1 and the second backup memory BMC ROM2, so that the operating state of the BMC controller under the second main memory BMC ROM1 and the operating state of the BMC controller under the second backup memory BMC ROM2 can be displayed by the display lamp on the second connector.
FIG. 5 is a schematic diagram of another computer work status display system according to some embodiments of the application; the main BMC ROM1 in fig. 5 is the second main memory BMC ROM1; the backup BMC ROM2 in fig. 5 is the second backup memory BMC ROM2;
in some alternative embodiments, as shown in fig. 5, the second connector is provided with fifth to eighth display lamps;
a fifth state interface BMC_GPIO_L5 of the BMC controller is connected to a first display interface L5 of the second connector through a GPIO bus;
the sixth state interface BMC_GPIO_L6 of the BMC controller is connected to the second display interface L6 of the second connector through a GPIO bus;
the seventh state interface BMC_GPIO_L7 of the BMC controller is connected to the third display interface L7 of the second connector through a GPIO bus;
the eighth state interface bmc_gpio_l8 of the BMC controller is connected to the fourth display interface L8 of the second connector through a GPIO bus.
Further, the fifth to eighth state interfaces bmc_gpio_l5 to bmc_gpio_l8 are also general purpose input/output interfaces of the BMC controller, like the first to fourth state interfaces bmc_gpio_l1 to bmc_gpio_l4, and can be set to a low level or a high level output by an internal code of the BMC controller.
Code for setting the fifth to eighth state interfaces bmc_gpio_l5 to bmc_gpio_l8 to be high or low in the BMC controller as follows:
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L5); setting the fifth state interface bmc_gpio_l5 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L5); setting the fifth state interface bmc_gpio_l5 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L6); setting the sixth state interface bmc_gpio_l6 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L6); setting/setting a sixth state interface bmc_gpio_l6 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L7); setting the seventh state interface bmc_gpio_l7 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L7); setting the seventh state interface bmc_gpio_l7 to a high level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
= (BMC-GPIO-L8); setting the eighth state interface bmc_gpio_l8 to a low level;
*(volatile unsigned long*)(AST-GPIO-VA-BASE+GPIO-DATA-OFFSET)
|= (BMC-GPIO-L8); setting the eighth state interface bmc_gpio_l8 to a high level;
the waveforms of the high level, the low level and the high-low level transition of the fifth state interface bmc_gpio_l5 to the eighth state interface bmc_gpio_l8 are shown in fig. 3.
According to the scheme, the sixth state interfaces BMC_GPIO_L6 to eighth state interfaces BMC_GPIO_L8 of the BMC controller are respectively connected to different display interfaces on the second connector, so that the working state of the BMC controller is displayed through different display lamps on the second connector, and the working state and the working process of the BMC controller are displayed more intuitively and conveniently.
In some alternative embodiments, as shown in fig. 5, the first display interface L5 of the second connector (i.e., the Green closest to the first display interface L5 in fig. 5) is located at the negative electrode of the fifth display lamp, and the sixth display lamp (i.e., the Orange closest to the first display interface L5 in fig. 5) is located at the positive electrode;
the second display interface L6 of the second connector is positioned at the positive electrode of the fifth display lamp and the negative electrode of the sixth display lamp;
the third display interface L7 of the second connector is located at the negative electrode of the seventh display lamp (i.e. the Green closest to the third display interface L7 in fig. 5), and the positive electrode of the eighth display lamp (i.e. the Orange closest to the third display interface L7 in fig. 5);
the fourth display interface L8 of the second connector is located at the positive electrode of the seventh display lamp and the negative electrode of the eighth display lamp.
Further, as shown in fig. 5, the first display interface L5 of the second connector is on the L5 interface of the left lamp of the second connector, and the fifth state interface bmc_gpio_l5 of the BMC controller is connected to the L5 interface of the left lamp of the second connector through a GPIO bus, that is, the negative electrode of the Green light (i.e., the Green closest to the first display interface L5 in fig. 5) of the left lamp of the second connector, and the positive electrode of the Orange light (i.e., the Orange closest to the first display interface L5 in fig. 5);
The second display interface L6 of the second connector is an L6 interface of a left lamp of the second connector, and a sixth state interface BMC_GPIO_L6 of the BMC controller is connected to the L6 interface of the left lamp of the second connector through a GPIO bus, namely, the positive electrode of a green light of the left lamp of the second connector and the negative electrode of an orange light;
the third display interface L7 of the second connector is an L7 interface of a right lamp of the second connector, and the seventh state interface bmc_gpio_l7 of the BMC controller is connected to the L7 interface of the right lamp of the second connector through a GPIO bus, that is, a negative electrode of a Green light (i.e., the Green closest to the third display interface L7 in fig. 5) of the right lamp of the second connector, and a positive electrode of an Orange light (i.e., the Orange closest to the third display interface L7 in fig. 5);
the fourth display interface L8 of the second connector is an L8 interface of a right lamp of the second connector, and the eighth state interface bmc_gpio_l8 of the BMC controller is connected to the L8 interface of the right lamp of the second connector through a GPIO bus, that is, the positive electrode of the green light of the right lamp of the second connector and the negative electrode of the orange light.
Further, as shown in fig. 5, the communication interfaces of the BMC COM PORT include R1 to R8, and the communication data output interface bmc_uart_txd1 of the BMC controller is connected to R3 of the BMC COM PORT in consideration of the versatility of an external cable, for inputting communication data to the second connector; the communication data output interface BMC_UART_RXD1 of the BMC controller is accessed to R6 of the BMC COMPORT and is used for receiving the output communication data of the second connector, and the signal GND corresponding to the second connector is R4 and R5 connected to the BMC COMPORT; thereafter, G1 to G3 of the second connector are GND of the second connector itself (i.e., GND-UART1 in fig. 5), and are ground of the second connector itself against static electricity or the like. The model of the second connector may be rt15_ns_0005.
The above scheme defines the positional relationship between the interface positions of the first display interface L5 of the second connector to the fourth display interface L8 of the second connector and the four display lamps of the second connector; the working states of the computer are further displayed through the four display lamps on the second connector, different working states of the BMC controller are displayed more intuitively and conveniently, and the working states of various BMC controllers can be displayed only by lighting the different display lamps on the second connector and setting the lighting rules of the display lamps.
In this embodiment, a method for displaying a working state of a computer is provided, which may be used in a BMC controller of a system for displaying a working state of a computer as described above, and fig. 6 is a flowchart of a method for displaying a working state of a computer according to an embodiment of the present application, as shown in fig. 6, where the method includes:
step S601, acquiring working state information of a computer, and adjusting the level of a GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp performs state display according to the working state information.
In some optional embodiments, a host power-on self-checking program of the CPU chip is obtained, and the level of the GPIO bus between the BMC controller and the first connector is adjusted according to the host power-on self-checking program, so as to light up each display lamp on the first connector, so that each display lamp on the first connector performs status display according to the host power-on self-checking program.
Further, a host power-on self-checking program in the CPU chip is obtained through the LPC bus, and according to the host power-on self-checking program, the first state interface BMC_GPIO_L1 to the fourth state interface BMC_GPIO_L4 of the BMC controller are respectively set to be high level or low level so as to respectively light each display lamp of the first connector.
Further, the host startup self-checking program comprises the steps of starting up the host, finishing the host, triggering the BMC controller to receive an LPC reset signal, acquiring storage data in the BIOS ROM of the first memory by the CPU chip, updating the self-starting firmware of the CPU chip, finishing the initialization of the memory storage controller, finishing the initialization of the particles of the memory, finishing the activation of the core of the CPU chip, entering a host startup finishing interface and the like.
Fig. 7 is a schematic view showing the lighting of each display lamp of the first connector according to the embodiment of the present application, and as shown in fig. 7, the steps of lighting each display lamp of the first connector are as follows:
1. when the start button is pressed and the host starts to start, the state of the display lamp of the first connector is as follows:
at this time, the BMC controller receives a host start-up signal, and sets a first state interface bmc_gpio_l1 of the BMC controller to a low level, and sets a second state interface bmc_gpio_l2 to a high level, and at this time, the green light of the left lamp of the first connector (i.e., the first display lamp of the first connector) has a negative electrode of a low level, and the positive electrode of the green light of the left lamp of the first connector has a high level, so that the green light of the left lamp is turned on; meanwhile, the third state interface bmc_gpio_l3 and the fourth state interface bmc_gpio_l4 are set to be at low level, and at this time, the green light on the right side of the first connector (i.e. the third display light of the first connector) and the light orange (i.e. the fourth display light of the first connector) are both at low level, so that the right light is not turned on.
2. At the end of power-on of the host computer, the state of the display lamp of the first connector:
when the BMC controller receives that the host is powered up, the BMC controller sets a first state interface BMC_GPIO_L1 to be high level, a second state interface BMC_GPIO_L2 is set to be low level, at the moment, the negative electrode of an orange lamp of a left lamp of the first connector (namely a second display lamp of the first connector) is low level, the positive electrode of the orange lamp of the left lamp of the first connector is high level, and then the left orange lamp is lighted; meanwhile, the third state interface BMC_GPIO_L3 and the fourth state interface BMC_GPIO_L4 are set to be low level, and at the moment, the positive and negative poles of the orange light of the right lamp of the first connector are both low level, so that the right lamp is not lighted.
When the bmc controller receives the trigger of the LPC reset signal, the state of the display lamp of the first connector (corresponding to step5 of fig. 7):
when the BMC controller receives the trigger of the LPC reset signal, the BMC controller sets a third state interface BMC_GPIO_L3 to be low level, and a fourth state interface BMC_GPIO_L4 is set to be high level, at the moment, the green light negative electrode of the right lamp of the first connector is low level, the positive electrode is high level, and then the right green light is lightened; meanwhile, the first state interface BMC_GPIO_L1 and the second state interface BMC_GPIO_L2 are both set to be low level, and at the moment, the positive and negative poles of the orange light of the left lamp of the first connector are both low level, so that the left lamp is not lighted.
When the cpu chip reads the software (stored data) in the first memory BIOS ROM under the BMC controller through the LPC bus, the status of the display lamp of the first connector (corresponding to step6 of fig. 7):
when the BMC controller receives software (stored data) in a first memory BIOS ROM under the BMC controller, which is read by a CPU chip through an LPC bus, the BMC controller sets a third state interface BMC_GPIO_L3 to be in a high level state, and sets a fourth state interface BMC_GPIO_L4 to be in a low level state, at the moment, the negative electrode of an orange lamp of a right lamp of the first connector is in a low level, the positive electrode of the orange lamp of the right lamp of the first connector is in a high level, and then the right orange lamp is lightened; meanwhile, the third state interface BMC_GPIO_L3 and the fourth state interface BMC_GPIO_L4 are set to be low level, and at the moment, the positive and negative poles of the orange light of the left lamp of the first connector are both low level, so that the left lamp is not lighted.
5. When the self-starting firmware of the master CPU chip and the slave CPU chip is updated, the state of the display lamp of the first connector (corresponding to step9 of fig. 7):
at the moment, the BMC controller receives self-starting firmware updates of the main CPU chip and the auxiliary CPU chip, the BMC controller sets a first state interface BMC_GPIO_L1 to be low level, a second state interface BMC_GPIO_L2 is set to be high level, at the moment, the green light negative electrode of a left lamp of the first connector is low level, the positive electrode of the left lamp of the first connector is high level, and then the left green light is lighted; meanwhile, the BMC controller sets the third state interface BMC_GPIO_L3 to be low level, the fourth state interface BMC_GPIO_L4 is set to be high level, at the moment, the green light negative electrode of the right lamp of the first connector is low level, the positive electrode of the right lamp is high level, and then the right green light is lighted.
6. When the initialization of the memory storage controller is completed, the status of the display lamp of the first connector (corresponding to step10 of fig. 7):
at the moment, the BMC controller receives the completion of the initialization of the memory storage controller, the BMC controller sets a first state interface BMC_GPIO_L1 to be low level, a second state interface BMC_GPIO_L2 is set to be high level, at the moment, the green light of the left lamp of the first connector is low level, the positive electrode is high level, and then the green light on the left side is lighted; meanwhile, the BMC controller sets the third state interface BMC_GPIO_L3 to be in a high level, the fourth state interface BMC_GPIO_L4 is set to be in a low level state, at the moment, the negative electrode of the orange lamp of the right side lamp of the first connector is in a low level, the positive electrode of the orange lamp of the right side lamp of the first connector is in a high level, and then the right side orange lamp is lighted.
7. Upon completion of the initialization of the memory particles, the status of the display lamp of the first connector (corresponding to step14 of fig. 7):
at this time, the BMC controller receives the completion of the particle initialization of the memory, and sets the first state interface BMC_GPIO_L1 to be high level, and the second state interface BMC_GPIO_L2 to be low level, at this time, the negative electrode of the orange lamp of the left lamp of the first connector is low level, and the positive electrode is high level, so that the left orange lamp is lighted; meanwhile, the BMC controller sets the third state interface BMC_GPIO_L3 to be low level, the fourth state interface BMC_GPIO_L4 is set to be high level, at the moment, the green light negative electrode of the right lamp of the first connector is low level, the positive electrode of the right lamp is high level, and then the right green light is lighted.
8. When the activation of the master CPU chip core and the slave CPU chip core is completed, the state of the display lamp of the first connector (corresponding to step16 of fig. 7):
at the moment, the BMC controller receives the completion of the activation of the master-slave CPU chip, the BMC controller sets a first state interface BMC_GPIO_L1 to be in a high level state, and a second state interface BMC_GPIO_L2 is set to be in a low level state, at the moment, the negative electrode of the orange lamp of the left lamp of the first connector is in a low level, the positive electrode of the orange lamp of the left lamp of the first connector is in a high level, and then the left orange lamp is lightened; meanwhile, the BMC controller sets the third state interface BMC_GPIO_L3 to be in a high level, the fourth state interface BMC_GPIO_L4 is set to be in a low level state, at the moment, the negative electrode of the orange lamp of the right side lamp of the first connector is in a low level, the positive electrode of the orange lamp of the right side lamp of the first connector is in a high level, and then the right side orange lamp is lighted.
9. When entering the host startup completion interface, the status of the display light of the first connector:
at this time, when the BMC controller receives the host start-up completion interface, the BMC controller sets the first state interface bmc_gpio_l1, the second state interface bmc_gpio_l2, the third state interface bmc_gpio_l3, and the fourth state interface bmc_gpio_l4 to be at a low level at the same time, and at this time, both the green and orange lamps of the two side lamps of the first connector are at a low level, so that both the left and right side lamps are not turned on.
Fig. 7 only shows a logical sequence of the individual display lights on the first connector being lit, but in some cases the individual display lights on the first connector may be lit in a different logical sequence than here.
According to the scheme, the level of the first state interfaces BMC_GPIO_L1 to the level of the fourth state interfaces BMC_GPIO_L4 of the BMC controller are set according to the host starting self-checking program so as to control the on and off of the four display lamps on the first connector, further, the host starting self-checking state is displayed, the space of a main board or a case is not required to be occupied additionally, the space occupation of the main board or the case and the waste of resources are reduced, the display state can be seen without opening the case, and the method is more visual and convenient.
In some optional embodiments, the working state information of the BMC controller is obtained, and the level of the GPIO bus between the BMC controller and the second connector is adjusted according to the working state information of the BMC controller, so as to control each display lamp on the second connector to light and flash, so that each display lamp on the second connector performs state display according to the working state information of the BMC controller.
Further, acquiring state information of the BMC controller, and setting a fifth state interface BMC_GPIO_L5 to an eighth state interface BMC_GPIO_L8 of the BMC controller to be high level or low level respectively according to the state information of the BMC controller so as to light each display lamp of the second connector respectively; the state information of the BMC controller comprises the working state of the BMC controller under the second main memory BMC ROM1 and the working state of the BMC controller under the second backup memory BMC ROM 2.
Further, the state information of the BMC controller further includes a working state of the embedded ARM module of the BMC controller under the second main memory BMC ROM1 and a working state of the embedded ARM module of the BMC controller under the second backup memory BMC ROM2, and the working state of the BMC controller under the second main memory BMC ROM1 and the working state of the BMC controller under the second backup memory BMC ROM2 are displayed through different lighting sequences and flashing frequencies of a fifth display lamp (green light of a left lamp of the second connector) and a sixth display lamp (orange light of the left lamp of the second connector) of the second connector; and displaying the working state of the embedded ARM module of the BMC controller under the second main memory BMC ROM1 and the working state of the embedded ARM module of the BMC controller under the second backup memory BMC ROM2 through different lighting sequences and flashing frequencies of a seventh display lamp (green lamp of the right lamp of the second connector) and an eighth display lamp (orange lamp of the right lamp of the second connector).
Further, fig. 8 is a schematic view showing the lighting of each display lamp of the second connector according to the embodiment of the present application; as shown in fig. 8, the steps of the BMC controller for lighting the respective display lamps of the second connector in the operating state under the second main memory BMC ROM1 are as follows:
When the BMC controller is not started, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is not powered on, and the fifth state interface bmc_gpio_l5 and the sixth state interface bmc_gpio_l6 of the BMC controller are both in a low level state, and at this time, the green light state of the left light of the second connector (i.e., the fifth display light of the second connector) is not on;
when the BMC controller is started, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on and started, and the BMC controller sets the fifth state interface bmc_gpio_l5 to be in a low level state, and the sixth state interface bmc_gpio_l6 is set to be in a high level state, and at this time, the green light cathode of the left lamp of the second connector is in a low level, and the positive electrode is in a high level, so that the green light is turned on.
When the starting of the BMC controller is completed, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is started and completed, the BMC controller sets the fifth state interface bmc_gpio_l5 to be in a high-low level conversion state of 5Hz, and the sixth state interface bmc_gpio_l6 is set to be in a high level state, at this time, the green light negative electrode of the left lamp of the second connector is in a high-low level conversion state of 5Hz, and the positive electrode is in a high level. When the negative electrode is at a low level and the positive electrode is at a high level, the green light is lighted, and when the negative electrode is at a high level and the positive electrode is at a high level, the green light is not lighted. When the negative electrode is continuously switched between high and low levels and the positive electrode is always high, the green lamp point is further flashed.
When the BMC controller is in an operating state under the second backup memory BMC ROM2, the steps of lighting the display lamps of the second connector are as follows:
when the BMC controller is not started, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is not powered on, the fifth state interface bmc_gpio_l5 and the sixth state interface bmc_gpio_l6 are both in a low level state, and at this time, the orange lamp of the left lamp of the second connector (i.e., the sixth display lamp of the second connector) is in a non-lighting state;
the bmc controller starts the lamp, the status of the display lamp of the second connector:
at this time, the BMC controller is powered on and started, and the BMC controller sets the fifth state interface bmc_gpio_l5 to be in a high level state, and the sixth state interface bmc_gpio_l6 is set to be in a low level state, at this time, the negative electrode of the orange lamp of the left lamp of the second connector is in a low level, and the positive electrode is in a high level, so that the orange lamp is turned on.
When the starting of the BMC controller is completed, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is started and completed, the BMC controller sets the fifth state interface bmc_gpio_l5 to be in a high level state, and the sixth state interface bmc_gpio_l6 is set to be in a high-low level conversion state of 5Hz, and at this time, the orange lamp cathode of the left lamp of the second connector is in high-low level conversion of 5Hz, and the anode is in high level. When the negative electrode is at a low level and the positive electrode is at a high level, the orange lamp is lighted, and when the negative electrode is at a high level and the positive electrode is at a high level, the orange lamp is not lighted. When the negative electrode is continuously switched between high and low levels and the positive electrode is always high, the orange lamp is further flashed.
When the embedded ARM module of the BMC controller is in a working state under the BMC ROM1 of the second main memory, the steps of lighting each display lamp of the second connector are as follows:
when the ARM chip is not started, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is not powered on, the seventh state interface bmc_gpio_l7 and the eighth state interface bmc_gpio_l8 are both in a low level state, and at this time, the green light state of the right lamp of the second connector (i.e., the seventh display lamp of the second connector) is not on;
when the ARM module reads instructions from the flash memory to run programs, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on, and sets the seventh state interface bmc_gpio_l7 to be in a high-low level conversion state of 10Hz, and the eighth state interface bmc_gpio_l8 is set to be in a high level state, at this time, the green light cathode of the right lamp of the second connector is in high-low level conversion of 10Hz, and the positive electrode is in high level, so that the green light point is flashed at 10 Hz.
When the ARM module reads instructions from the memory particles to run a program (the interrupt function is not started), the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on and started, the BMC controller sets the seventh state interface bmc_gpio_l7 to be in a high-low level conversion state of 2Hz, and the eighth state interface bmc_gpio_l8 is set to be in a high level state, at this time, the green light negative electrode of the right lamp of the second connector is in a high-low level conversion state of 2Hz, and the positive electrode is in a high level, so that the green light point is flashed at 2 Hz.
When the ARM module reads the instruction from the memory particle to run the program (enabling the interrupt function, which is the normal operation mode), the state of the display lamp of the second connector is:
at this time, the BMC controller is powered on, and the BMC controller sets the seventh state interface bmc_gpio_l7 to be in a high-low level conversion state of 0.5Hz, and sets the eighth state interface bmc_gpio_l8 to be in a high level state, and at this time, the green light negative electrode of the right lamp of the second connector is in high-low level conversion of 0.5Hz, and the positive electrode is in high level, so that the green light point is flashed at 0.5 Hz.
When the ARM module is in an abnormal working mode and some interrupts are out of service for more than 2 seconds, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on, and the BMC controller sets the seventh state interface bmc_gpio_l7 to be in a high-low level conversion state of 0.1Hz, and sets the eighth state interface bmc_gpio_l8 to be in a high level state, and at this time, the green light negative electrode of the right lamp of the second connector is in high-low level conversion of 0.1Hz, and the positive electrode is in high level, so that the green light point is flashed at 0.1 Hz.
When the embedded ARM module of the BMC controller is in a working state under the BMC ROM2 of the second backup memory, the steps of lighting each display lamp of the second connector are as follows:
When the ARM module is not started, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is not powered on, the seventh state interface bmc_gpio_l7 and the eighth state interface bmc_gpio_l8 are both in a low level state, and at this time, the orange lamp of the right lamp of the second connector (i.e., the eighth display lamp of the second connector) is in a non-lighting state;
when the ARM module reads instructions from the flash memory to run programs, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on, the BMC sheet sets the eighth state interface bmc_gpio_l8 to be in a high-low level conversion state of 10Hz, and the seventh state interface bmc_gpio_l7 is set to be in a high level state, at this time, the negative electrode of the orange lamp of the right lamp of the second connector is in a high-low level conversion state of 10Hz, and the positive electrode is in a high level, so that the orange lamp point is flashed at 10 Hz.
When the ARM module reads instructions from the memory particles to run a program (the interrupt function is not started), the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on, and sets the eighth state interface bmc_gpio_l8 to be in a high-low level conversion state of 2Hz, and the seventh state interface bmc_gpio_l7 is set to be in a high level state, at this time, the negative electrode of the orange lamp of the right lamp of the second connector is in a high-low level conversion state of 2Hz, and the positive electrode is in a high level, so that the orange lamp point is flashed at 2 Hz.
When the ARM module reads the instruction from the memory particle to run the program (enabling the interrupt function, which is the normal operation mode), the state of the display lamp of the second connector is:
at this time, the BMC controller is powered on, and sets the eighth state interface bmc_gpio_l8 to be in a high-low level conversion state of 0.5Hz, and the seventh state interface bmc_gpio_l7 is set to be in a high level state, at this time, the negative electrode of the orange lamp of the right lamp of the second connector is in a high-low level conversion state of 0.5Hz, and the positive electrode is in a high level, so that the orange lamp point is flashed at 0.5 Hz.
When the ARM module is in an abnormal working mode and some interrupts are out of service for more than 2 seconds, the state of the display lamp of the second connector is as follows:
at this time, the BMC controller is powered on, and sets the eighth state interface bmc_gpio_l8 to be in a high-low level conversion state of 0.1Hz, and the seventh state interface bmc_gpio_l7 is set to be in a high level state, at this time, the negative electrode of the orange lamp of the right lamp of the second connector is in a high-low level conversion state of 0.1Hz, and the positive electrode is in a high level, so that the orange lamp point is flashed at 0.1 Hz.
Fig. 8 only shows a logical sequence of the individual display lights that illuminate the second connector, but in some cases the second connector may be illuminated in a different sequence than here.
According to the scheme, according to the state information of the BMC controller, the levels of the fifth state interface BMC_GPIO_L5 to the eighth state interface BMC_GPIO_L8 of the BMC controller are set to control the on and off of the four display lamps on the second connector, so that the working state of the BMC controller is displayed, the display state can be seen without unpacking, and the use of external diagnostic tools is reduced; and the non-professional person can also provide information to the rear maintenance personnel according to the state of the display lamp.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A computer work status display system, the system comprising: BMC controller and connector; each display lamp is arranged on the connector;
the BMC controller is respectively connected with each display lamp through a GPIO bus;
the BMC controller is used for acquiring working state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp can perform state display according to the working state information.
2. The system of claim 1, further comprising a CPU chip and a first memory BIOS ROM; the connector includes a first connector;
the CPU chip is connected with the BMC controller through an LPC bus, and the BMC controller is connected with the first memory BIOS ROM through an SPI bus;
the BMC controller is connected with the first connector through a UART bus, and is also connected with each display lamp of the first connector through a GPIO bus;
the BMC is used for acquiring a host power-on self-checking program of the CPU chip, adjusting the level of a GPIO bus between the BMC and the first connector according to the host power-on self-checking program, and lighting each display lamp on the first connector so that each display lamp on the first connector displays a state according to the host power-on self-checking program.
3. The system of claim 2, wherein the first connector has first to fourth display lights disposed thereon;
a first state interface BMC_GPIO_L1 of the BMC controller is connected to a first display interface L1 of the first connector through a GPIO bus; the first display interface L1 of the first connector is positioned at the negative electrode of the first display lamp, and the positive electrode of the second display lamp;
a second state interface BMC_GPIO_L2 of the BMC controller is connected to a second display interface L2 of the first connector through a GPIO bus; the second display interface L2 of the first connector is positioned at the positive electrode of the first display lamp and the negative electrode of the second display lamp;
a third state interface BMC_GPIO_L3 of the BMC controller is connected to a third display interface L3 of the first connector through a GPIO bus; the third display interface L3 of the first connector is positioned at the negative electrode of the third display lamp, and the positive electrode of the fourth display lamp;
a fourth state interface BMC_GPIO_L4 of the BMC controller is connected to a fourth display interface L4 of the first connector through a GPIO bus; the fourth display interface L4 of the first connector is positioned at the positive electrode of the third display lamp and the negative electrode of the fourth display lamp.
4. A system according to any one of claims 1 to 3, wherein the system further comprises a second memory BMC ROM; the connector includes a second connector;
the BMC controller is connected with the BMC ROM of the second memory through an SPI bus;
the BMC controller is connected with the second connector through a UART bus, and is also connected with each display lamp of the second connector through a GPIO bus;
the BMC controller is used for adjusting the level of the GPIO bus between the BMC controller and the second connector according to the working state information of the BMC controller so as to control each display lamp on the second connector to be lightened and twinkle, and each display lamp on the second connector is used for carrying out state display according to the working state information of the BMC controller.
5. The system of claim 4, wherein the second memory BMC ROM comprises a second main memory BMC ROM1 and a second backup memory BMC ROM2;
the BMC controller is respectively connected with the second main memory BMC ROM1 and the second backup memory BMC ROM2 through SPI buses.
6. The system of claim 5, wherein a fifth display light to an eighth display light are provided on the second connector;
A fifth state interface BMC_GPIO_L5 of the BMC controller is connected to a first display interface L5 of the second connector through a GPIO bus; the first display interface L5 of the second connector is positioned at the negative electrode of the fifth display lamp, and the positive electrode of the sixth display lamp;
a sixth state interface BMC_GPIO_L6 of the BMC controller is connected to a second display interface L6 of the second connector through a GPIO bus; the second display interface L6 of the second connector is positioned at the positive electrode of the fifth display lamp and the negative electrode of the sixth display lamp;
a seventh state interface BMC_GPIO_L7 of the BMC controller is connected to a third display interface L7 of the second connector through a GPIO bus; the third display interface L7 of the second connector is positioned at the negative electrode of the seventh display lamp, and the positive electrode of the eighth display lamp;
an eighth state interface BMC_GPIO_L8 of the BMC controller is connected to a fourth display interface L8 of the second connector through a GPIO bus; the fourth display interface L8 of the second connector is positioned at the positive electrode of the seventh display lamp and the negative electrode of the eighth display lamp.
7. A system according to any one of claims 1 to 3, wherein the connector is an RJ45 connector.
8. A method for displaying a working state of a computer, wherein the method is applied to a BMC controller of a working state display system of any one of claims 1 to 7, and the method comprises:
and acquiring working state information of a computer, and adjusting the level of a GPIO bus between the BMC controller and the connector according to the working state information so as to control each display lamp on the connector, so that each display lamp performs state display according to the working state information.
9. The method of claim 8, wherein the obtaining the operating state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the operating state information, so as to control each display lamp on the connector, so that each display lamp performs state display according to the operating state information, includes:
and acquiring a host power-on self-checking program of the CPU chip, and adjusting the level of a GPIO bus between the BMC controller and the first connector according to the host power-on self-checking program so as to light each display lamp on the first connector, so that each display lamp on the first connector displays the state according to the host power-on self-checking program.
10. The method of claim 8, wherein the obtaining the operating state information of the computer, and adjusting the level of the GPIO bus between the BMC controller and the connector according to the operating state information, so as to control each display lamp on the connector, so that each display lamp performs state display according to the operating state information, includes:
and acquiring working state information of the BMC controller, and adjusting the level of a GPIO bus between the BMC controller and the second connector according to the working state information of the BMC controller so as to control each display lamp on the second connector to be lightened and flash, so that each display lamp on the second connector performs state display according to the working state information of the BMC controller.
CN202310436225.0A 2023-04-21 2023-04-21 Computer working state display system and method Active CN116662124B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310436225.0A CN116662124B (en) 2023-04-21 2023-04-21 Computer working state display system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310436225.0A CN116662124B (en) 2023-04-21 2023-04-21 Computer working state display system and method

Publications (2)

Publication Number Publication Date
CN116662124A true CN116662124A (en) 2023-08-29
CN116662124B CN116662124B (en) 2023-12-22

Family

ID=87708741

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310436225.0A Active CN116662124B (en) 2023-04-21 2023-04-21 Computer working state display system and method

Country Status (1)

Country Link
CN (1) CN116662124B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104679116A (en) * 2013-11-28 2015-06-03 英业达科技有限公司 Server cabinet system, circuit board combined system and circuit board of circuit combined system
CN206312126U (en) * 2016-12-26 2017-07-07 郑州云海信息技术有限公司 A kind of server admin functional test plate
CN107203458A (en) * 2017-05-23 2017-09-26 郑州云海信息技术有限公司 A kind of server state information display device and method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104679116A (en) * 2013-11-28 2015-06-03 英业达科技有限公司 Server cabinet system, circuit board combined system and circuit board of circuit combined system
CN206312126U (en) * 2016-12-26 2017-07-07 郑州云海信息技术有限公司 A kind of server admin functional test plate
CN107203458A (en) * 2017-05-23 2017-09-26 郑州云海信息技术有限公司 A kind of server state information display device and method

Also Published As

Publication number Publication date
CN116662124B (en) 2023-12-22

Similar Documents

Publication Publication Date Title
US5293494A (en) Personal computer for setting, in a software setup operation normal/reverse display, connection of an external device, and an automatic display off function
US20210315115A1 (en) Electronic device, expansion card assembly, server device and management method therefor
CN112860298A (en) Remote BIOS (basic input output System) upgrading implementation method and system
CN113760667A (en) Hard disk management method and device, readable storage medium and electronic equipment
EP0404182B1 (en) Personal computer for setting, in setup operation, normal/reverse display, external device, and automatic display off
CN116662124B (en) Computer working state display system and method
CN110618744A (en) Novel GPU Carrier board card
JP6575715B1 (en) Information processing system and relay device
CN112685054A (en) Portable board card burning device and method
CN208654779U (en) A kind of firmware based on multiple types bus more new system offline
CN116627729A (en) External connection cable, external connection cable in-place detection device, startup self-checking method and system
CN101727333A (en) Method for updating firmware in microprocessor and firmware updating system
CN214042302U (en) Portable board card burning device
Intel Intel® Desktop Board DG41TY Technical Product Specification
Intel Intel® Desktop Board DG965PZ Technical Product Specification
CN110612502B (en) Dongle with rechargeable supercapacitor-based power supply
CN215987289U (en) Abnormal display device for server equipment
CN216387781U (en) Gateway control system of open source hardware single board computer
CN113821230A (en) System firmware updating mode design of embedded system
CN110095735B (en) Power supply short circuit detection device and equipment
CN116955098A (en) Method for displaying fault information by display lamp and related equipment
CN104035792A (en) Signal mainboard upgrading device and method
TWI259599B (en) Battery power inspection device formed together with the system LED of a notebook computer and the method thereof
CN218630778U (en) USB burning circuit
CN211149437U (en) OCP3.0 hot plug framework

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant