CN116648782A - Chip, electronic equipment and film perforation forming method - Google Patents
Chip, electronic equipment and film perforation forming method Download PDFInfo
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- CN116648782A CN116648782A CN202180086460.9A CN202180086460A CN116648782A CN 116648782 A CN116648782 A CN 116648782A CN 202180086460 A CN202180086460 A CN 202180086460A CN 116648782 A CN116648782 A CN 116648782A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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Abstract
The embodiment of the application provides a film perforation forming method, a chip and electronic equipment. Relates to the technical field of semiconductors, and can avoid the grinding fluid from immersing into the film perforation. The chip comprises: the chip comprises a substrate, an electronic component arranged on the substrate, wherein the electronic component is isolated from a wiring layer by a dielectric layer, the chip further comprises a film layer perforation, the film layer perforation comprises a hole penetrating through the dielectric layer, a first filling layer, a spacer layer and a second filling layer are sequentially stacked in the hole along the axial direction of the hole, and an adhesion layer is arranged at the position of the second filling layer, which is contacted with the side wall surface of the hole; wherein the first filling layer, the second filling layer and the spacer layer are all made of conductive materials, the material of the spacer layer is different from that of the first filling layer, and the material of the spacer layer is different from that of the second filling layer; in addition, the first filling layer is disposed near the electronic component, and the second filling layer is disposed near the wiring layer to electrically connect the electronic component and the wiring layer.
Description
The present application relates to the field of semiconductor technology, and more particularly, to a method for forming a film perforation capable of avoiding occurrence of voids in a conductive layer, a chip including the film perforation, and an electronic device including the chip.
As integrated circuit technology continues to advance, chips further advance to integrate and miniaturize, and transistor feature sizes shrink accordingly, so that new challenges are presented to metal interconnect hole filling technology.
Fig. 1 is a conventional structure of film perforation for metal interconnection, that is, the wiring layers on opposite sides of the substrate are connected by film perforation as shown in fig. 1, and the film perforation is processed by firstly forming holes in the substrate and then filling conductive materials in the holes to form the film perforation structure capable of realizing electrical conduction.
In the process of preparing the film perforation shown in fig. 1, as shown in fig. 2, since the conductive layer made of the conductive material is directly in contact with the sidewall surface of the hole, a phenomenon in which a gap is formed between the conductive layer and the sidewall surface of the hole shown in fig. 2 easily occurs. In this way, the polishing liquid is easily permeated into the gap during the chemical mechanical polishing (chemical mechanical polishing, CMP) after the hole filling, and the CMP process can be understood as removing the conductive material (shown as a dotted line frame in fig. 2) located on the substrate surface a as in fig. 2, that is, planarizing the surface of the substrate.
The polishing liquid is usually selected to have a certain corrosiveness, and if the gap between the conductive layer and the sidewall surface of the hole is filled with the polishing liquid, the polishing liquid can corrode the conductive material, so as to reduce the conductive performance of the conductive channel, and even cause the perforation of the film layer to fail.
Disclosure of Invention
The embodiment of the application provides a chip, electronic equipment comprising the chip and a method for forming film perforation in the chip, and mainly aims to provide a film perforation structure capable of preventing grinding fluid from being immersed in the film perforation.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:
in a first aspect, the present application provides an electronic device, including a film layer, which may be a substrate or a dielectric layer, and in which a film layer through hole for electrically connecting a first wiring layer and a second wiring layer is formed, the film layer through hole including a hole formed in the film layer, a first filling layer, a spacer layer, and a second filling layer are sequentially formed in the hole and along an axial direction of the hole, the first filling layer is electrically connected to the first wiring layer at one end of the film layer through hole, the second filling layer is electrically connected to the second wiring layer at the other end of the film layer through hole, and an adhesion layer is formed at a position of the second filling layer in contact with a sidewall surface of the hole, where the first filling layer, the spacer layer, and the second filling layer are each made of a conductive material, for example, a material of the spacer layer may be different from a material of the first filling layer, and a material of the spacer layer may be different from a material of the second filling layer.
In the electronic device provided by the embodiment of the application, the holes comprising the first filling layer, the second filling layer, the spacing layer and the adhesion layer form the film perforation structure, and the first filling layer, the spacing layer and the second filling layer are all made of conductive materials, so that the film perforation can realize electric conduction between the first wiring layer and the second wiring layer.
Based on the description, in the film perforation process, after the first filling layer, the second filling layer, the spacer layer and the adhesive layer are completed, when the CMP process is performed, the adhesive layer exists between the second filling layer and the side wall surface of the hole, and can promote the second filling layer to be attached to the hole together, so that the occurrence of pores between the second filling layer and the side wall surface of the hole is avoided, and the grinding liquid in the CMP process is blocked from being immersed into the film perforation, so that the corrosion of the second filling layer by the grinding liquid is prevented.
In a second aspect, the present application provides a chip comprising: the electronic component comprises a transistor and a wiring layer formed on one side of the electronic component far away from the substrate, wherein the wiring layer is a signal wire, the electronic component and the wiring layer are isolated by a dielectric layer, the chip further comprises a film layer perforation, the film layer perforation comprises a hole penetrating through the dielectric layer, a first filling layer, a spacer layer and a second filling layer are sequentially stacked in the hole along the axial direction of the hole, and an adhesive layer is arranged at the position of the second filling layer, which is contacted with the side wall surface of the hole; wherein the first filling layer, the second filling layer and the spacer layer are all made of conductive materials, the material of the spacer layer is different from that of the first filling layer, and the material of the spacer layer is different from that of the second filling layer; in addition, the first filling layer is disposed near the electronic component, and the second filling layer is disposed near the wiring layer to electrically connect the electronic component and the wiring layer.
In the chip provided by the embodiment of the application, since the film layer perforation including the first filling layer, the second filling layer, the spacer layer and the adhesion layer is formed in the dielectric layer, such a film layer perforation structure may be referred to as a dielectric perforation (through dielectric via, TDV) or contact (contact) structure.
In the process of forming the chip, after the electronic component is integrated on the substrate, a dielectric layer is formed on the substrate containing the electronic component, a hole is formed in the dielectric layer, a first filling layer, a spacing layer and a second filling layer are sequentially formed along the axial direction of the hole and along the direction far away from the electronic component, an adhesion layer is formed between the second filling layer and the side wall surface of the hole, and finally a CMP process is performed. Because the adhesive layer exists between the second filling layer and the side wall surface of the hole, the adhesive layer can promote the second filling layer to be attached to the hole together, so that the occurrence of pores between the second filling layer and the side wall surface of the hole is avoided, and further, the grinding fluid in the CMP process is blocked from being immersed into the film perforation, and the corrosion of the grinding fluid to the second filling layer is avoided.
In a third aspect, the present application provides a chip comprising: the chip further comprises a film layer perforation, wherein the film layer perforation comprises a hole penetrating through the substrate and at least one part of the active layer, a first filling layer, a spacing layer and a second filling layer are sequentially stacked in the hole along the axial direction of the hole, and an adhesive layer is arranged at the position of the second filling layer, which is contacted with the side wall surface of the hole; wherein the first filling layer, the second filling layer and the spacer layer are all made of conductive materials, the material of the spacer layer is different from that of the first filling layer, and the material of the spacer layer is different from that of the second filling layer; the first filling layer is disposed near the active layer, and the second filling layer is disposed near the wiring layer to electrically connect the active layer and the wiring layer.
In the chip provided in the embodiment of the present application, since the film perforation including the first filling layer, the second filling layer, the spacer layer, and the adhesion layer is formed in the substrate, for example, when the substrate includes silicon, the film perforation structure may be referred to as a through silicon perforation (through silicon via, TSV). In addition, the substrate may be a gallium arsenide (GaAs) substrate, a gallium arsenic phosphate (GaAsP) substrate, or the like.
In the process of forming the chip, after an active layer is formed on a substrate, a hole is formed in the substrate, a first filling layer, a spacer layer and a second filling layer are sequentially formed along the axial direction of the hole and along the direction away from the active layer, an adhesion layer is formed between the second filling layer and the side wall surface of the hole, and finally a CMP process is performed. Because the adhesive layer exists between the second filling layer and the side wall surface of the hole, the adhesive layer can promote the second filling layer to be attached to the hole together, so that the occurrence of pores between the second filling layer and the side wall surface of the hole is avoided, and further, the grinding fluid in the CMP process is blocked from being immersed into the film perforation, and the corrosion of the grinding fluid to the second filling layer is avoided.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspect, a height dimension of the first filling layer along an axial direction of the hole is larger than a height dimension of the second filling layer along the axial direction of the hole.
When the film layer is perforated, the first filling layer is usually formed by adopting a selective growth process stacked along the axial direction of the hole, so that the phenomenon that the closing-in is improved and gaps are not formed in the first filling layer is avoided, the first filling layer is arranged higher than the second filling layer, and further, the phenomenon that the perforation resistance of the film layer is increased because gaps are formed in the first filling layer under the condition that the grinding fluid cannot be immersed into the film layer for perforation is ensured.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspect, a resistivity of the conductive material of the second filling layer is smaller than or equal to a resistivity of the conductive material of the first filling layer.
The resistivity of the second filling layer is set to be smaller than or equal to that of the first filling layer, so that the perforated resistance of the film layer can be further reduced, and the signal transmission efficiency between the first wiring layer and the second wiring layer is improved.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspect, the first filling layer and the second filling layer are manufactured by using a same process. For example, a selective growth process may be employed, and for example, a selective growth chemical vapor deposition (chemical vapor deposition, CVD) process or a selective growth atomic layer deposition (atomic layer deposition, ALD) process may be employed.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspects, the electronic device or the chip further comprises a barrier layer, which is disposed at a position where the adhesion layer is in contact with the second filling layer. The barrier layer may prevent conductive ions in the second filler layer from diffusing outside the hole.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspect, the spacer layer and the adhesion layer are made of the same material.
For example, the adhesive layer may be at least one of Ti, tiN, ta and TaN. When at least one of Ti, tiN, ta and TaN is adopted as the adhesion layer, the adhesion between the second filling layer and the hole wall surface is good, and conductive ions in the second filling layer can be prevented from diffusing to the outside of the hole, namely, the two functions are realized by one layer structure, so that the filling amount of the second filling layer can be increased, and the resistance of the whole film perforation is reduced.
As another example, the spacer layer may be at least one of Ti, tiN, ta and TaN.
In a possible implementation manner of the first aspect, the second aspect or any one of the third aspect, the aspect ratio of the hole is greater than or equal to 10:1. Of course, the aperture may also be a low aspect ratio structure.
In a fourth aspect, the present application further provides an electronic device, including a circuit board and an electronic device according to any implementation manner of the first aspect, where the electronic device is disposed on the circuit board, and the circuit board is electrically connected to the electronic device; alternatively, the electronic device comprises a circuit board and a chip as described above in the second aspect or any implementation manner of the third aspect, the chip is disposed on the circuit board, and the circuit board is electrically connected with the electronic device.
The electronic device provided by the embodiment of the application comprises the electronic device or the chip, so that the electronic device provided by the embodiment of the application and the electronic device or the chip of the technical scheme can solve the same technical problems and achieve the same expected effect.
In a fifth aspect, the present application further provides a method for forming a film perforation, where the method for forming a film perforation includes: opening holes in the film layer; sequentially forming a first filling layer, a spacing layer and a second filling layer in the hole along the axial direction of the hole, and forming an adhesion layer at the position where the side wall surfaces of the hole of the second filling layer are contacted;
wherein the first filling layer, the spacer layer and the second filling layer are all made of conductive materials, the spacer layer is made of different materials from the first filling layer, and the spacer layer is made of different materials from the second filling layer.
In the method for forming the film perforation according to the embodiment of the application, the film perforation with the electric conduction function is formed by filling the holes of the first filling layer, the spacer layer, the second filling layer and the adhesive layer, and in the film perforation, the adhesive layer is arranged at the position close to the hole opening, so that even if a gap is formed between the first filling layer and the side wall surface of the hole, the grinding liquid is not immersed into the first filling layer in the subsequent chemical mechanical grinding.
In a possible implementation manner of the fifth aspect, when forming the first filling layer, the method includes: a selective growth process is used to stack the first conductive material along the axial direction of the hole to produce a first fill layer.
That is, a selective growth process is used to grow a conductive material along the axial direction of the hole to form a first filling layer, so that voids are not formed in the formed first filling layer.
In a possible implementation manner of the fifth aspect, when forming the first filling layer, the method includes: and filling the first conductive material in the hole until the height dimension of the filled first conductive material along the axial direction of the hole is larger than or equal to the height dimension of the unfilled part of the hole, and stopping filling the first conductive material to form a first filling layer.
That is, the height dimension of the first filling layer formed along the axial direction of the hole is greater than or equal to the height dimension of the second filling layer formed along the axial direction of the hole.
In a possible implementation manner of the fifth aspect, a forming process of the first filling layer is the same as a forming process of the second filling layer. For example, a selectively grown CVD process or a selectively grown ALD process may be employed.
In a possible implementation manner of the fifth aspect, the adhesive layer is formed simultaneously with the formation of the spacer layer, and a material of the adhesive layer is the same as a material of the spacer layer. For example, a deposition process is used to form the spacer layer and the adhesion layer simultaneously.
In a possible implementation manner of the fifth aspect, after forming the second filling layer, the forming method further includes: and flattening the surface of the second filling layer far away from the first filling layer by adopting a chemical mechanical polishing process.
Since the second filler layer is formed with an adhesive layer between the second filler layer and the sidewall surface of the hole, the polishing liquid is not perforated by the chemical mechanical polishing in this step.
FIG. 1 is a schematic view of a prior art film perforation structure;
FIG. 2 is a schematic diagram of the structure of FIG. 1 when one of the steps is performed to make the structure;
FIG. 3 is an exploded view of an electronic device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a chip package structure in an electronic device according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing the detailed structure of the chip in FIG. 4;
fig. 6 is a schematic structural diagram of another chip package structure in an electronic device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of another chip in an electronic device according to an embodiment of the present application;
FIG. 8 is a cross-sectional view of the structure of FIGS. 4 and 5 after each step has been completed;
FIG. 9 is a cross-sectional view of the structure of FIG. 7 after each step of fabrication;
FIG. 10 is a process flow diagram of a method for forming a film perforation according to an embodiment of the present application;
FIG. 11 is a cross-sectional view of the process flow of FIG. 10 after each step is completed;
FIG. 12 is a cross-sectional view of the first filler layer after each step is completed;
FIG. 13 is a schematic view illustrating a structure of a film perforation according to an embodiment of the present application;
fig. 14 is a schematic structural diagram of a chip in an electronic device according to an embodiment of the present application;
fig. 15 is a schematic structural diagram of another chip in an electronic device according to an embodiment of the present application.
Reference numerals:
11-a middle frame; 110-a carrier plate; 111-frames; 12-a rear shell; 13-a display screen; 01-PCB; 02-chip package structure; 021-packaging the substrate; 022-chip; 023-electrical connection structure; 0221-a first chip; 0222-a second chip; 024-an adapter plate; 025-RDL; 026-a substrate;
1-a substrate; 2-an active layer; 21-an electronic component; 22-metal line layers; 3-perforation of the film layer; a 4-transistor; 41-a first pole; 42-second pole; 43-gate layer; 44-a semiconductor layer; 45-gate insulating layer; 5-a dielectric layer; 6-signal lines; 7-a contact layer;
100-film layers; 101-a first filling layer; 1011-a first film layer; 1012-a second film layer; 102-a second filling layer; 103-spacer layer; 104-an adhesion layer; 105-well; 106-void.
The embodiment of the application provides electronic equipment. The electronic device may include a mobile phone (mobile phone), a tablet (pad), an intelligent wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) device, an augmented reality (augmented reality, AR), a home appliance, an automobile, an artificial intelligence device, a server, a data center, etc. The embodiment of the application does not limit the specific form of the electronic device.
In the above electronic device, for example, as shown in fig. 3, the electronic device may include a middle frame 11, a rear case 12, and a display 13. The middle frame 11 comprises a bearing plate 110 for bearing a display screen 13, and a frame 111 surrounding the bearing plate 110 for a circle, wherein a circuit board, such as a printed circuit board 01 (printed circuit board, PCB), is arranged on the bearing plate 110, a chip packaging structure 02 is borne on the PCB01, and the chip packaging structure 02 is electrically connected with the PCB01 to realize the intercommunication of signals between the chip packaging structure 02 and the PCB01, and the rear shell 12 is connected with the middle frame 11, so that the influence of external water vapor and dust on the performance of the structure in the electronic equipment can be prevented.
Fig. 4 shows a schematic diagram of a chip package structure 02, where the chip package structure 02 includes a package substrate 021 and a chip 022 integrated on the package substrate 021, and the chip 022 is disposed on the package substrate 021 by an electrical connection structure 023, for example, the chip 022 may be integrated on the package substrate 021 by a controllably collapsed chip connection pad (controlled collapse chip connection, C4), or may be integrated on the package substrate 021 by a micro bump (uBump).
Fig. 5 is a partial detailed structure diagram of the chip 022 in fig. 4, the chip 022 may include a substrate 1 and an active layer 2, the active layer 2 is disposed on the substrate 1, the active layer 2 is a circuit structure for forming the chip 022, as in fig. 5, the active layer 2 includes not only electronic components 21 such as transistors, diodes, resistors, capacitors, inductors, etc. fabricated on the substrate 1, but also a plurality of metal line layers 22 disposed on the substrate 1, and the plurality of metal line layers 22 are used for electrically connecting a plurality of electronic components 21 together to form the circuit structure.
In some alternative embodiments, the chip 022 may further include a re-wiring layer (redistribution layer, RDL), which may be formed on the surface of these multilayer metal wiring layers 22 remote from the substrate 1.
With continued reference to fig. 4 and 5, since the substrate 1 of the chip 022 is disposed close to the package substrate 021, in order to achieve the interconnection between the chip 022 and the circuit layer on the package substrate 021, for example, it is necessary to electrically connect the RDL located on the active layer 2 with the package substrate 021, or it is necessary to electrically connect a certain metal circuit layer in the active layer 2 with the package substrate 021, and in connection with fig. 5, it is necessary to form a film layer perforation 3 in the substrate 1, the film layer perforation 3 penetrating through the substrate 1, and at least a part of the active layer 2. For example, when the film perforation 3 needs to be electrically connected to an RDL located on the active layer 2, the film perforation 3 needs to pass through the active layer 2 to the RDL, and for example, when the film perforation 3 needs to be electrically connected to a metal line layer located in the active layer 2, the film perforation 3 needs to pass through a portion of the active layer 2.
The film perforation 3 belongs to an electrical conduction structure, wherein one end of the film perforation 3 is electrically connected with a certain metal circuit layer or RDL of the active layer 6, the other end of the film perforation 3 is electrically connected with an electrical connection structure 023, and the electrical connection structure 023 is electrically connected with the package substrate 021. Thus, signal interconnection of the chip 022 and the package substrate 021 can be achieved through the film layer perforation 3 and the electric connection structure 023.
In some alternative embodiments, when the chip 022 includes a plurality of chips 022 and these chips 022 are stacked in three dimensions, for example, RDL is disposed between two chips stacked, and interconnection between the chips is achieved by a structure including RDL, as illustrated in fig. 5, RDL is disposed on a side of the substrate 1 away from the active layer 2, so that an end of the film perforation 3 away from the active layer 2 is electrically connected with RDL on a side of the substrate 1 away from the active layer 2.
In the structure shown in fig. 5, when the material of the substrate 1 is silicon, the film via 3 may be referred to as a through-silicon via (through silicon via, TSV), and in addition, the substrate 1 may be a gallium arsenide (GaAs) substrate, a gallium arsenic phosphate (GaAsP) substrate, or the like.
Fig. 6 shows a schematic diagram of another chip package structure 02, where the chip package structure 02 includes a first chip 0221 and a second chip 0222, and the first chip 0221 and the second chip 0222 are respectively disposed on an Interposer (Interposer) 024 by an inverse package mounting process, and the Interposer 021 is disposed on a package substrate 021.
In order to realize interconnection between the chips or interconnection between each of the chips and the package substrate 021, the interposer 024 includes a base 026, an RDL025 integrated on the base 026, and a side of the interposer 024 having the RDL025 faces the first chip 0221 and the second chip 0222, and the first chip 0221 and the second chip 0222 are electrically connected to the RDL025 respectively, and a film perforation 3 is penetrated in the base 026, and the film perforation 3 is also an electrical conduction structure. One end of the film perforation 3 is electrically connected with the RDL025, and the other end of the film perforation 3 is electrically connected with the package substrate 021. In this way, the first chip 0221 and the second chip 0222 can be in signal communication with the packaging substrate 021 through the adapter plate 024.
In some alternative embodiments, the material of the interposer 024 may be selected to be silicon, such that the interposer 024 may be referred to as a silicon interposer, and the film via 3 may be referred to as a TSV structure.
Fig. 7 shows a schematic diagram of another chip 022, where the chip 022 includes a substrate 1, and electronic components such as a transistor, a resistor, a capacitor, and the like are formed on the substrate 1, and fig. 7 is an example of a transistor 4, and the transistor 4 may be a thin film transistor (thin film transistor, TFT), a fin field-efffect transistor (FinFET), or a transistor with other structures. As shown in fig. 7, a structure of a transistor is also provided, the transistor 4 comprising a first pole 41, a second pole 42, a gate 43, a semiconductor layer 44 and a gate insulating layer 45, wherein the first pole 41, the second pole 42 and the gate insulating layer 45 are arranged on the semiconductor layer 44, the semiconductor layer 44 is arranged on the substrate 1, the gate 43 is arranged on the gate insulating layer 45, the gate insulating layer 45 is used for isolating the gate 43 and the semiconductor layer 44, and the gate insulating layer 45 may also be referred to as a gate dielectric layer or a gate oxide dielectric layer. The first pole 41 here is one of a source and a drain, and the second pole 42 is the other of the source and the drain.
In fig. 7, for example, when the transistor 4 is used to form a memory cell structure in a memory, the second electrode 42 needs to be electrically connected to a signal line 6 formed in the dielectric layer 5, where the signal line 6 may be a Bit Line (BL). Then, it is necessary to form the film perforations 3 in the dielectric layer 5, where the film perforations 3 are also an electrically conductive structure. One end of the film perforation 3 is electrically connected with the second pole 42, and the other end of the film perforation 3 is electrically connected with the signal line 6. In this way, the second pole 42 can be in signal communication with the signal line 6 via the film perforation 3.
With continued reference to fig. 7, the film perforation 3 penetrates the dielectric layer 5, and the film perforation 10 may be referred to as a dielectric perforation (through dielectric via, TDV), or such a film perforation may be referred to as a contact structure.
The above-mentioned figures 4, 5, 6 and 7 only show a few exemplary structures with film perforations 3, but in addition to that, some chips have film perforations for electrical conduction, and these chip structures are not exhaustive.
Fig. 8 shows a corresponding structure diagram after each step of preparing the chip package structure shown in fig. 4.
As in (a) of fig. 8, an active layer 2 is formed on a substrate 1, the active layer 2 including not only electronic components 21 fabricated on the substrate 1 but also a plurality of metal wiring layers 22 on the substrate 1, the plurality of metal wiring layers 22 being for electrically connecting a plurality of electronic components 21 together to form a circuit structure.
As shown in fig. 8 (b), the structure of fig. 8 (a) is inverted, and the hole 105 is opened, and the hole 105 passes through the substrate 1 to a certain metal line layer in the active layer 2.
As shown in fig. 8 (c), the conductive material is filled in the opened hole 105 to form a film perforation 3 structure, thereby manufacturing a chip 022 having the film perforation 3.
As in (d) of fig. 8, the chip 022 having the film perforation 3 is integrated on the package substrate 021 through the electrical connection structure 023, for example, integrated on the package substrate 021 through uBump.
Fig. 9 shows a corresponding block diagram after each step in the preparation of the chip shown in fig. 7.
As in (a) of fig. 9, a preparation transistor 4 is formed on a substrate 1, and a dielectric layer 5 is formed on the substrate 1 having the transistor 4.
As shown in fig. 9 (b), a hole 105 is formed in the dielectric layer 5, and the hole 105 penetrates through the transistor 4, for example, the hole 105 penetrates through the second pole 42 of the transistor 4 as shown in fig. 9 (b), and the second pole 42 is one of a source and a drain.
As in (c) of fig. 9, the opened hole 105 is filled with a conductive material to form a film perforation 3 structure.
As in (d) of fig. 9, the signal line 6 formed of a metal layer is formed on the side of the film perforation 3 remote from the second pole 42 so that the signal line 6 is electrically connected to the second pole 42 through the film perforation 3.
Whether the chip containing the TSV film perforation shown in fig. 8 is prepared, or the chip containing the TDV or contact film perforation shown in fig. 9 is prepared, with the continuous miniaturization of the process node, the aspect ratio (aspect ratio) of the film perforation is continuously increasing, for example, the radial dimension is now tens of nanometers, and the depth dimension is 1 micrometer. As such, the process of forming the film via presents increasing challenges, such as not degrading the conductive performance due to the high aspect ratio, or even degrading the performance due to the high aspect ratio, introducing more impurities, and even causing the film via to fail.
The application provides a method for forming a film perforation, which not only can prepare a film perforation with high depth-to-width ratio, for example, the depth-to-width ratio is larger than or equal to 10:1, but also is applicable to preparing a film perforation with low depth-to-width ratio, for example, the depth-to-width ratio is smaller than 10:1, and the film perforation prepared by the method does not have gaps and does not introduce impurities, for example, grinding liquid in a chemical mechanical grinding process and the like.
The method of forming the film perforations is explained in detail below with reference to the drawings.
The method of forming the perforations in the film is described in detail with reference to fig. 10 and 11. Fig. 10 is a process flow chart of the film perforation forming method, and fig. 11 is a cross-sectional view of the film perforation process after each step is completed.
Referring to step S1 of fig. 10 and the structure of (a) of fig. 11, fig. 11 (a) is the structure after step S1 is completed, and step S1 includes: an aperture 105 is formed in the film 100.
The film 100 may be a substrate, or may be a dielectric layer, and when the film is a substrate and is made of a silicon material, the film perforation is formed as a TSV. When the film layer is a dielectric layer, for example, one or a combination of at least two of silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicon dioxide, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, or boron-phosphorus-doped silicon dioxide may be selected, and the formed film layer is perforated to have a TDV or contact structure.
As shown in fig. 11 (a), a first wiring layer 031 is shown on one side of the hole 105, where the film layer is perforated to electrically connect the first wiring layer 031 and a second wiring layer (not shown), for example, the first wiring layer 031 may be the second pole 42 in the transistor 4 shown in fig. 7, and when the hole 105 is opened, the hole 105 needs to be perforated through the dielectric layer to the second pole 42 so as to expose the second pole 42.
In addition, in some other alternative embodiments, as shown in fig. 7, a contact layer 7 electrically connected to the second pole 42 may be formed on the surface of the second pole 42, where the contact layer 7 is used to reduce the contact resistance between the film through hole 3 and the second pole 42, and the contact layer 7 may be made of Silicide (silicon), and further, when the hole 105 is opened, the hole 105 penetrates through to the contact layer 7, so that the contact layer 7 is exposed.
In fig. 11 (a), two holes 105 are shown as an example, and in some cases, more holes may need to be formed, for example, a memory may include a plurality of memory cells, and one hole for each second pole (source or drain) of each memory cell needs to be electrically connected to the BL, and thus a plurality of holes need to be formed. These multiple holes 105 may be formed simultaneously for simplicity of the process.
In the case of opening the hole 105, a dry etching process may be selected, and then, in the case of dry etching, the opening process steps may be: the top topography of the holes is formed at the top of the film layer and an etching gas with a high carbon content, such as octafluorocyclobutane (C) 4 F 8 ) The Polymer thus formed will deposit on the hole sidewall, protecting the hole diameter that has been etched from being enlarged, and the excess Polymer will be expelled out of the hole, continuing to etch the bottom topography, eventually forming a hole, typically in a tapered configuration.
After the perforation is completed, the perforation is further required to be Pre-cleaned (Pre-clean), namely, the inner wall surface of the perforation is chemically treated, so that the influence on the conductivity of the formed perforation of the film layer due to the residue is avoided.
Referring to step S2 of fig. 10, a first filling layer, a spacer layer and a second filling layer are sequentially formed in the hole in the axial direction of the hole, and an adhesive layer is formed at a position where the sidewall surfaces of the hole of the second filling layer are in contact, the first filling layer, the spacer layer and the second filling layer are each made of a conductive material, and the spacer layer and the first filling layer are different in material, and the spacer layer and the second filling layer are different in material.
Specific processes of forming the first filling layer, the second filling layer, the spacer layer and the adhesive layer are described in detail below with reference to fig. 11 (b) to (e), respectively.
As shown in fig. 11 (b), after the opening shown in fig. 11 (a) is completed, a conductive material is filled in the hole 105 to form a first filling layer 101, and the first filling layer 101 does not fill the hole 105, so that a receiving space needs to be reserved for a subsequent second filling layer, spacer layer and adhesive layer.
In some alternative embodiments, the process means shown in fig. 12 may be selected to form the first filling layer 101. Fig. 12 shows a structural diagram after completion of each step in forming the first filling layer 101.
As in fig. 12 (a), a non-selective growth (no selective deposition) process is used to form a first film 1011 on both the bottom and side surfaces of the hole.
As in (b) of fig. 12, a second film layer 1012 is formed on the first film layer 1011 on the bottom surface and on the first film layer 1011 on the side surface.
According to the process shown in fig. 12 (b), a third film layer, a fourth film layer, or even more film layers are sequentially formed on the second film layer 1012, and finally the first filling layer 101 composed of a plurality of film layers shown in fig. 12 (m) is formed.
When the film perforation is formed by the non-selective growth process shown in fig. 12, an early necking phenomenon occurs, where the early necking can be explained as a phenomenon that when the hole is not filled with the conductive material, the opening of the hole is blocked by the conductive material, and the first filling layer 101 shown in fig. 12 (m) has a void (sea) 106. The disadvantage of having voids 106 in the first fill layer 101 is that the electrical resistance of the film perforations may be increased, even causing open circuits, which may not meet the electrical conductivity requirements for the film perforations.
In other alternative embodiments, a selective growth (selective deposition) process may be used to stack conductive material along the axial direction of the hole 105, e.g., a selective growth may be used to obtain the first fill layer 101 using chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), or the like.
For example, when CVD selective growth is used, the conductive material is stacked in the axial direction of the hole 105, and thus, the void 106 shown in fig. 12 does not occur, so that the process of stacking the conductive material in the axial direction can avoid the occurrence of voids, and thus, the conductive performance of the finally formed film perforation can be improved. Particularly for high aspect ratio holes, early healing occurs more easily when the non-selective growth process shown in fig. 12 is used, but voids do not occur easily when the selective growth process stacked in the axial direction is used even for high aspect ratio holes.
In some alternative embodiments, the first filling layer 101 may be formed by selectively growing tungsten (Selective W Deposition), selectively growing cobalt (Selective Co Deposition), or the like.
The above-described selective growth of tungsten or selective growth of cobalt can be understood as follows: during the growth of tungsten or cobalt, tungsten or cobalt will grow gradually only on the conductive layer made of conductive material and not on the non-conductive material of the sidewall surface of the hole, in a manner which may be referred to as a selective growth process, i.e. only in specific areas, not fully epitaxial non-selective growth.
Continuing with the explanation of the film perforation formation method of the present application with reference to fig. 11, after the filling of the first filling layer 101 shown in fig. 11 (b) is completed, fig. 11 (c) may be performed, that is, the spacer layer 103 is formed on the surface of the first filling layer 101, and the adhesion layer 104 is formed on the sidewall surface of the unfilled portion of the hole 105.
Since the selective growth process of stacking the first filling layer along the axial direction of the hole is used to prevent formation of voids in the first filling layer 101 when forming the first filling layer 101, so that the adhesion between the first filling layer 101 and the sidewall surface of the hole 105 is poor, and further, there is a possibility that a gap may be generated between the first filling layer 101 and the sidewall surface of the hole 105, by forming the adhesion layer 104 at a position contacting the hole sidewall surface at the remaining portion of the hole as shown in fig. 11 (c), the path of the fluid medium (e.g., polishing liquid) which can be immersed in the first filling layer 101 is blocked, and thus, the subsequent process is prevented from immersing the corrosive polishing liquid in the gap between the first filling layer 101 and the hole 105 when performing the chemical mechanical polishing (chemical mechanical polishing, CMP) process.
Continuing with the explanation of the film perforation forming method of the present application with reference to fig. 11, with reference to fig. 11 (d), the remaining space of the hole 105 is filled with a conductive material to form the second filling layer 102.
The second filling layer 102 may be formed by selective growth or non-selective growth, for example, by CVD, physical vapor deposition (physical vapor deposition, PVD), ALD, or electroplating.
As can be seen from fig. 11 (c), the spacer layer 103 isolates the first filling layer 101 from the second filling layer 102, and in order to allow electrons passing through the first filling layer 101 to pass through the spacer layer 103 and enter the second filling layer 102 to conduct the wiring layers on the upper and lower sides of the film perforation, the spacer layer 103 is made of a conductive material, such as zirconium nitride (ZrN), manganese oxide (MnO) x ) One or a combination of at least two of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) may also be selected, as may tungsten cobalt alloy (CoW), molybdenum cobalt alloy (CoMo), cobalt ruthenium alloy (RuCo), tungsten titanium alloy (TiW), etc. Because Ti, tiN, ta or TaN is used as the spacer layer, ti, tiN, ta, taN these materials have a certain viscosity, and can also ensure the bonding strength between the second filling layer 102 and the first filling layer 101, prevent the formed film perforation from layering between the first filling layer 101 and the second filling layer 102 in use, so as to generate open phenomenon, and the layer structure with both bonding and blocking effects can be called as adhesion diffusion barrier (liner layer).
The material of the adhesion layer 104 of the present application may be made of a conductive material, for example, a metal may be selected, and when aluminum (Al) is selected as the material of the second filling layer 102, ti or Ta may be selected as the material of the adhesion layer 104 because Al and Ti or Al and Ta have good adhesion properties; as another example, when copper (Cu) is selected as the material of the second filling layer 102, ta may be selected as the material of the adhesion layer 104 because of good adhesion between Cu and Ta, and in addition to this, metals such as cobalt (Co), ruthenium (Ru), molybdenum (Mo), iridium (Ir), lead (Pd), rhodium (Rh) and the like may be selected as the adhesion layer 104.
When Ti, tiN, ta or TaN is used as the adhesive layer, not only the adhesive strength between the second filling layer 102 and the hole is ensured, but also the conductive ions in the second filling layer 102 can be prevented from diffusing to the outside of the hole to affect the conductive performance.
In addition, when Ti, tiN, ta or TaN is adopted, on the basis of being compatible with blocking conductive ion diffusion and playing a role in bonding, the adhesion layer can be made thin, so that more accommodating spaces can be reserved for the second filling layer, the filling amount of the second filling layer is improved, the perforated resistance of the film layer is further reduced, and the signal transmission efficiency of the perforation of the film layer is improved.
If the material of the adhesion layer 104 is the same as that of the spacer layer 103, a deposition process such as PVD, ALD, etc. may be used, so that the adhesion layer 104 and the spacer layer 103 may be formed together to simplify the manufacturing process of the film perforation. Of course, different processes may be used.
The material of the second filling layer 102 may be one or a combination of at least two of metals such as tungsten (W), cobalt (Co), aluminum (Al), and copper (Cu).
In this way, the second filling layer 102 may be made of the same conductive material as the first filling layer 101 or may be made of a different conductive material.
In order to reduce the resistance value of the entire film perforation, the second filling layer 102 may be formed of a material having a resistivity smaller than or equal to that of the material of the first filling layer 101. For example, when tungsten is selected for the first fill layer 101, copper may be selected for the second fill layer 102.
After forming the second filling layer 102 shown in fig. 11 (d), as in fig. 11 (e), it is also necessary to planarize the second filling layer 102, for example, by polishing the conductive material on the surface of the film layer 100 by a CMP process, and by planarizing the surface of the second filling layer 102.
In addition to forming the adhesion layer 104 on the inner wall surface of the hole and forming the spacer layer 103 on the surface of the first filling layer 101 as shown in fig. 11 (d), a cover layer is formed on the surface of the film layer 100, for example, when the adhesion layer 104 and the spacer layer 103 are made of the same material, the cover layer is made of the same material as the adhesion layer and the spacer layer, and further, when the planarization treatment shown in fig. 11 (e) is performed, the cover layer on the surface of the film layer 100 needs to be removed to obtain the structure shown in fig. 11 (e).
Since the adhesive layer 104 has been formed in the previous process, even if there is a gap between the first filling layer 101 and the wall surface of the hole after the first filling layer 101 is completed, the slurry is prevented from being immersed in the gap by the adhesive layer 104.
In addition, when the planarization treatment is performed by adopting the CMP process, common and commonly used grinding liquid can be adopted, and some special grinding liquid is not required to be adopted. In addition, compared with the special grinding fluid, the common grinding fluid is convenient to control in terms of process parameters, and further the process difficulty is reduced.
After the planarization process of (e) of fig. 11 is completed, a second wiring layer may be formed on the second filling layer again to electrically conduct the first wiring layer 031 and the second wiring layer through the film layer via hole.
Fig. 13 shows a structure of a film perforation made by the above method, in which film perforation 3, the height dimension h1 of the first filling layer 101 in the axial direction of the hole is larger than the height dimension h2 of the second filling layer 102 in the axial direction of the hole. For example, the ratio of the height dimension h1 of the first filling layer 101 to the height dimension h of the hole may be 50% to 90%. This is given by way of example only, and other ratios may, of course, be selected.
The reason why the height dimension h1 of the first filling layer 101 is designed to be higher than the height dimension h2 of the second filling layer 102 is that: since the selective growth process is adopted in forming the first filling layer 101, the occurrence of void phenomenon can be prevented, the electrical conductivity of the whole film perforation is ensured, and the second filling layer 102, the spacer layer 103 and the adhesive layer 104 formed on the first filling layer 101 can be used as a cap structure for protecting the first filling layer 101.
Therefore, the method for forming the film perforation provided by the embodiment of the application can be applied to both high-aspect-ratio structures and low-aspect-ratio structures, and the resistance value of the film perforation cannot be reduced due to the high-aspect-ratio structures.
In the film perforation 3 shown in fig. 13, the thickness of the adhesion layer 104 and the spacer layer 103 is substantially 0.5nm to 10nm, and may be between 0.5nm and 5nm, so that a larger space is not occupied, and more accommodation space is reserved for the first filling layer 101 and the second filling layer 102 as conductive structures, so as to prevent the phenomenon of increasing the perforation resistance of the film because the adhesion layer 104 and the spacer layer 103 occupy a larger space. The 0.5nm to 10nm, 0.5nm to 5nm values are only an exemplary range of values, although other values may be selected.
Fig. 14 shows a structure of a chip, in which the film perforation 3 of the chip 022 is manufactured by the method shown in fig. 10 and 11, and in the structure shown in fig. 14, the first filling layer 101 is close to the active layer 2 of the chip 022, and the second filling layer 102 is close to the metal layer, such as close to the electrical connection structure 023. It can also be understood that, in the preparation of the chip structure, after the film perforation 3 including the first filling layer 101, the second filling layer 102, the spacer layer 103 and the adhesion layer 104 is completed, when the CMP process is used to planarize the second filling layer 102 far from the active layer 2, the polishing liquid will not enter the film perforation under the blocking effect of the adhesion layer 104, so as to ensure the performance of the chip.
Fig. 15 shows a structure of a chip, in which the film perforation of the chip 022 is also manufactured by the method shown in fig. 10 and 11, and in the structure shown in fig. 15, the first filling layer 101 is close to the transistor 4, and the second filling layer 102 is close to the signal line 6. It will also be understood that in the preparation of the chip structure, after the film perforation 3 including the first filling layer 101, the second filling layer 102, the spacer layer 103 and the adhesion layer 104 is completed, when the CMP process is used to planarize the second filling layer 102 far from the transistor 4, the polishing liquid will not enter the film perforation under the barrier action of the adhesion layer 104, so as to ensure the performance of the chip.
In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (20)
- A chip, comprising:a substrate;an electronic component disposed on the substrate;a wiring layer formed on a side of the electronic component remote from the substrate;a dielectric layer, between the electronic component and the wiring layer being isolated by the dielectric layer;the film layer perforation comprises a hole penetrating through the dielectric layer, a first filling layer, a spacing layer and a second filling layer are sequentially stacked in the hole along the axial direction of the hole, and an adhesion layer is arranged at the position of the second filling layer, which is in contact with the side wall surface of the hole;wherein the first filling layer, the second filling layer and the spacer layer are all made of conductive materials, the material of the spacer layer is different from the material of the first filling layer, and the material of the spacer layer is different from the material of the second filling layer;the first filling layer is arranged close to the electronic component, and the second filling layer is arranged close to the wiring layer so as to electrically connect the electronic component and the wiring layer.
- The chip of claim 1, wherein a height dimension of the first filler layer along an axial direction of the hole is greater than or equal to a height dimension of the second filler layer along the axial direction of the hole.
- The chip of claim 1 or 2, wherein the resistivity of the conductive material of the second filler layer is less than or equal to the resistivity of the conductive material of the first filler layer.
- A chip according to any one of claims 1 to 3, wherein the material of the adhesion layer is the same as the material of the spacer layer.
- The chip of any one of claims 1 to 4, wherein the material of the adhesion layer is one or a combination of at least two of titanium, titanium nitride, tantalum nitride.
- The chip of any one of claims 1 to 5, wherein the material of the spacer layer is one or a combination of at least two of titanium, titanium nitride, tantalum nitride.
- The chip of any one of claims 1 to 6, wherein the aspect ratio of the holes is greater than or equal to 10:1.
- A chip, comprising:a substrate;an active layer disposed on the substrate;a wiring layer formed on a side of the substrate away from the active layer;the film layer perforation comprises a hole penetrating through the substrate and at least one part of the active layer, a first filling layer, a spacing layer and a second filling layer are sequentially stacked in the hole along the axial direction of the hole, and an adhesion layer is arranged at the position, contacted with the side wall surface of the hole, of the second filling layer;Wherein the first filling layer, the second filling layer and the spacer layer are all made of conductive materials, the material of the spacer layer is different from the material of the first filling layer, and the material of the spacer layer is different from the material of the second filling layer;the first filling layer is arranged close to the active layer, and the second filling layer is arranged close to the wiring layer so as to electrically connect the active layer and the wiring layer.
- The chip of claim 8, wherein a height dimension of the first filler layer along an axial direction of the hole is greater than or equal to a height dimension of the second filler layer along the axial direction of the hole.
- The chip of claim 8 or 9, wherein the resistivity of the conductive material of the second filler layer is less than or equal to the resistivity of the conductive material of the first filler layer.
- The chip according to any one of claims 8 to 10, wherein the material of the adhesion layer is the same as the material of the spacer layer.
- The chip of any one of claims 8 to 11, wherein the material of the adhesion layer is one or a combination of at least two of titanium, titanium nitride, tantalum nitride.
- The chip of any one of claims 8 to 12, wherein the material of the spacer layer is one or a combination of at least two of titanium, titanium nitride, tantalum nitride.
- The chip of any one of claims 8 to 13, wherein the aspect ratio of the holes is greater than or equal to 10:1.
- An electronic device, comprising:a circuit board;a chip as claimed in any one of claims 1 to 14, which is disposed on and electrically connected to the circuit board.
- A method of forming a perforation in a film, comprising:opening holes in the film layer;sequentially forming a first filling layer, a spacer layer and a second filling layer in the hole along the axial direction of the hole, and forming an adhesion layer at a position where the side wall surfaces of the hole of the second filling layer are contacted;wherein the first filling layer, the spacer layer and the second filling layer are all made of conductive materials, the spacer layer is made of a material different from that of the first filling layer, and the spacer layer is made of a material different from that of the second filling layer.
- The method of forming a film perforation according to claim 16, wherein forming a first filler layer comprises:A selective growth process is used to stack a first conductive material along the axial direction of the hole to produce the first fill layer.
- The method of forming a film perforation according to claim 16 or 17, wherein the forming a first filler layer comprises:and filling a first conductive material in the hole until the height dimension of the filled first conductive material along the axial direction of the hole is larger than or equal to the height dimension of the unfilled part of the hole, and stopping filling the first conductive material to form the first filling layer.
- The method of any one of claims 16 to 18, wherein the spacer layer and the adhesive layer are formed simultaneously, and the adhesive layer is the same material as the spacer layer.
- The method of forming a film perforation according to any one of claims 16 to 19, wherein after the forming of the second filler layer, the method further comprises:and flattening the surface of the second filling layer, which is far away from the first filling layer, by adopting a chemical grinding process.
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| PCT/CN2021/083422 WO2022198674A1 (en) | 2021-03-26 | 2021-03-26 | Chip, electronic device, and forming method for film perforation |
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| KR100946024B1 (en) * | 2007-09-06 | 2010-03-09 | 주식회사 하이닉스반도체 | Metal wiring of a semiconductor device and method of forming thereof |
| TW201145493A (en) * | 2010-06-01 | 2011-12-16 | Chipmos Technologies Inc | Silicon wafer structure and multi-chip stack structure |
| TWI500134B (en) * | 2010-11-26 | 2015-09-11 | 財團法人工業技術研究院 | Tsv substrate structure and the stacked assembly thereof |
| US20140264869A1 (en) * | 2013-03-15 | 2014-09-18 | Chao-Yuan Huang | Semiconductor Device |
| US9865523B2 (en) * | 2014-01-17 | 2018-01-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Robust through-silicon-via structure |
| US10396012B2 (en) * | 2016-05-27 | 2019-08-27 | International Business Machines Corporation | Advanced through substrate via metallization in three dimensional semiconductor integration |
| US9824970B1 (en) * | 2016-06-27 | 2017-11-21 | Globalfoundries Inc. | Methods that use at least a dual damascene process and, optionally, a single damascene process to form interconnects with hybrid metallization and the resulting structures |
| US11004794B2 (en) * | 2018-06-27 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof |
| KR102060360B1 (en) * | 2018-07-20 | 2019-12-30 | 한양대학교 에리카산학협력단 | Method for forming bumps on a tsv substrate |
| CN111293079B (en) * | 2020-03-17 | 2023-06-16 | 浙江大学 | Manufacturing method of ultra-thick adapter plate |
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