CN110729231A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN110729231A CN110729231A CN201810784633.4A CN201810784633A CN110729231A CN 110729231 A CN110729231 A CN 110729231A CN 201810784633 A CN201810784633 A CN 201810784633A CN 110729231 A CN110729231 A CN 110729231A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The invention provides a manufacturing method of a semiconductor device and the semiconductor device, wherein a back etching groove is formed by removing a part of the first conductive structure with partial thickness through back etching, so that the thickness of a covering layer between the first conductive structure and an upper second conductive structure is increased (namely, the distance between the first conductive structure and the second conductive structure which are separated by the covering layer is increased), further parasitic capacitance is reduced, meanwhile, the vertex angle of the back etching groove is rounded, so that the adhesiveness of the covering layer and the thickness uniformity on the side wall and the bottom wall of the back etching groove are increased, further, the contact resistance between the first conductive structure and the second conductive structure is reduced, and therefore, RC delay is reduced, and the performance of the device is improved; the semiconductor device comprises an interlayer dielectric layer with a round-cornered opening, a first conductive structure, a covering layer and a second conductive structure, wherein the first conductive structure is filled in the opening, and the top surface of the first conductive structure is lower than that of the interlayer dielectric layer.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
With the rapid development of semiconductor manufacturing technology, in order to achieve faster operation speed, larger data storage capacity and more functions, semiconductor devices (or integrated circuits, semiconductor chips) are developed to higher integration, which increases the density of elements to be formed and at the same time reduces the size and gap between members or elements in the semiconductor devices, which may cause various problems. For example, for any two adjacent conductive structures, when the distance between the conductive structures is reduced, the resulting parasitic capacitance is increased, and the increased parasitic capacitance causes an increase in power consumption and an increase in resistance-capacitance delay (RCdelay), which further affects the performance of the semiconductor device more and more, and therefore, how to reduce the RC delay of the conductive structure becomes one of the hot problems studied by those skilled in the art.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device and the semiconductor device, which can reduce the parasitic capacitance between two adjacent layers of conductive structures, reduce the resistance-capacitance delay and improve the performance of the device.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
forming a first conductive structure in an interlayer dielectric layer, wherein the top surface of the first conductive structure is exposed out of the interlayer dielectric layer;
removing part of the thickness of the first conductive structure by adopting a back etching process to form a back etching groove;
performing round angle on the back etching groove;
forming a covering layer at least covering the surface of the back etching groove;
and forming a second conductive structure on the surface of the covering layer.
Optionally, the step of forming the first conductive structure in the interlayer dielectric layer includes:
providing a semiconductor substrate, and forming an interlayer dielectric layer on the semiconductor substrate;
forming an opening in the interlayer dielectric layer through an etching process;
forming a diffusion barrier layer overlying a surface of the opening;
and filling a conductive metal layer in the opening to form the first conductive structure in the interlayer dielectric layer, wherein the top surface of the first conductive structure is flush with the top surface of the interlayer dielectric layer.
Optionally, the step of filling the opening with the conductive metal layer includes:
depositing a conductive metal layer, wherein the conductive metal layer fills the opening and covers the upper part of the interlayer dielectric layer;
and removing the conductive metal layer above the interlayer dielectric layer by adopting a planarization process so as to fill the conductive metal layer in the opening.
Optionally, before the interlayer dielectric layer is etched to form the opening, a planarization stop layer is further formed on the surface of the interlayer dielectric layer, the deposited conductive metal layer fills the opening and covers the surface of the planarization stop layer, and the conductive metal layer on the surface of the planarization stop layer is removed by using a planarization process, so that the opening is filled with the conductive metal layer.
Optionally, before rounding the etch-back trench, the planarization stop layer is removed.
Optionally, after forming the diffusion barrier layer in the opening and before filling the conductive metal layer in the opening, an adhesion layer and/or a seed layer is further formed on the surface of the diffusion barrier layer.
Optionally, the diffusion barrier layer includes at least one of tantalum, titanium, tantalum nitride, titanium tungsten, tungsten nitride, titanium aluminide, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride, and silicon nitride.
Optionally, after forming the etch-back trench and before rounding the etch-back trench, etching to remove the diffusion barrier layer exposed by the etch-back trench.
Optionally, the diffusion barrier layer exposed by the etch-back groove is etched and removed by using a plasma etching process.
Optionally, the back etching process for removing a part of the thickness of the first conductive structure is a synchronous pulse etching process.
Optionally, the first conductive structure is a metal electrode, a conductive contact plug and/or a metal interconnection line.
Optionally, the first conductive structure is made of at least one metal element selected from copper (Cu), tungsten (W), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), vanadium (V), and chromium (Cr).
Optionally, the step of forming a cover layer at least covering the surface of the etch-back trench includes:
forming a line dielectric layer at least covering the surface of the back etching groove;
and forming a flat layer with a flat top surface on the surfaces of the line dielectric layer and the interlayer dielectric layer.
The present invention also provides a semiconductor device comprising:
an interlayer dielectric layer;
the first conductive structure is formed in the interlayer dielectric layer, and the interlayer dielectric layer forms a circular angle back etching groove on the first conductive structure;
a covering layer, wherein the covering layer at least covers the surface of the back etching groove;
and the second conductive structure is positioned on the surface of the covering layer.
Optionally, the first conductive structure includes a diffusion barrier layer and a conductive metal layer on a surface of the diffusion barrier layer.
Optionally, the cover layer includes a line dielectric layer covering the surface of the etch-back trench and a planarization layer covering the surface of the line dielectric layer and the surface of the interlayer dielectric layer.
Optionally, the first conductive structure and the second conductive structure respectively include at least one of a metal electrode, a conductive contact plug, and a metal interconnection line.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the semiconductor device, the first conductive structure with partial thickness is removed through back etching to form the back etching groove, so that the thickness of the covering layer between the first conductive structure and the second conductive structure above the first conductive structure is increased (namely, the distance between the first conductive structure and the second conductive structure which are separated by the covering layer is increased), further parasitic capacitance is reduced, meanwhile, the vertex angle of the back etching groove is rounded, so that the adhesiveness of the covering layer and the thickness uniformity on the side wall and the bottom wall of the back etching groove are increased, further, the contact resistance between the first conductive structure and the second conductive structure is reduced, and therefore RC delay is reduced, and the performance of the device is improved.
2. The semiconductor device comprises an interlayer dielectric layer, a first conductive structure, a covering layer and a second conductive structure, wherein the first conductive structure, the covering layer and the second conductive structure are formed in the interlayer dielectric layer, the interlayer dielectric layer forms a circular-angle back etching groove on the first conductive structure, the top surface of the first conductive structure is lower than the top surface of the interlayer dielectric layer through the back etching groove, therefore, the thickness of the covering layer between the first conductive structure and the second conductive structure above the first conductive structure can be increased, parasitic capacitance is reduced, meanwhile, the covering layer is formed on the surface of the circular-angle back etching groove, adhesion is increased, the thickness uniformity of the covering layer on the side wall and the bottom wall of the back etching groove is reduced, contact resistance is reduced, RC delay is reduced, and device performance is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor device;
FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 3A to 3E are schematic cross-sectional views of device structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background art, as semiconductor devices are developed to have higher integration density, the element density is increased, that is, as the semiconductor manufacturing technology is rapidly developed, the number of elements included in the semiconductor devices is increased, and in the back-end-of-line (BEOL) of the integrated circuit manufacturing, an interconnection structure is required to be formed to electrically connect the respective independent elements in the semiconductor devices to realize signal transmission between the elements. As shown in fig. 1, a method of fabricating an interconnect structure includes the steps of:
first, a first interlayer dielectric layer 100 and a planarization stop layer 101 are formed on a semiconductor substrate (not shown) including at least one element (not shown), and an opening capable of exposing a top surface of the element or a metal conductive structure (e.g., a conductive plug electrically contacting the element or a lower metal interconnection line electrically connecting the element, etc.) is formed in the interlayer dielectric layer 100;
then, filling the openings with a diffusion barrier layer 102 and a conductive metal layer 103 such as copper in sequence, and removing the excess diffusion barrier layer 102 and the conductive metal layer 103 on the surface of the planarization stop layer 101 by a Chemical Mechanical Polishing (CMP) process, thereby forming a metal interconnection layer;
then, a line dielectric layer 104 and a second interlayer dielectric layer 105 are sequentially formed on the surfaces of the planarization stop layer 101 and the metal interconnection layers (i.e., the diffusion barrier layer 102 and the conductive metal layer 103);
thereafter, another metal interconnect layer is formed, which may include a conductive via structure (not shown) that penetrates through the second interlevel dielectric layer 105 and the line dielectric layer 104 and is in electrical contact with the top surface of the conductive metal layer 103 and the bottom surface of the interconnect line 106, and an interconnect line 106.
In the above-described interconnect structure, as the semiconductor device is further scaled down, the distance D1 between the interconnect line 106 and the conductive metal layer 103 is further decreased, and thus the resulting parasitic capacitance is increased, which results in increased power consumption and increased RC delay, and thus greater and greater influence on the performance of the semiconductor device; in addition, the presence of the planarization stop layer 101 may increase the contact resistance between the conductive metal layer 103 and the further metal interconnect layer, further degrading device performance.
Based on the above, the invention provides a semiconductor device and a manufacturing method thereof, wherein the distance between the first conductive structure and the second conductive structure above the first conductive structure is increased by performing back etching on the first conductive structure, so that the parasitic capacitance between two adjacent layers of conductive structures is reduced, and the back etching groove is further rounded, so that the contact resistance between two adjacent layers of conductive structures is reduced, the resistance-capacitance delay is reduced, and the device performance is improved.
The present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:
s1, forming a first conductive structure in an interlayer dielectric layer, wherein the top surface of the first conductive structure is exposed out of the interlayer dielectric layer;
s2, removing the first conductive structure with partial thickness by adopting a back etching process to form a back etching groove;
s3, performing round angle on the back etching groove;
s4, forming a covering layer at least covering the surface of the etch-back groove;
and S5, forming a second conductive structure on the surface of the covering layer.
Referring to fig. 3A, the specific process of forming the first conductive structure on the interlayer dielectric layer in step S1 includes:
first, a semiconductor substrate (not shown) is provided, on which an interlayer dielectric layer 300 and a planarization stop layer 301 are sequentially formed, wherein the semiconductor substrate as a platform of a subsequent process may be any semiconductor substrate known to those skilled in the art, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a Silicon On Insulator (SOI) or Germanium On Insulator (GOI), etc., and may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), or silicon carbide (SiC), etc., the semiconductor substrate may be a substrate on which a previous process (FEOL) has been completed, the semiconductor substrate may have a plurality of device isolation structures and a plurality of active elements, such as MOS transistors, and passive elements, such as resistors and capacitors, in most cases, these active and passive components need to be externally connected through conductive structures such as conductive plugs, multilayer metal interconnection structures, etc., or electrically connected with other components or control circuits to achieve their respective functions; the interlayer dielectric layer 300 may be formed by chemical vapor deposition, physical vapor deposition, coating, or other processes, the interlayer dielectric layer 300 may cover the surface of the entire semiconductor substrate, that is, the interlayer dielectric layer 300 may cover active elements and passive elements of the semiconductor substrate and have a relatively flat top surface to provide a flat working platform for subsequent processes, the interlayer dielectric layer 300 may specifically be a low-K dielectric layer (dielectric constant K is less than 4 and greater than or equal to 2) or an ultra-low-K dielectric layer (dielectric constant K is less than 2, or may be a stack of a low-K dielectric layer and an ultra-low-K dielectric layer, or may be a stack of a low-K dielectric layer and a silicon oxide layer (silicon oxide may also be used as the low-K dielectric layer and the ultra-low-K dielectric layer), but in this specification, the silicon oxide layer refers to a stack of a conventional insulating material silicon dioxide layer, that is, a non, or a lamination of an ultra-low K dielectric layer and a silicon oxide layer; the planarization stop layer 301 may be formed by at least one of atomic layer deposition, chemical vapor deposition, and physical vapor deposition, and the planarization stop layer 301 may serve as a mask protection layer for the subsequent etching of the interlayer dielectric layer 300, and may serve as a stop point for the CMP process when the subsequent first conductive structure is formed; the material of the planarization stop layer 301 includes silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN, NDC), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), silicon oxide containing carbon, silicon oxynitride, or the like.
Then, sequentially etching the planarization stop layer 301 and the interlayer dielectric layer 301 by a dry etching process to form an opening in the interlayer dielectric layer 301, where the opening may penetrate through the interlayer dielectric layer 300 to expose a top surface of an element in the semiconductor substrate and/or a top surface of a conductive structure (including a conductive plug, a metal interconnection line, and an electrode of a capacitor), or may only penetrate into the interlayer dielectric layer 300 to a certain depth, and the opening is used to form a first conductive structure capable of connecting the element in the semiconductor substrate outwards;
next, an Atomic Layer Deposition (ALD) process may be used to deposit a diffusion barrier layer 302 on the planarization stop layer 301 and the surface of the opening, the material of the diffusion barrier layer 302 is different from that of the interlayer dielectric layer 300, and preferably has a larger etching selectivity ratio with respect to the planarization stop layer 301 and the interlayer dielectric layer 300, and the material of the diffusion barrier layer 302 may include at least one of metal, metal nitride, metal oxide, metal silicide, and the like, for example, at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten nitride (TiW), cobalt nitride (CoN), tungsten nitride (WN), Ti mixed TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WsiN), tantalum silicon nitride (TaSiN), and silicon nitride (sinin).
Then, an adhesion layer (not shown) and/or a seed layer (not shown) may be formed on the surface of the open diffusion barrier layer 302 by using processes such as atomic layer deposition, for example, a material of a metal nitride such as TiN and an inert metal such as cobalt (Co), tantalum (Ta), or ruthenium (Ru), and a material of a seed layer such as copper (Cu), titanium (Ti), tantalum (Ta), cobalt (Co), silver (Ag), gold (Au), etc. to facilitate nucleation, growth, and attachment of a subsequent conductive metal layer, and then, the opening is filled with the conductive metal layer 303 by using processes such as vacuum evaporation, sputtering, and electroplating, and the conductive metal layer is usually located above the interlayer dielectric layer 300 on both sides of the opening (i.e., covering the surface of the planarization stop layer 301), and an excess conductive metal layer outside the opening needs to be further removed by using a planarization process such as CMP, that is, the portion covering the surface of the planarization stop layer 301 is removed, so that the top surface of the filled conductive metal layer is flush with the top surface of the planarization stop layer 301, so as to form a first conductive structure (including the diffusion barrier layer 302 and the conductive metal layer 303) in the interlayer dielectric layer 300, and at the same time, provide a flat process platform for the subsequent process, where the first conductive structure may include at least one conductive material selected from a metal electrode, a conductive contact plug, and a metal interconnection line, and the material of the first conductive structure includes at least one metal element selected from copper (Cu), tungsten (W), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), vanadium (V), and chromium (Cr).
Referring to fig. 3B, in step S2, an appropriate etching process may be selected according to the materials of the conductive metal layer 303, the diffusion barrier layer 302, and the interlayer dielectric layer 300 to etch back the first conductive structure, and remove a portion of the thickness of the first conductive structure to form an etch-back trench 303 a. In this embodiment, a cyclic etching method is adopted to remove the first conductive structure with the required thickness and form the etch-back groove 303a with the required depth, specifically including the following steps: (a) depositing a protective layer (not shown, for example, some organic polymers) on the surfaces of the planarization stop layer 301, the diffusion barrier layer 302, and the conductive metal layer 303 using an atomic deposition process, a coating process, or the like, and patterning the protective layer to expose only a portion of the top surface or the entire top surface of the conductive metal layer; (b) hydrogen is used as main etching gas, oxygen and/or inert gas (such as helium, argon and the like) is used as carrier gas, and the conductive metal layer 303 is etched back by adopting a synchronous pulse etching process to a certain depth to form an etching-back groove; (c) removing the protective layer; (d) and (c) repeating the steps (a) to (c) circularly until the etch-back groove 303a is formed to expose the surface of the diffusion barrier layer 302 and have the required depth. The source power and the bias power in the synchronous pulse etching process are both in a pulse mode, and the pulse modes of the source power and the bias power are in the same frequency and the same phase.
Referring to fig. 3C and 3E, in step S3, a plasma etching process may be first used to remove the diffusion barrier layer 302 exposed by the etch-back trench 303a, wherein the etching gas used in the process may be tetrafluorideCarbon (CF)4) Nitrogen (N)2) And oxygen (O)2) The diffusion barrier layer 302 and the interlayer dielectric layer 300 have a high etching selectivity (e.g., greater than 1000); then, another plasma etching process or a CMP process may be employed to remove the planarization stop layer 301; then, another plasma etching process may be used to round the back-etched trench 303a, so as to round the top corner and the bottom corner of the back-etched trench 303a, thereby improving the step coverage capability of the subsequently deposited capping layer at the back-etched trench 303a, and improving the uniformity of the coverage thickness of the subsequently deposited capping layer on the sidewall and the bottom wall of the back-etched trench 303a, thereby reducing the contact resistance between layers and improving the device performance.
Referring to fig. 3E, in step S4, a thin line dielectric layer (liner) 304 may be formed on the etch-back trench 303a and the surface of the interlayer dielectric layer 300 by using atomic layer deposition or coating, the thickness of the line dielectric layer 304 is, for example, 100 angstroms to 500 angstroms, the line dielectric layer 304 may be made of a low K dielectric, an ultra-low K dielectric, silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN, NDC), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), carbon-containing silicon oxide, silicon oxynitride, or the like, on one hand, the line dielectric layer 304 can provide a contact surface for the subsequent deposition of the planar layer 305, enhance the adhesion between the planar layer 305 and the interlayer dielectric layer 300, and reduce the contact resistance, on the other hand, the line dielectric layer has the function of closing the first conductive structure, and can prevent the metal in the first conductive structure from diffusing into the interlayer dielectric layer 300 and the subsequently formed planar layer 305; then, an insulating dielectric material such as a low-K dielectric and/or an ultra-low-K dielectric is deposited on the surface of the line dielectric layer 304 by using a chemical vapor deposition, physical vapor deposition or coating process, the deposited insulating dielectric material has a thickness sufficient to fill the etch-back groove 303a and can accumulate a sufficient thickness on the global surface of the interlayer dielectric layer 300, and the deposited insulating dielectric material is planarized to form a planar layer 305 having a flat top surface, where the planar layer 305 has a required thickness on the interlayer dielectric layer 300, so as to provide a flat platform for a subsequent process. The line dielectric layer 304 and the planarization layer 305, i.e. the covering layer at least covering the surface of the etched-back trench described in step S4 of this embodiment, in other embodiments of the present invention, the covering layer may also be a stacked structure of more than three layers, and will not be described in detail herein.
With reference to fig. 3E, in step S5, the second conductive structure 306 may be directly formed on the surface of the planarization layer 305 through a deposition process of a conductive material such as a metal, and the distance D2 between the second conductive structure 306 and the first conductive structure (i.e., the conductive metal layer 303) is larger than D1 in fig. 1, so that the parasitic capacitance between the two structures is reduced, thereby reducing the RC delay and improving the device performance. In step S5 of other embodiments of the present invention, when the second conductive structure 306 is a part of an interconnect structure (e.g., a combination of a conductive plug and a metal interconnect line), the planarization layer 305 and the line dielectric layer 304 may be etched first, forming openings through the planarization layer 305 and the line dielectric layer 304, then filling a diffusion impervious layer and a conductive metal layer in the opening in sequence, and carrying out corresponding CMP treatment on the filled conductive metal layer, thereby forming a second conductive structure that is both in the planar layer 305 and on the surface of the planar layer 305, and, at this time, the distance D2 between the portion of the second conductive structure 306 on the surface of the planarization layer 305 (i.e. the metal interconnect line) and the first conductive structure (i.e. the conductive metal layer 303) is increased relative to D1 in figure 1, therefore, the parasitic capacitance between the two becomes smaller, thereby reducing the RC delay and improving the performance of the device.
In addition, referring to fig. 3E and fig. 1, compared with the interconnect structure shown in fig. 1, in the technical solution of the present invention, there is no planarization stop layer between the line dielectric layer 304 and the interlayer dielectric layer 300, and the thickness uniformity of the line dielectric layer 304 is higher on the whole, so that there is lower contact resistance between the first conductive structure (i.e., the conductive metal layer 303) and the second conductive structure 306, thereby further reducing RC delay and improving device performance.
It should be noted that, when the second conductive structure is a conductive plug and/or a metal interconnection line in the interconnection structure, and a new conductive structure (for example, a pad structure such as a new metal interconnection line, an aluminum pad, or a metal electrode) needs to be formed above the second conductive structure, the second conductive structure may be equivalent to the first conductive structure in the manufacturing method of the semiconductor device of the present invention, so as to perform the processes such as the etching back of the second conductive structure, the rounding of the etching back groove, and the like, thereby reducing the parasitic capacitance between the second conductive structure and the conductive structure above the second conductive structure, reducing the contact resistance between layers, further reducing the RC delay, and improving the device performance.
In summary, in the manufacturing method of the semiconductor device of the present invention, the etch-back groove is formed by removing a part of the thickness of the first conductive structure by etch-back to increase the thickness of the covering layer between the first conductive structure and the second conductive structure above the first conductive structure (i.e. to increase the distance between the first conductive structure and the second conductive structure separated by the covering layer), so as to reduce the parasitic capacitance, and meanwhile, the corner angle of the etch-back groove is rounded to increase the adhesion of the covering layer and the thickness uniformity on the sidewall and the bottom wall of the etch-back groove, so as to reduce the contact resistance between the first conductive structure and the second conductive structure, thereby reducing the RC delay and improving the device performance.
Referring to fig. 3E, the present invention further provides a semiconductor device, including: an interlayer dielectric layer 300; forming a first conductive structure in the interlayer dielectric layer 300, and forming a circular-cornered back-etched groove on the first conductive structure by the interlayer dielectric layer 300; a covering layer at least covering the surface of the etch-back groove; and a second conductive structure 306 on the surface of the blanket layer.
Wherein the first and second conductive structures may include at least one of a metal electrode, a conductive contact plug, and a metal interconnection line, respectively. In this embodiment, the first conductive structure includes a diffusion barrier layer 302 and a conductive metal layer 303 on a surface of the diffusion barrier layer 302, the diffusion barrier layer 302 may be made of at least one of metal, metal nitride, metal oxide, metal silicide, etc., for example, at least one of titanium (Ti), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten nitride (TiW), cobalt nitride (CoN), tungsten nitride (WN), Ti mixed TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WsN), tantalum silicon nitride (TaSiN), and silicon nitride, the conductive metal layer includes at least one of copper (Cu), tungsten (W), aluminum (Al), silver (Ag), gold (Au), platinum (Pt), iron (Fe), cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), vanadium (V), and chromium (Cr); the covering layer comprises a line dielectric layer 304 at least covering the surface of the etch-back groove and a flat layer 305 covering the line dielectric layer 304 and the surface of the interlayer dielectric layer 300, the line dielectric layer 304 can be made of a low-K dielectric, an ultra-low-K dielectric, silicon nitride (SiN), silicon carbide (SiC), silicon carbide nitride (SiCN, NDC), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), carbon-containing silicon oxide, silicon oxynitride and the like, and the interlayer dielectric layer 300 and the flat layer 305 can be made of a low-K dielectric or an ultra-low-K dielectric.
In other embodiments of the present invention, the first conductive structure may further include an adhesion layer (not shown) and/or a seed layer (not shown) between the diffusion barrier layer 302 and the conductive metal layer 303, the adhesion layer may be made of, for example, metal nitride such as TiN and inert metal such as cobalt (Co), tantalum (Ta) or ruthenium (Ru), and the seed layer may be made of, for example, copper (Cu), titanium (Ti), tantalum (Ta), cobalt (Co), silver (Ag), gold (Au), or the like.
In other embodiments of the present invention, the semiconductor device may further include a semiconductor substrate (not shown) under the interlayer dielectric layer 300, the semiconductor substrate may be any semiconductor substrate well known to those skilled in the art, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI), or the like, and may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), or silicon carbide (SiC), and the like, the semiconductor substrate may be a substrate on which a front end of line (FEOL) has been completed, the semiconductor substrate has a plurality of device isolation structures and a variety of active elements, such as MOS transistors, and passive elements, such as resistors and capacitors, the interlayer dielectric layer 300 may cover the active devices and the passive devices and has a relatively flat top surface.
The semiconductor device of the present invention can be formed by the method for manufacturing a semiconductor device of the present invention.
Therefore, the semiconductor device comprises the interlayer dielectric layer, the first conductive structure formed in the interlayer dielectric layer, the covering layer and the second conductive structure, wherein the interlayer dielectric layer forms a circular-cornered back etching groove on the first conductive structure, and the back etching groove enables the top surface of the first conductive structure to be lower than the top surface of the interlayer dielectric layer, so that the thickness of the covering layer between the first conductive structure and the second conductive structure above the first conductive structure can be increased, the parasitic capacitance is reduced, meanwhile, the covering layer is formed on the surface of the circular-cornered back etching groove, the adhesiveness is increased, the thickness uniformity of the covering layer on the side wall and the bottom wall of the back etching groove is improved, the contact resistance is reduced, and the RC delay can be reduced due to the reduction of the parasitic capacitance and the contact resistance, and the performance of the device is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (17)
1. A method of manufacturing a semiconductor device, comprising the steps of:
forming a first conductive structure in an interlayer dielectric layer, wherein the top surface of the first conductive structure is exposed out of the interlayer dielectric layer;
removing part of the thickness of the first conductive structure by adopting a back etching process to form a back etching groove;
performing round angle on the back etching groove;
forming a covering layer at least covering the surface of the back etching groove;
and forming a second conductive structure on the surface of the covering layer.
2. The method of claim 1, wherein forming the first conductive structure in the interlevel dielectric layer comprises:
providing a semiconductor substrate, and forming an interlayer dielectric layer on the semiconductor substrate;
forming an opening in the interlayer dielectric layer through an etching process;
forming a diffusion barrier layer overlying a surface of the opening;
and filling a conductive metal layer in the opening to form the first conductive structure in the interlayer dielectric layer, wherein the top surface of the first conductive structure is flush with the top surface of the interlayer dielectric layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the step of filling the opening with a conductive metal layer comprises:
depositing a conductive metal layer, wherein the conductive metal layer fills the opening and covers the upper part of the interlayer dielectric layer;
and removing the conductive metal layer above the interlayer dielectric layer by adopting a planarization process so as to fill the conductive metal layer in the opening.
4. The method of manufacturing a semiconductor device according to claim 3, wherein before the etching of the interlayer dielectric layer to form the opening, a planarization stop layer is further formed on a surface of the interlayer dielectric layer, the deposited conductive metal layer fills the opening and covers a surface of the planarization stop layer, and the conductive metal layer on the surface of the planarization stop layer is removed by using a planarization process so that the opening is filled with the conductive metal layer.
5. The method for manufacturing a semiconductor device according to claim 4, wherein the planarization stop layer is removed before the back-etched trench is rounded.
6. The method for manufacturing a semiconductor device according to claim 2, wherein after the diffusion barrier layer is formed in the opening and before the opening is filled with the conductive metal layer, an adhesion layer and/or a seed layer is further formed on a surface of the diffusion barrier layer.
7. The method for manufacturing a semiconductor device according to claim 2, wherein a material of the diffusion barrier layer includes at least one of tantalum, titanium, tantalum nitride, titanium tungsten, tungsten nitride, titanium aluminide, titanium silicon nitride, tungsten silicon nitride, tantalum silicon nitride, and silicon nitride.
8. The method for manufacturing a semiconductor device according to claim 2, wherein the diffusion barrier layer exposed by the etch-back groove is etched away after the etch-back groove is formed and before the etch-back groove is rounded.
9. The manufacturing method of a semiconductor device according to claim 8, wherein the diffusion barrier layer exposed by the etch-back groove is etched away by using a plasma etching process.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the etch-back process for removing a part of the thickness of the first conductive structure is a synchronous pulse etching process.
11. The manufacturing method of a semiconductor device according to any one of claims 1 to 10, wherein the first conductive structure and the second conductive structure respectively include at least one of a metal electrode, a conductive contact plug, and a metal interconnection line.
12. The method for manufacturing a semiconductor device according to claim 11, wherein the first conductive structure and the second conductive structure are made of a material containing at least one metal element selected from the group consisting of copper, tungsten, aluminum, silver, gold, platinum, iron, cobalt, nickel, molybdenum, titanium, vanadium, and chromium.
13. The method for manufacturing a semiconductor device according to claim 11, wherein the step of forming the cover layer covering at least the surface of the etch-back groove comprises:
forming a line dielectric layer at least covering the surface of the back etching groove;
and forming a flat layer with a flat top surface on the surfaces of the line dielectric layer and the interlayer dielectric layer.
14. A semiconductor device, comprising:
an interlayer dielectric layer;
the first conductive structure is formed in the interlayer dielectric layer, and the interlayer dielectric layer forms a circular angle back etching groove on the first conductive structure;
the covering layer covers the surface of the back etching groove;
and the second conductive structure is positioned on the surface of the covering layer.
15. The semiconductor device of claim 14, wherein the first conductive structure comprises a diffusion barrier layer and a conductive metal layer on a surface of the diffusion barrier layer.
16. The semiconductor device of claim 14, wherein the capping layer comprises a line dielectric layer overlying a surface of the etch-back trench and a planarization layer overlying a surface of the line dielectric layer and the interlevel dielectric layer.
17. The semiconductor device of claim 14, wherein the first conductive structure and the second conductive structure each include at least one of a metal electrode, a conductive contact plug, and a metal interconnect line.
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