CN116647223A - Gate-level driving circuit, chip and electronic equipment - Google Patents
Gate-level driving circuit, chip and electronic equipment Download PDFInfo
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- CN116647223A CN116647223A CN202310908144.6A CN202310908144A CN116647223A CN 116647223 A CN116647223 A CN 116647223A CN 202310908144 A CN202310908144 A CN 202310908144A CN 116647223 A CN116647223 A CN 116647223A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
- H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The application discloses a gate-level driving circuit, a chip and electronic equipment, wherein the gate-level driving circuit comprises: the voltage detection module is used for detecting drain-source voltage between the drain electrode and the source electrode of the MOSFET and generating a first level signal according to the drain-source voltage; the pulse generation module is used for receiving the first pulse signal and the first level signal and generating a second pulse signal, a third pulse signal and a fourth pulse signal according to the first level signal and the first pulse signal; the first control module is used for generating gate-level opening current according to the second pulse signal so as to control the MOSFET to be conducted; generating a first gate-off current according to the third pulse signal to control the MOSFET to be turned off; and the second control module is used for generating a second gate-level turn-off current according to the fourth pulse signal so as to control the MOSFET to be turned off, wherein the second gate-level turn-off current is smaller than the first gate-level turn-off current. The application turns off the MOSFET by only turning off the current through two gate stages, has simple circuit structure, greatly reduces the turn-off delay of the MOSFET, and can quickly inhibit the voltage spike of the MOSFET.
Description
Technical Field
The application relates to the technical field of power semiconductors, in particular to a gate-level driving circuit, a chip and electronic equipment.
Background
The MOSFET device has the advantages of low loss, high working temperature, high on-off speed and the like when being used as a switching device, however, the switching-off process of the MOSFET device can generate larger voltage change and current change, so that the gate level of the MOSFET can generate larger voltage peak and oscillation, and further, the problem of electromagnetic interference is caused, and the stability and the safety of a circuit system are affected.
At present, a multi-path gate resistance switching off MOSFET is arranged in a gate driving circuit of the MOSFET to relieve voltage spikes and oscillation phenomena of the MOSFET in the turn-off process, or a multi-path gate voltage switching off MOSFET is arranged in the gate driving circuit of the MOSFET to relieve the voltage spikes of the MOSFET in the turn-off process, however, the complexity of the gate driving circuit of the MOSFET is increased by arranging the multi-path gate resistance and the multi-path gate voltage, so that the turn-off process delay of the MOSFET is increased, and the voltage spikes generated by the MOSFET are difficult to be quickly inhibited.
Disclosure of Invention
In view of the above, the present application provides a gate driving circuit, a chip and an electronic device, so as to solve the above technical problems.
In a first aspect, the present application provides a gate level driving circuit comprising:
the voltage detection module is used for detecting drain-source voltage between the drain electrode and the source electrode of the MOSFET and generating a first level signal according to the drain-source voltage;
the pulse generation module is used for receiving a first pulse signal and the first level signal and generating a second pulse signal, a third pulse signal and a fourth pulse signal according to the first level signal and the first pulse signal;
the first control module is used for receiving the second pulse signal, and generating gate-on current according to the second pulse signal so as to control the MOSFET to be conducted; receiving the third pulse signal, and generating a first gate-off current according to the third pulse signal to control the MOSFET to be turned off;
and the second control module is used for receiving the fourth pulse signal, generating a second gate-level turn-off current according to the fourth pulse signal so as to control the MOSFET to be turned off, wherein the second gate-level turn-off current is smaller than the first gate-level turn-off current.
In a second aspect, the present application further provides a chip, including the gate-level driving circuit described in the first aspect.
In a third aspect, the present application further provides an electronic device, including a device main body and a chip set in the device main body according to the second aspect.
According to the gate-level driving circuit provided by the application, the voltage detection module directly detects the drain-source voltage between the drain electrode and the source electrode of the MOSFET, the first level signal is generated according to the drain voltage, the pulse generation module obtains the second pulse signal, the third pulse signal and the fourth pulse signal according to the first pulse signal and the first level signal so as to control the control module of the later stage, the first control module drives the MOSFET according to the second pulse signal and the third pulse signal so as to realize the on and off of the MOSFET under the normal condition, and the second control module drives the MOSFET according to the fourth pulse signal so as to realize the off of the MOSFET under the abnormal condition through smaller gate-level off current. The gate-level driving circuit provided by the application does not need complex multi-level voltage or multi-level resistance, has a simple circuit structure, greatly reduces the turn-off delay time of the MOSFET, and can quickly inhibit the voltage peak of the MOSFET.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a gate driving circuit according to an embodiment of the present application.
Fig. 2 shows a schematic structural diagram of a voltage detection module according to an embodiment of the present application.
Fig. 3 shows a schematic structural diagram of a pulse generating module according to an embodiment of the present application.
Fig. 4 shows a schematic structural diagram of a first control module according to an embodiment of the present application.
Fig. 5 shows a schematic structural diagram of a second control module according to an embodiment of the present application.
Fig. 6 shows a schematic diagram of a gate driving circuit according to an embodiment of the present application.
Fig. 7 shows a timing diagram of a gate driving circuit according to an embodiment of the application.
Detailed Description
In order to enable those skilled in the art to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the present application in the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It should be noted that "connection" in the embodiments of the present application is understood as an electrical connection, and two electrical components may be directly or indirectly connected between two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.
The second pole of each transistor used in the embodiment of the application is one of a source electrode and a drain electrode, and the third pole of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain may be indistinguishable in structure, that is, the second and third poles of the transistor in embodiments of the present application may be indistinguishable in structure.
Compared with Si MOSFET devices or other Si-based power semiconductor devices, the SiC MOSFET devices have the advantages of lower loss, higher working temperature, faster switching speed and the like, but compared with Si MOSFET devices, the switching-off process can generate larger voltage change and current change, which can cause larger voltage peak and oscillation of the gate level of the SiC MOSFET, thereby bringing about electromagnetic interference problems, and the traditional technical means for solving the technical problems are as follows: the gate-level driving circuit of the MOSFET is provided with a plurality of gate-level resistors, the MOSFET is turned off by switching different resistors so as to inhibit voltage spikes and oscillation phenomena of the MOSFET in the turn-off process, or the gate-level driving circuit of the MOSFET is provided with a plurality of gate-level voltages, the MOSFET is turned off by switching different voltages so as to relieve the voltage spikes and oscillation phenomena of the MOSFET in the turn-off process, however, the two technical schemes can increase the complexity of the gate-level driving circuit of the MOSFET, so that the turn-off process delay of the MOSFET becomes high, and the voltage spikes generated by the MOSFET cannot be inhibited rapidly.
In view of this, an embodiment of the present application provides a gate driving circuit, and fig. 1 shows a schematic block diagram of the gate driving circuit provided in the embodiment of the present application, and as shown in fig. 1, the gate driving circuit provided in the embodiment of the present application includes a voltage detection module, a pulse generation module, a first control module, and a second control module, for Si MOSFET devices, other Si-based power semiconductor devices, and SiC MOSFET devices, which can quickly suppress voltage spikes generated by the Si MOSFET devices.
The voltage detection module is used for detecting drain-source voltage between the drain electrode and the source electrode of the MOSFET and generating a first level signal according to the drain-source voltage; when the MOSFET device is used as a switching device, a voltage spike is generated in the process of turning off the MOSFET, the voltage jumps in a very short time, and even the voltage possibly exceeds the maximum voltage bearable by the device, so that the device is burnt out; optionally, in the embodiment of the present application, the voltage change is monitored by determining whether the drain-source voltage exceeds the threshold voltage of the circuit design, and generating the first level signal, if the drain-source voltage exceeds the threshold voltage, the first level signal is kept at a high level or a low level, and if the drain-source voltage does not exceed the threshold voltage, the first level signal is kept at an opposite level, where the selected threshold voltage is generally lower than the maximum voltage that can be borne by the MOSFET, so as to avoid the circuit from being damaged.
The pulse generation module is used for receiving the first pulse signal and the first level signal and generating a second pulse signal, a third pulse signal and a fourth pulse signal according to the first level signal and the first pulse signal; optionally, the first pulse signal is a PWM signal (Pulse width modulation ) sent by an external circuit and used for driving a post module of the gate driving circuit, and in the embodiment of the present application, the pulse generating module is further connected to the voltage detecting module, and the first control module and the second control module for driving the gate driving circuit are under the combined action of the first pulse signal and the first level signal; the external circuit outputting the first pulse signal may be any circuit that meets the output condition, which is not limited in the embodiment of the present application.
The first control module is used for receiving the second pulse signal, and generating gate-on current according to the second pulse signal so as to control the MOSFET to be conducted; receiving a third pulse signal, and generating a first gate-level turn-off current according to the third pulse signal to control the MOSFET to turn off; the first control module acts on the gate of the MOSFET to turn on the MOSFET and acts on the gate of the MOSFET to turn off the MOSFET when the drain-source voltage does not exceed the threshold voltage.
The second control module is used for receiving a fourth pulse signal, and generating a second gate-level turn-off current according to the fourth pulse signal so as to control the MOSFET to be turned off; the second control module acts on the MOSFET to turn off the MOSFET when the drain-source voltage exceeds the threshold voltage, namely, when the MOSFET is turned off by the first control module, the gate-level driving circuit can enable the first control module not to generate current any more when the voltage spike is overlarge, and the second control module generates a second gate-level turn-off current to turn off the MOSFET; the first gate-level turn-off current is larger than the second gate-level turn-off current, when the gate-level turn-off current is large, the MOSFET turn-off speed is high, but the voltage spike is larger at the moment.
According to the gate-level driving circuit provided by the embodiment of the application, the voltage detection module directly detects the drain-source voltage between the drain electrode and the source electrode of the MOSFET, the first level signal is generated according to the drain voltage, the pulse generation module obtains the second pulse signal, the third pulse signal and the fourth pulse signal according to the first pulse signal and the first level signal so as to control the first control module and the second control module of the later stage, the first control module drives the MOSFET according to the second pulse signal and the third pulse signal so as to realize the on and off of the MOSFET under the normal condition, and the second control module drives the MOSFET according to the fourth pulse signal so as to realize the turn-off of the MOSFET under the abnormal condition through smaller gate-level turn-off current. The gate-level driving circuit provided by the application does not need complex multi-level voltage or multi-level resistance, reduces the complexity of the circuit, reduces the turn-off delay time of the MOSFET, and can quickly inhibit the voltage peak of the MOSFET.
In some embodiments, in the gate-level driving circuit provided by the embodiment of the present application, when the voltage detection module detects that the drain-source voltage exceeds the threshold voltage of the circuit design, the generated first level signal is in the first state, and the first control module generates the first gate-level off current according to the third pulse signal to control the MOSFET to be turned off; when the voltage detection module detects that the drain-source voltage does not exceed the threshold voltage, the generated first level signal is in a second state, and the pulse generation module generates a second gate-level turn-off current according to the fourth pulse signal to control the MOSFET to be turned off; the first state is high level or low level, and the second state is opposite to the first state, i.e. when the first state is high level, the second state is low level, and when the first state is low level, the second state is high level.
In the embodiment of the application, the first level signal directly affects the generation of the first gate-level turn-off current and the second gate-level turn-off current, namely, the detection result of the voltage detection module directly affects the turn-off mode of the MOSFET, and an additional control circuit is not required to be arranged to control the multi-path resistor or the multi-path voltage switch to turn off the MOSFET, so that the circuit delay is greatly shortened.
In some embodiments, fig. 2 shows a schematic structural diagram of a voltage detection module according to an embodiment of the present application, where, as shown in fig. 2, the voltage detection module includes a comparator, a voltage division unit, and a pull-up resistor R3.
The voltage dividing unit is connected with the first input end of the comparator and is used for being connected with the drain electrode of the MOSFET, the voltage dividing unit is used for detecting drain-source voltage between the drain electrode and the source electrode of the MOSFET, the divided voltage of the drain-source voltage is input to the first input end of the comparator, specifically, the drain-source voltage is high voltage and is directly input to the comparator, the device is easy to damage, and therefore the voltage input to the comparator is reduced by arranging the voltage dividing unit.
The second input end of the comparator is used for receiving a reference voltage Vref, the output end of the comparator is connected with the pulse generation module and is used for outputting a first level signal generated by the comparator according to a comparison result of the reference voltage and the divided voltage to the pulse generation module, wherein the reference voltage is determined by an external circuit module according to a threshold voltage selected by a circuit design process; optionally, the value of the divided voltage is a voltage value obtained after the drain-source voltage is reduced, and similarly, the value of the reference voltage may also be a voltage value obtained after the threshold voltage is correspondingly reduced.
The first end of the pull-up resistor is connected with the output end of the comparator, the second end of the pull-up resistor is used for being connected with a positive power supply VCC, and the output end of the comparator is an OC gate (Open Collector Open gate), so that if the pull-up resistor is not used, the comparator cannot output a high level, but corresponds to a wire in a suspended state, and the comparator can output the high level by setting the pull-up resistor.
In some embodiments, in the gate driving circuit provided by the embodiments of the present application, the voltage dividing unit of the voltage detection module includes a first resistor R1 and a second resistor R2, where a first end of the first resistor is connected to a first end of the second resistor, and a second end of the first resistor is used to connect to a drain of the MOSFET; the first end of the second resistor R2 is also connected with the second input end of the comparator, the second end of the second resistor is used for connecting a negative power supply VEE, and specifically, the divided voltage input to the first input end of the comparator by the voltage dividing unit is the voltage of the second resistor; it should be clear that in the embodiment of the application, the positive power supply VCC means that the output voltage of this power supply is higher than the output voltage of the negative power supply VEE, i.e. the positive power supply VCC and the negative power supply VEE are relatively present, not absolutely present.
According to the gate level driving circuit provided by the embodiment of the application, the comparator, the voltage dividing unit and the pull-up resistor are arranged to form the voltage detection module, the voltages at the two ends of the drain electrode and the source electrode of the MOSFET of the voltage detection module are compared with the preset reference voltage, and then the first level signal is output, so that whether the voltage peak exceeds the threshold voltage or not is rapidly judged through the comparator, and the circuit delay is reduced.
In some embodiments, to determine whether the voltage spike exceeds the threshold voltage more quickly, the comparator of the voltage detection module may also select a high-speed comparator to further reduce the circuit delay.
Fig. 3 is a schematic diagram of a pulse generating module according to an embodiment of the present application, where, as shown in fig. 3, the pulse generating module includes a first logical not unit, a logical and unit, and a second logical not unit.
The input end of the first logical non unit is connected with an external circuit and used for receiving a first pulse signal output by the external circuit, the output end of the first logical non unit is connected with the first control module and used for outputting a logical non result of the first pulse signal to the first control module, the first logical non unit is also connected with the first input end of the logical AND unit and used for outputting a logical non result of the first pulse signal to the logical AND unit, and the logical non result is a second pulse signal.
The second input end of the logic AND unit is connected with the voltage detection module and is used for receiving a first level signal, the output end of the logic AND unit is connected with the first control module and is used for outputting a logic AND result of the second pulse signal and the first level signal to the first control module, and the logic AND result is a third pulse signal;
the input end of the second logic NOT unit is connected with the voltage detection module and used for receiving the first level signal, the output end of the second logic NOT unit is connected with the second control module and used for outputting a logic NOT result of the first level signal to the second control module, and the logic NOT result is a fourth pulse signal.
The gate level driving circuit provided by the embodiment of the application has the advantages that the pulse generating module comprises the first logic NOT unit, the logic AND unit and the second logic NOT unit, and the first level signal output by the first pulse signal and the voltage detecting module can be subjected to logic processing rapidly, so that the circuit delay is further reduced.
In some embodiments, fig. 4 shows a schematic structural diagram of a first control module provided in an embodiment of the present application, where, as shown in fig. 4, the first control module includes:
the first electrode of the first transistor is connected with the pulse generation module and is used for receiving a second pulse signal; the second stage of the first transistor is used for being connected with a positive power supply VCC, and the third stage of the first transistor is connected with the first end of the on resistor and used for generating gate-stage on current Ig1; the second end of the turn-on resistor is used for connecting the gate level of the MOSFET, specifically, the second pulse signal enables the first transistor to be turned on, and then gate-level turn-on current is generated on the turn-on resistor, and the gate-level turn-on current is used for enabling the MOSFET to be turned on.
The second transistor and the first turn-off resistor Rgoff1, the first pole of the second transistor is connected with the pulse generation module, be used for receiving the third pulse signal, the second level of the second transistor is used for connecting negative power VEE, the third level of the second transistor is connected with the first end of first turn-off resistor, be used for producing first gate level off current Ig2, the second end of first turn-off resistor is used for connecting the gate level of MOSFET, specifically, the third pulse signal makes the second transistor switch on, and then produce first gate level off current on first turn-off resistor, first gate level off current is used for making MOSFET cut-off, can produce voltage spike when first gate level off current turn-off MOSFET, if voltage spike that produces does not surpass threshold voltage, gate level drive circuit cuts off MOSFET through first gate level off current all the time.
Fig. 5 shows a schematic structural diagram of a second control module according to an embodiment of the present application, where, as shown in fig. 5, the second control module includes:
the second stage of the third transistor is connected with the first end of the second turn-off resistor and is used for generating a second gate-stage turn-off current Ig3, the second end of the second turn-off resistor is connected with the gate stage of the MOSFET, specifically, the fourth pulse signal enables the third transistor to be turned on, and then the second gate-stage turn-off current is generated on the second turn-off resistor, the second gate-stage turn-off current is used for enabling the MOSFET to be turned off, a voltage spike is generated when the first gate-stage turn-off current turns off the MOSFET, if the voltage spike generated in the first gate-stage turn-off current turn-off process exceeds a threshold voltage, the level of the third pulse signal received by the second transistor is turned over after feedback of the voltage detection module and the pulse generation module, the second transistor turns off so that the first control module does not generate the first gate-stage turn-off current, and the fourth pulse signal received by the second transistor turns over so that the second control module generates the second gate-stage turn-off current SFEY.
In some embodiments, in the gate driving circuit provided by the embodiment of the present application, the second turn-off resistor includes an adjustable resistor, and is configured to control the magnitude of the turn-off current of the second gate by adjusting the resistance value, so as to control the turn-off speed of the MOSFET.
Compared with the traditional gate-level driving circuit, the gate-level driving circuit provided by the embodiment of the application does not need complex multi-level voltage or multi-level resistance, has a simple circuit structure, does not need an additional control circuit in the process of controlling the MOSFET, reduces circuit delay and realizes quick suppression of the voltage spike of the MOSFETD.
Fig. 6 shows a schematic diagram of a gate driving circuit according to an embodiment of the present application, where in the voltage detection circuit, as shown in fig. 6, taking driving SiC MOSFETs as an example, a non-inverting input terminal of a comparator is configured to receive a reference voltage, an inverting input terminal of the comparator is configured to receive a divided voltage, the divided voltage is smaller than the reference voltage to indicate that a voltage spike is normal, a first level signal output by the comparator is a high level, the divided voltage is larger than the reference voltage to indicate that the voltage spike is abnormal, and a first level signal output by the comparator is a low level; based on the first level signal, the truth table of the second pulse signal, the third pulse signal and the fourth pulse signal generated by the pulse generating module is as follows:
as shown in fig. 6, the first transistor selects a P-type MOS transistor with low-level turn-on, the second transistor selects an N-type MOS transistor with high-level turn-on, and the third transistor selects an N-type MOS transistor with high-level turn-on.
The first pulse signal is high level to indicate that the MOSFET is turned on, and no voltage peak exists when the MOSFET is turned on, so that the first level signal is high level, the second pulse signal generated by the pulse generating module is low level at the moment, a first transistor of a P-type MOS tube in the first control module is conducted, and gate-level on current is generated to conduct the MOSFET; the third pulse signal generated by the pulse generating module is of low level, and the second transistor of the N-type MOS transistor cannot be conducted, so that no first gate level off current is generated; the fourth pulse signal generated by the pulse generating module is in a low level, and the third transistor of the N-type MOS transistor cannot be turned on, so that no second gate level turn-off current is generated.
The first pulse signal is low level to turn off the MOSFET, no voltage spike is generated when the MOSFET starts to turn off or the voltage spike does not exceed the threshold voltage, and the reference voltage is larger than the divided voltage, so that the first level signal is high level, and the second pulse signal generated by the pulse generating module is high level at the moment and cannot turn on the first transistor of the P-type MOS transistor, so that no gate-on current is generated; the third pulse signal generated by the pulse generating module is high level, and the second transistor of the N-type MOS transistor is turned on, so that a first gate turn-off current is generated; the fourth pulse signal generated by the pulse generating module is in a low level, and the third transistor of the N-type MOS transistor cannot be turned on, so that no second gate level turn-off current is generated.
When the MOSFET is turned off, if the voltage peak exceeds the threshold voltage, the reference voltage is smaller than the divided voltage, the first level signal is changed from high level to low level, and the second pulse signal generated by the pulse generating module is high level and cannot turn on the first transistor of the P-type MOS transistor, so that no gate-on current is generated; the third pulse signal generated by the pulse generating module is of low level and cannot turn on the second transistor of the N-type MOS transistor, so that no first gate turn-off current is generated; the fourth pulse signal generated by the pulse generating module is in a high level, and the third transistor of the N-type MOS transistor is turned on, so that the second gate turn-off current is generated.
It should be clear that, in the gate-level driving circuit shown in fig. 6 provided in the embodiment of the present application, in the voltage detection module, the reference voltage is received through the non-inverting input terminal of the comparator, the divided voltage is received through the inverting input terminal of the comparator to control the first level signal, but the designer can also receive the divided voltage through the non-inverting input terminal of the comparator, and the reference voltage is received through the inverting input terminal to control the first level signal, which is different in that the first level signals of the two schemes are completely opposite, but still can implement the gate-level driving circuit provided in the embodiment of the present application; that is, the gate driving circuit provided by the embodiment of the application does not require the level states of the first level signal, the first pulse signal, the second pulse signal, the third pulse signal and the fourth pulse signal, so long as the conditions are satisfied: when the MOSFET is turned on, the second pulse signal can enable the first transistor to be turned on, the third pulse signal cannot enable the second transistor to be turned on, and the fourth pulse signal cannot enable the third transistor to be turned on; when the voltage peak does not exceed the threshold voltage and the MOSFET is turned off, the third pulse signal can enable the second transistor to be turned on, the second pulse signal cannot conduct the first transistor, and the fourth pulse signal cannot conduct the third static transistor; when the voltage peak exceeds the threshold voltage and the MOSFET is turned off, the fourth pulse signal can enable the third transistor to be turned on, the second pulse signal cannot enable the first transistor to be turned on, and the third pulse signal cannot enable the second transistor to be turned on.
It should be clear that, in the gate driving circuit shown in fig. 6 provided in the embodiment of the present application, the first transistor is set to be a P-type MOS transistor, the second transistor is set to be an N-type MOS transistor, and the third transistor is set to be an N-type MOS transistor, but when designing the circuit, a designer sets the first transistor, the second transistor and the third transistor to be MOS transistors of a type opposite to that of the gate driving circuit shown in fig. 6, so long as the condition is satisfied: the second transistor and the third transistor are turned off when the first transistor is turned on, the first transistor and the third transistor are turned off when the second transistor is turned on, and the first transistor and the second transistor are turned off when the third transistor is turned on.
FIG. 7 shows a timing diagram of a gate driving circuit according to an embodiment of the present application, as shown in FIG. 7, V GS For the change of the gate voltage during the MOSFET turn-off process, the turn-off process of the MOSFET is as follows:
the MOSFET is started to be turned off at the time t0, and the drain-source voltage V is not generated DS The third pulse signal generated by the pulse generating module is changed from low level to high level, and the first control module generates a first gate-off current Ig2; the time t 0-t 1 is the process of the first control module turning off the MOSFET, and the voltage peak V appears in the circuit ds And V is ds Is larger and larger until the threshold voltage V is exceeded at the time t 0-t 1 ds_th When the voltage is spike V ds Exceeding threshold voltage V ds_th At this time, the reference voltage is smaller than the divided voltage, the first level signal is changed from high level to low level, and then the third pulse signal generated by the pulse generating module is changed from high level to low level, and the fourth pulse signal is changed from low level to high level.
the time t 1-t 2 is the process of the second control module turning off the MOSFET to restrain voltage spike, the second control module generates the second gate turn-off current Ig3, and the voltage spike V is because the second gate turn-off current is far smaller than the first gate turn-off current ds Starting to decrease until the MOSFET is completely turned off after the time t 2;
it should be clear that, in the gate driving circuit provided in the embodiment of the present application, fig. 7 only shows a timing chart of voltage spikes exceeding the threshold voltage, and does not indicate that each turn-off process voltage spike can exceed the threshold voltage.
The embodiment of the application also provides a Chip (Integrated Circuit, IC) which comprises the gate-level driving circuit provided by the embodiment of the application, and the Chip can be, but is not limited to, an SOC (System on Chip) Chip or an SIP (System in package ) Chip. The gate-level driving circuit has a simple structure, greatly reduces the turn-off delay of the MOSFET, can quickly inhibit the voltage peak of the MOSFET, and improves the chip performance.
The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment main body, wherein a gate-level driving circuit in the chip has a simple structure, greatly reduces the turn-off delay of the MOSFET, can quickly inhibit the voltage peak of the MOSFET, and improves the performance of the electronic equipment.
The foregoing is a further detailed description of the application in connection with specific embodiments, and it is not intended that the application be limited to such description. It will be apparent to those skilled in the art that several simple deductions or substitutions can be made without departing from the spirit of the application, and the scope of the application is to be considered as the scope of the application.
Claims (10)
1. A gate level driving circuit, comprising:
the voltage detection module is used for detecting drain-source voltage between the drain electrode and the source electrode of the MOSFET and generating a first level signal according to the drain-source voltage;
the pulse generation module is used for receiving a first pulse signal and the first level signal and generating a second pulse signal, a third pulse signal and a fourth pulse signal according to the first level signal and the first pulse signal;
the first control module is used for receiving the second pulse signal, and generating gate-on current according to the second pulse signal so as to control the MOSFET to be conducted; receiving the third pulse signal, and generating a first gate-off current according to the third pulse signal to control the MOSFET to be turned off;
and the second control module is used for receiving the fourth pulse signal, generating a second gate-level turn-off current according to the fourth pulse signal so as to control the MOSFET to be turned off, wherein the second gate-level turn-off current is smaller than the first gate-level turn-off current.
2. The gate driving circuit according to claim 1, wherein,
the first level signal generated by the voltage detection module is in a first state, the first control module generates the first gate-off current according to the third pulse signal to control the MOSFET to be turned off,
the first level signal generated by the voltage detection module is in a second state, the pulse generation module generates the second gate-level off current according to the fourth pulse signal to control the MOSFET to be turned off,
the first state is a high level or a low level, and the second state is a level opposite to the first state.
3. The gate driving circuit of claim 1, wherein the voltage detection module comprises a comparator, a voltage dividing unit and a pull-up resistor,
the voltage dividing unit is connected with the first input end of the comparator and is used for being connected with the drain electrode of the MOSFET, detecting the drain-source voltage between the drain electrode and the source electrode of the MOSFET and inputting the divided voltage of the drain-source voltage to the first input end of the comparator;
the second input end of the comparator is used for receiving a reference voltage, and the output end of the comparator is connected with the pulse generation module and is used for outputting a first level signal generated by the comparator according to the comparison result of the reference voltage and the divided voltage to the pulse generation module;
the first end of the pull-up resistor is connected with the output end of the comparator, and the second end of the pull-up resistor is used for being connected with a positive power supply.
4. The gate driving circuit of claim 3, wherein the voltage dividing unit comprises a first resistor and a second resistor,
the first end of the first resistor is connected with the first end of the second resistor, and the second end of the first resistor is used for being connected with the drain electrode of the MOSFET;
the first end of the second resistor is also connected with the second input end of the comparator, and the second end of the second resistor is used for being connected with a negative power supply.
5. The gate driving circuit of claim 1, wherein the pulse generating module comprises a first logical not unit, a logical AND unit, and a second logical not unit,
the input end of the first logical non unit is used for receiving the first pulse signal, the output end of the first logical non unit is connected with the first control module and used for outputting a logical non result of the first pulse signal to the first control module, the first logical non unit is also connected with the first input end of the logical AND unit and used for outputting a logical non result of the first pulse signal to the logical AND unit, and the logical non result is the second pulse signal;
the second input end of the logic AND unit is connected with the voltage detection module and is used for receiving the first level signal, the output end of the logic AND unit is connected with the first control module and is used for outputting a logic AND result of the second pulse signal and the first level signal to the first control module, and the logic AND result is the third pulse signal;
the input end of the second logic NOT unit is connected with the voltage detection module and is used for receiving the first level signal, the output end of the second logic NOT unit is connected with the second control module and is used for outputting a logic NOT result of the first level signal to the second control module, and the logic NOT result is the fourth pulse signal.
6. The gate level driving circuit of claim 1, wherein the first control module comprises:
the first electrode of the first transistor is connected with the pulse generation module and is used for receiving the second pulse signal; the second stage of the first transistor is used for being connected with a positive power supply, and the third stage of the first transistor is connected with the first end of the turn-on resistor and used for generating gate turn-on current; the second end of the opening resistor is used for being connected with the gate level of the MOSFET;
the second transistor and the first turn-off resistor, the first pole of the second transistor is connected with the pulse generating module and used for receiving the third pulse signal, the second stage of the second transistor is used for being connected with a negative power supply, the third stage of the second transistor is connected with the first end of the first turn-off resistor and used for generating a first gate turn-off current, and the second end of the first turn-off resistor is used for being connected with the gate of the MOSFET.
7. The gate level driving circuit of claim 1, wherein the second control module comprises:
the first pole of the third transistor is connected with the pulse generating module and is used for receiving the fourth pulse signal, the second pole of the third transistor is used for being connected with a negative power supply, the third pole of the third transistor is connected with the first end of the second turn-off resistor and is used for generating a second gate turn-off current, and the second end of the second turn-off resistor is used for being connected with the gate of the MOSFET.
8. The gate level driving circuit of claim 7, wherein the second off-resistance comprises:
and the adjustable resistor is used for controlling the magnitude of the second gate turn-off current.
9. A chip comprising the gate driving circuit of any one of claims 1-8.
10. An electronic device comprising a device body and a chip as claimed in claim 9 provided on the device body.
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| CN202310908144.6A CN116647223A (en) | 2023-07-24 | 2023-07-24 | Gate-level driving circuit, chip and electronic equipment |
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| CN202310908144.6A CN116647223A (en) | 2023-07-24 | 2023-07-24 | Gate-level driving circuit, chip and electronic equipment |
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