CN116646246A - Ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method - Google Patents

Ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method Download PDF

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CN116646246A
CN116646246A CN202310706680.8A CN202310706680A CN116646246A CN 116646246 A CN116646246 A CN 116646246A CN 202310706680 A CN202310706680 A CN 202310706680A CN 116646246 A CN116646246 A CN 116646246A
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ion implantation
ionizing radiation
ion
ions
process chip
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孟德超
张光辉
杨萍
周航
刘杨
钟乐
周泉丰
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Institute of Electronic Engineering of CAEP
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Abstract

The invention discloses an ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method, which comprises the following steps: obtaining a sensitive position, thinning a passivation layer of a specified circuit or a specified area of a chip circuit, and/or thinning the thickness of a metal layer to obtain a structure optimization device; ion implantation is carried out on the structure optimization device; the annealing treatment repairs damage caused by ion implantation. The invention is based on structural design optimization of transistor devices, so as to obviously reduce the range of ions to be injected, obviously improve the irradiation resistance of the devices, and develop the specific ion injection of the silicon oxide layer of the appointed device (sensitive) or the appointed device area of the bipolar process chip by utilizing commercial ion injection equipment, thereby realizing the development of the anti-ionizing radiation reinforcement process of the electronic chip with low cost, rapidness and high degree of freedom.

Description

Ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method
Technical Field
The invention relates to the technical field of electrons, in particular to an ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method.
Background
In the fields of aerospace, nuclear and the like, high-energy particles or photons generate an ionization radiation effect, a single particle effect, a displacement radiation effect and the like in a semiconductor device, so that the reliability of the semiconductor device is seriously affected. For transistor devices employing SiO2 as the insulating material and passivation layer, a large number of electron-hole pairs are generated in the oxide layer under the influence of ionizing radiation, since the mobility of electrons in the oxide is much higher than that of holes. Under the action of the electric field, electrons drift at a fast rate toward the electrode terminal, while holes with lower mobility are trapped by oxide traps, forming positive oxide charges. In addition, holes react with hydrogen-containing defects in the migration process of the silicon dioxide layer to release hydrogen ions. The hydrogen ions are gradually transported to Si/SiO 2 The interface reacts with Si-H bonds to generate dangling bonds (interface states), thereby causing the degradation of the electrical performance of the device. Both the oxide charge and the interface state change the recombination rate of carriers, and for a bipolar transistor, the oxide traps positive charges and the interface state can increase the recombination rate of a space charge region of a bipolar transistor base region, so that the base current is increased, and the current gain of the bipolar transistor is reduced. For bipolar process chips, ionizing radiation can drift, degrade, or even severely directly fail the electrical parameters of the chip. Therefore, the anti-radiation reinforcement has important significance and application value.
Among the existing radiation-resistant reinforcement measures of the silicon bipolar chip, the radiation-resistant reinforcement is mainly carried out by the measures of circuit design and layout design reinforcement, and by the measures of adjusting the doping concentration of devices, changing the technological conditions of a silicon oxide layer or a dielectric layer, injecting ions into the dielectric layer (adjusting defects, impurities, interface state defects and the like in the dielectric layer), changing the structure of transistor devices and the like.
The design reinforcement can utilize the existing commercial flow sheet process line, but the reinforcement optimization of the circuit and the layout is required to be carried out aiming at each sensitive chip, the workload is high, and the reinforcement effect is limited by the commercial flow sheet process line; the process reinforcement has an ionizing radiation resistant reinforcement effect on all bipolar chips using the process, but has the following problems:
1. high cost and high risk: because a new process is introduced in the mature sheet-flowing process, the influence on the subsequent process is large, and the risk is high; meanwhile, the number of production lines of the semiconductor is large, the base number is large, and if the irradiation resistance is required to be improved, the cost is high;
2. not flexible enough: the production line is fixed, the process is almost motionless, and the irradiation resistance can not be improved after the process is started.
Therefore, there are certain difficulties in improving the resistance to ionizing radiation, both in designing the reinforcement and in reinforcing the process on the flow sheet line.
Disclosure of Invention
In order to solve the problems, the invention aims to provide an anti-ionizing radiation reinforcing method for a bipolar process chip based on dielectric layer ion implantation, which is used for identifying the sensitive position of ionizing radiation in the bipolar process chip, thinning the passivation layer of a designated circuit or area of a chip circuit, further thinning the thickness of a possible metal layer, and obtaining a device structure with improved structure so as to obviously reduce the range of ions to be implanted, so that commercial equipment can perform high-degree-of-freedom (ion type, depth and dose) ion implantation of the sensitive area of the chip circuit, and further realize the development method of the anti-ionizing radiation specific process of the chip by combining annealing repair.
The invention aims to provide an ion implantation-based bipolar process chip anti-ionization radiation reinforcement method, which comprises the following steps of:
identifying a sensitive location in the bipolar process chip to ionizing radiation to obtain a sensitive location;
thinning the passivation layer at the sensitive position of the chip circuit and/or thinning the thickness of the metal layer to obtain a structure optimization device;
ion implantation is carried out on the structure optimization device;
the annealing treatment repairs damage caused by ion implantation.
The invention provides a new solution for anti-ionizing radiation reinforcement, and discovers a sensitive area by exploring the structure of an electronic device, and further thins the passivation layer and the thickness of a possible metal layer of a specified circuit area of a chip circuit of the electronic device, so that the ion implantation range is improved, and the anti-irradiation capability of the device is obviously improved.
In an alternative embodiment, the method for obtaining the sensitive location includes:
identifying the types of transistors in a silicon-based bipolar chip with unknown circuit information, identifying the emitter, the base and the collector of each type of transistors, and identifying the interconnection relation of each transistor in the chip to obtain a circuit schematic diagram;
obtaining the transverse and longitudinal structural dimensions of each electrode part of the transistor, the passivation layer and the electrode by preparing a cross-section sample;
and carrying out circuit simulation through a circuit schematic diagram, or measuring the change of the electrical properties of different transistors in the chip before and after radiation by utilizing the micro-nano probe, so as to obtain a sensitive position.
In an alternative embodiment, the passivation layer is thinned by etching, wherein the etching process is as follows: by CF 4 /O 2 Dry etching, wherein the etching rate is controlled to be 5-10 nm/s;
the process of thinning the metal layer comprises the following steps: dry etching is adopted, and the etching gas adopts Cl 2 、BCl 3 、Ar、N 2 、CHF 3 、C 2 H 4 The etching rate is controlled to be 5-10 nm/s.
The inventor finds that the etching and thinning processes can not damage the peripheral structure, have small process difficulty and low cost, and can easily obtain the required thickness, and the like, thereby being beneficial to the subsequent ion implantation to obtain the effect of resisting the ionizing radiation.
In an alternative embodiment, the thickness of the passivation layer and the thickness of the metal layer after thinning are 300-1000 nm.
In an alternative embodiment, the process of ion implantation of the structure optimization device is as follows:
(1) According to the obtained structural size, density and material information of the structural optimization device, the ranges and distribution of different types of ions implanted in the material with different energy and dosage and the formed defects and damages are obtained by utilizing ion implantation simulation;
(2) Modeling and simulating the device according to the obtained structural size information of the structure optimization device, substituting defects and damages caused by ion implantation of different ion types, energy and dosages in the step (1), and simulating the change of the electrical properties of the device to obtain the optimal implanted ion types, energy and dosages;
(3) Ion implantation is carried out on the chip by adopting an ion implanter according to the optimal ion type, energy and dosage obtained in the step (2).
In an alternative embodiment, the ion implantation is modeled using SRIM simulation, and the change in electrical properties of the device is simulated using TCAD.
In an alternative embodiment, the ion implanter is used for ion implantation, wherein the performance index of the ion implanter is implantation energy of 10 KeV-1 MeV, and implantation dosage of 1E 11-1E 17 ions/cm 2 Injection angle: 11 deg.. By the improvement of the invention, the prior commercial ion implanter is adopted to obtain good ionization radiation resistance.
In an alternative embodiment, any of the B, P, al, F, N, si elements is implanted during the ion implantation process to perform an ion implantation process to the silicon oxide layer near the silicon-silicon oxide interface to modify the silicon oxide layer material of the silicon-based chip.
According to the invention, the silicon oxide layer material of the silicon-based chip is modified by performing ion implantation treatment to the silicon oxide layer near the silicon-silicon oxide interface, so that the defect number generated by the silicon oxide layer and the interface under radiation is reduced. The passivation layer and the thinned metal are removed at specific positions of the passivation layer, such as the upper part of G in FIG. 1, so that the effect is that the passivation layer is blocked at the position beside the passivation layer during ion implantation, ions cannot damage the devices below, and the silicon oxide material is modified at the required position to carry out reinforcement treatment.
The conventional semiconductor device ion implantation equipment is used for doping in silicon, is generally used for preparing regions such As pn junctions and EBCs (i.e. n and P regions below the EBCs in fig. 1) of PNP transistors, is not used for doping in silicon oxide, and is generally used for ion implantation of boron B, phosphorus P and arsenic As elements only, and the implantation energy, the implantation quantity and other parameters remain unchanged. The invention can use boron B and phosphorus P as implantation ions, and can also use fluorine F, nitrogen N, silicon Si and aluminum Al elements, and the treatment is carried out after the semiconductor chip is prepared by the flow sheet line, so that the pollution of the flow sheet production line caused by introducing other elements can be avoided.
In an alternative embodiment, the injection energy and range information for different ion implantations are respectively:
for B ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is from 150nm to 1.4 mu m;
for P ions: the injection energy range is 40 KeV-800 KeV, and the range is 50 nm-1 μm;
for Al ions: the injection energy ranges from 40KeV to 700KeV, and the injection range is from 60nm to 1.2 mu m;
for the F ions: the injection energy ranges from 50KeV to 600KeV, and the range is 100nm to 1.2 mu m;
for N ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is 100nm to 1.1 mu m;
for Si ions: the injection energy ranges from 50KeV to 800KeV, and the injection range is from 60nm to 1.1 mu m.
In an alternative embodiment, the annealing process is performed at a temperature of 200 ℃ to 400 ℃ for 30min to 120min. The inventor finds that under the preferable annealing temperature and annealing time, the technical effect of repairing the damage of the device due to ion implantation can be achieved, and the problems of breakage of the metal electrode of the device and the like can not be introduced.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention provides an ion implantation-based bipolar process chip anti-ionization radiation reinforcing method, which is based on transistor device structural design optimization to remarkably reduce the range of ions to be implanted, remarkably improve the anti-irradiation capability of devices, and utilize commercial ion implantation equipment to develop the specific ion implantation of a bipolar process chip designated device (sensitive) or a designated device region silicon oxide layer so as to realize the low-cost, rapid and high-degree-of-freedom development of an electronic chip anti-ionization radiation reinforcing process.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic diagram of a bipolar process lateral PNP transistor structure; wherein, epiaxial Si is an Epitaxial silicon layer, burid Si is Buried layer silicon, and Si substrate is a silicon substrate region.
FIG. 2 is a flow chart of a method for reinforcing a bipolar process chip against ionizing radiation based on ion implantation;
fig. 3 is a graph of transistor magnification results for example samples and reference samples implanted with different ions under gamma irradiation.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
When the silicon-based chip is in an ionizing radiation environment, such as the fields of aerospace, satellite, nuclear power station, radiomedicine and the like, ionizing radiation caused by gamma rays, X rays, high-energy particles, high-energy electrons and the like generates oxide positive charges (Not) (the position in the following figure 1) and interface traps (Nit) (the position in the following figure 1) on the silicon oxide layer of the silicon-based device, and the defects can influence the recombination of carriers in the semiconductor device, reduce the service life of the carriers, increase the base current of the transistor device, reduce the amplification factor and reduce the performance of the device. For chips, it is ionizing radiation that drifts the electrical parameters of the chip, or degrades, or even severely fails directly. Therefore, the anti-radiation reinforcement has important significance and application value.
In order to solve the problem, the invention provides a new method, which is mainly used for reinforcing after the silicon-based chip is prepared from the flow sheet process, is applicable to the flow sheet lines of all bipolar processes, and can be compatible with the existing flow sheet lines.
The specific anti-ionizing radiation reinforcement method is shown in fig. 2:
step S1, identifying the types of transistors in a bipolar process chip, and identifying an emitter, a base and a collector of each type of transistor; identifying the interconnection relation of each transistor in the chip to obtain a circuit schematic diagram;
obtaining the transverse and longitudinal structural dimensions of each electrode part of the transistor, the passivation layer and the electrode by preparing a cross-section sample;
and carrying out circuit simulation through a circuit schematic diagram, or measuring the change of the electrical properties of different transistors in the chip before and after radiation by utilizing the micro-nano probe, so as to obtain a sensitive position.
And S2, thinning the device structure of the passivation layer and/or the metal electrode layer aiming at the transistor device at the sensitive position to obtain the structure optimization device.
And S3, simulating the stopping range of the implanted ions in the ion implantation simulation software SRIM according to the obtained structural size, density and material information of the structural optimization device, and obtaining the range and distribution of certain type of ion implantation. The ion implantation is F, P, N, B, si, al, and internal defects and damages are simulated and checked by using simulation software SRIM.
And S4, substituting the defects and the damages formed in the material according to different ion types, implantation energy and implantation doses in the step S3 into device modeling simulation TCAD software, and simulating the electrical output change of the device after ion implantation to obtain the optimal ion implantation type, energy and dose.
And S5, carrying out ion implantation treatment on the bipolar process chip according to the optimal ion type, implantation energy and dose obtained in the step S4, and then carrying out annealing treatment to repair damage caused by ion implantation, wherein the annealing temperature range is 200-500 ℃ and the annealing time range is 30-120 min.
The injection energy and the range information when different ions are adopted for injection are respectively as follows:
for B ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is from 150nm to 1.4 mu m;
for P ions: the injection energy range is 40 KeV-800 KeV, and the range is 50 nm-1 μm;
for Al ions: the injection energy ranges from 40KeV to 700KeV, and the injection range is from 60nm to 1.2 mu m;
for the F ions: the injection energy ranges from 50KeV to 600KeV, and the range is 100nm to 1.2 mu m;
for N ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is 100nm to 1.1 mu m;
for Si ions: the injection energy ranges from 50KeV to 800KeV, and the injection range is from 60nm to 1.1 mu m.
And S6, carrying out a total dose irradiation test on the bipolar process chip subjected to the anti-ionizing radiation reinforcement treatment, and confirming the anti-ionizing radiation reinforcement effect of the bipolar process chip.
The invention provides an ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method, which is based on the confirmation of radiation sensitive positions in a chip, and the structural design of a transistor device is optimized to obviously reduce the range of ions to be implanted, so that the anti-irradiation capability of the device is obviously improved, and commercial ion implantation equipment is utilized to carry out specific ion implantation of a bipolar process chip appointed device (sensitive) or an appointed device region silicon oxide layer, thereby realizing the development of the electronic chip anti-ionizing radiation reinforcing process with low cost, rapidness and high degree of freedom.
The present invention will be described in detail with reference to specific examples.
Example 1: anti-ionizing radiation reinforcement for bipolar process lateral gate control transistor
Step S1, aiming at the bipolar process lateral gate control transistor with the simplest circuit, the lateral gate control transistor is a sensitive part.
And S2, designing the field oxide thickness of the base region position of the transistor to be 750nm, the metal electrode thickness to be 250nm, and etching the passivation layer on the surface. By CF 4 /O 2 And (3) dry etching, wherein the etching rate is controlled to be 5nm/s.
Step S3, setting corresponding material parameters, setting ion types, adjusting ion implantation energy and simulating ion implantation depth in SRIM simulation software according to field oxygen of the transistor structure with optimized structure, structural size, density and material information of the metal electrode; and simulate viewing internal defects and lesions. And setting P ion implantation energy according to the structural size of the device material, and implanting the P ion implantation energy to the silicon oxide near the interface.
And S4, constructing a transistor model in the TCAD according to parameters such as the structure size, doping and the like of the transistor with optimized structure, adding the ion implantation defect and damage into the transistor model, and simulating the change of the output parameters of the transistor along with the change of the ion implantation parameters. Optimal ion implantation type, energy and dose are obtained.
The optimal ion implantation type, energy and dose are specifically: f ion, 320KeV,1E15cm -2 . The ion implantation treatment comprises selecting ion source as F ion source, regulating voltage of ion implanter to make ion implantation energy reach 320KeV, regulating ion implantation dosage rate, and making ion implantation dosage reach 1E15cm according to implantation time -2 。
Optimum implantation energy and dose rate of B ion 240KeV,1E15 cm -2 . The ion implantation process comprises selecting ion source B as ion source, and regulating ion implantationThe voltage of the implantation machine is used to make the ion implantation energy reach 240KeV, the ion implantation dosage rate is regulated, and the implantation ion dosage reaches 1E15cm according to the implantation time -2 。
Optimal implantation energy and dose rate of P ions 530KeV,1E15 cm -2 . The ion implantation treatment comprises selecting ion source as F ion source, regulating voltage of ion implanter to make ion implantation energy reach 320KeV, regulating ion implantation dosage rate, and making ion implantation dosage reach 1E15cm according to implantation time -2 。
Optimal implantation energy and dose rate of N ions, 305KeV,5E14 cm -2 . The ion implantation treatment comprises selecting ion source as F ion source, regulating voltage of ion implanter to make ion implantation energy reach 320KeV, regulating ion implantation dosage rate, and making ion implantation dosage reach 5E14cm according to implantation time -2 。
And S5, performing ion implantation treatment on the PNP transistor with the customized structure according to the parameters such as the optimized ion implantation energy, the dosage and the like obtained in the steps S3 and S4, and annealing for 120min at the temperature of 350 ℃.
And S6, performing a total dose irradiation test on the customized PNP transistor subjected to the ion implantation and annealing treatment.
The total dose irradiation experiment is carried out on a Co60 gamma radiation source, 5 kinds of PNP transistors which are not subjected to ion implantation and PNP transistors which are respectively subjected to B, P, N, F ion implantation (the range is the same, the implanted ions are near a silicon-silicon oxide interface) on a base region field oxide layer are respectively subjected to irradiation to a certain dose under the condition that the dose rate is 1.7rad (Si)/s, a sample is taken out, the amplification factor of the transistor is measured, then the transistor is subjected to irradiation, and the irradiation-test is repeated until the total irradiation dose reaches 130krad (Si).
Fig. 3 shows the results of total dose experiments for the reference samples, respectively injected B, P, N, F ions and not injected ions, showing the relative change in transistor magnification β after the four ions were reinforced by different ion injection treatments, with the abscissa being the total dose of gamma irradiation. Under the same irradiation total dose condition (130 krad), the amplification factor of the reference sample is reduced by 60% relative to the initial value before ionization irradiation, namely the PNP transistor performance of the reference sample is reduced by 60% and the reduction is the greatest by irradiation. The amplification factor drop of the B ion implantation sample is smaller relative to the reference sample; the F ion implanted samples were at a total dose of irradiation (130 krad) with a 20% decrease in magnification relative to the initial value before irradiation, with minimal decrease, and the larger implanted samples (1E 15) were at a smaller relative decrease. The sample with F ion implantation was shown to have a 40% improvement in ionizing radiation resistance over the reference sample without ion implantation.
The radiation-resistant reinforcement method provided by the invention realizes the improvement of the radiation-resistant capacity through the ion implantation and post-treatment modes, and has the following advantages:
1. the cost is low: the invention can carry out anti-radiation reinforcement aiming at a single chip or bipolar process chips of a plurality of different manufacturers, and solves the problem that the production line process in the existing semiconductor technology is fixed, and the addition or change of new process steps can have influence on the subsequent process.
2. Flexibility/specificity: the invention can carry out irradiation-resistant reinforcement aiming at a single transistor, a module, a whole chip or a plurality of bipolar process chip integrated circuit systems in the chip, can flexibly and specifically change different reinforcement process conditions, and can realize rapid iterative optimization, thereby avoiding the problems of high cost and long time for iterative flow sheet required for changing the reinforcement process conditions.
3. Irradiation resistance: the invention can realize maximized energy implantation for the ion implantation of the device, solves the problem of an ion implanter, and increases the range of the ion implantation, thereby greatly improving the irradiation resistance of the device.
4. Ion implantation is difficult: the invention solves the problem that the ion implantation energy in the prior art cannot be injected to the wanted interface by optimizing the structure of the device.
The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the invention is not limited to the particular embodiments disclosed, but is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the invention.

Claims (10)

1. The method for reinforcing the bipolar process chip against ionizing radiation based on ion implantation is characterized by comprising the following steps of:
identifying a location in the bipolar process chip circuit that is sensitive to ionizing radiation to obtain a sensitive location;
thinning the passivation layer at the sensitive position of the chip circuit and/or thinning the thickness of the metal layer to obtain a structure optimization device;
ion implantation is carried out on the structure optimization device;
the annealing treatment repairs damage caused by ion implantation.
2. The method for ion implantation-based bipolar process chip anti-ionizing radiation reinforcement according to claim 1, wherein the method for obtaining the sensitive position comprises the following steps:
identifying the types of transistors in a bipolar process chip, identifying the emitter, the base and the collector of each type of transistor, and identifying the interconnection relation of each transistor in the chip to obtain a circuit schematic diagram;
obtaining the transverse and longitudinal structural dimensions of each electrode part of the transistor, the passivation layer and the metal electrode by preparing a cross-section sample;
and carrying out circuit simulation through a circuit schematic diagram, or measuring the change of the electrical properties of different transistors in the chip before and after radiation by utilizing the micro-nano probe, so as to obtain a sensitive position.
3. The method for reinforcing the bipolar process chip against ionizing radiation according to claim 1, wherein the passivation layer is thinned by etching, and the etching process is as follows: by CF 4 /O 2 And (3) dry etching, wherein the etching rate is controlled to be 5-10 nm/s.
The process of thinning the metal layer comprises the following steps: dry etching is adopted, and the etching gas adopts Cl 2 、BCl 3 、Ar、N 2 、CHF 3 、C 2 H 4 The etching rate is controlled to be 5-10 nm/s.
4. The method for reinforcing the bipolar process chip against ionizing radiation based on ion implantation according to claim 1, wherein the thickness of the thinned passivation layer and the thinned metal layer is 300-1000 nm.
5. The method for reinforcing a bipolar process chip against ionizing radiation based on ion implantation according to claim 1, wherein the ion implantation process of the structure optimizing device is as follows:
(1) According to the obtained structural size, density and material information of the structural optimization device, the ranges and distribution of different types of ions implanted in the material with different energy and dosage and the formed defects and damages are obtained by utilizing ion implantation simulation;
(2) Modeling and simulating the device according to the obtained structural size information of the structure optimization device, substituting defects and damages caused by ion implantation of different ion types, energy and dosages in the step (1), and simulating the change of the electrical properties of the device to obtain the optimal implanted ion types, energy and dosages;
(3) Ion implantation is carried out on the chip by adopting an ion implanter according to the optimal ion type, energy and dosage obtained in the step (2).
6. The method for reinforcing an ion implantation-based bipolar process chip against ionizing radiation according to claim 5, wherein the ion implantation is modeled and simulated by using SRIM simulation, and the change of the electrical properties of the device is simulated by using TCAD.
7. The method for reinforcing a bipolar process chip against ionizing radiation according to claim 1, wherein the ion implantation is performed by using an ion implanter with a performance index of 10 keV-1 MeV and an implantation dose of 1E 11-1E 17 ions/cm 2 Injection angle: 11 deg..
8. The method for reinforcing a bipolar process chip against ionizing radiation according to claim 1, wherein any one of B, P, al, F, N, si elements is implanted during the ion implantation process to perform ion implantation treatment near a silicon oxide layer near a silicon-silicon oxide interface, thereby modifying a silicon oxide layer material of a silicon-based chip.
9. The method for reinforcing a bipolar process chip against ionizing radiation according to claim 8, wherein the injection energy and the range information when different ion implantations are adopted are respectively as follows:
for B ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is from 150nm to 1.4 mu m;
for P ions: the injection energy range is 40 KeV-800 KeV, and the range is 50 nm-1 μm;
for Al ions: the injection energy ranges from 40KeV to 700KeV, and the injection range is from 60nm to 1.2 mu m;
for the F ions: the injection energy ranges from 50KeV to 600KeV, and the range is 100nm to 1.2 mu m;
for N ions: the injection energy ranges from 50KeV to 500KeV, and the injection range is 100nm to 1.1 mu m;
for Si ions: the injection energy ranges from 50KeV to 800KeV, and the injection range is from 60nm to 1.1 mu m.
10. The method for reinforcing the bipolar process chip against ionizing radiation according to claim 1, wherein the annealing treatment temperature is 200-500 ℃ and the annealing time is 30-120 min.
CN202310706680.8A 2023-06-14 2023-06-14 Ion implantation-based bipolar process chip anti-ionizing radiation reinforcing method Pending CN116646246A (en)

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