CN116644021A - Dual-core communication control method and device, computer equipment and dual-core chip - Google Patents
Dual-core communication control method and device, computer equipment and dual-core chip Download PDFInfo
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Abstract
The embodiment of the application provides a dual-core communication control method, a dual-core communication control device, computer equipment and a dual-core chip, wherein the method is applied to a first core, and the first core is any core in dual-core communication and comprises the following steps: sending a first data packet and a first sending count value to a second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication; receiving a first response count value sent by a second kernel; and if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel. The method provided by the embodiment of the application can set the packet loss retransmission mechanism on the basis of dual-core communication, thereby improving the stability of dual-core communication.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a dual-core communication control method, a dual-core communication control device, a computer device, and a dual-core chip.
Background
Along with the continuous development of artificial intelligence technology, the chip functions used in the field of single chip microcomputer are more and more powerful. The core in the CPU is the most important component, and the dual-core and quad-core chips are widely applied along with the higher and higher integration level of the chips.
The dual-core communication in the chip needs to pay attention to the verification during data receiving, and the data which does not pass the verification can be discarded. The chips in the double-sided chip are usually applied to large-scale projects, so that more processing items are needed, and various packet losses are possible. In application scenes such as man-machine interaction, packet loss can cause unresponsiveness or incorrect response of user operation, and the running stability and user experience of products are affected.
Disclosure of Invention
In order to solve the problem of weak stability of the existing dual-core communication, the application provides a dual-core communication control method, a device, computer equipment and a dual-core chip, which can effectively avoid the problem that packet loss in dual-core communication affects system operation.
In one aspect, a dual-core communication control method is provided, and is applied to a first core, where the first core is any core in dual-core communication, and the method includes:
sending a first data packet and a first sending count value to a second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication;
receiving a first response count value sent by a second kernel;
and if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel.
In some embodiments, before the sending the first data packet and the first sending count value to the second core, the method further includes:
establishing a data cache area of the first kernel, wherein the data cache area is used for storing a data packet array, and the number of bits of the data packet array is greater than one; the first data packet is the data packet in the first bit in the data packet array.
In some embodiments, before the sending the first data packet and the first sending count value to the second core, the method further includes:
establishing a count value array of the first kernel; each count value in the count value array corresponds to one data packet in the data packet array, and each count value is the same as the serial number of the corresponding data packet; the first sending count value is a sending count value corresponding to the first data packet.
In some embodiments, the method further comprises:
if the first sending count value is consistent with the first response count value, updating the data packet data and the count value data;
updating the data packet array, including pushing each data packet in the data packet array forward by one bit;
updating the count value array includes pushing each count value in the count value array forward by one bit.
In some embodiments, the retransmitting data to the second core comprises:
retransmitting the first data packet and the first transmission count value to the second kernel, and receiving a first response count value transmitted by the second kernel;
if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel;
and if the number of times of retransmitting the data to the second kernel is greater than a preset number of times threshold, updating the data packet array and the count value data.
In another aspect, a dual-core communication control method is provided, and the dual-core communication control method is applied to a second core, where the second core is a core in dual-core communication except for the first core, and the method includes:
receiving a first data packet and a first sending count value sent by a first kernel;
and sending a response count value to the first kernel. In some embodiments of the present application, in some embodiments,
in another aspect, a dual-core communication control device is provided, and is applied to a first core, where the first core is any core in dual-core communication, and the device includes:
the first sending module is used for sending a first data packet and a first sending count value to the second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication;
the first receiving module is used for receiving the first response count value sent by the second kernel;
and the data retransmission module is used for retransmitting data to the second kernel if the first transmission count value is inconsistent with the first response count value.
In some embodiments, the apparatus further includes a packet array construction module configured to establish a data buffer of the first core, where the data buffer is configured to store a packet array, and a number of bits of the packet array is greater than one bit; the first data packet is the data packet in the first bit in the data packet array.
In some embodiments, the apparatus further includes a count value array construction module for establishing a count value array for the first core; each count value in the count value array corresponds to one data packet in the data packet array, and each count value is the same as the serial number of the corresponding data packet; the first sending count value is a sending count value corresponding to the first data packet.
In some embodiments, the apparatus further includes an array update module configured to update the packet data and the count value data if the first transmit count value and the first reply count value agree;
updating the data packet array, including pushing each data packet in the data packet array forward by one bit;
updating the count value array includes pushing each count value in the count value array forward by one bit.
In some embodiments, the data retransmission module is specifically configured to:
retransmitting the first data packet and the first transmission count value to the second kernel, and receiving a first response count value transmitted by the second kernel;
if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel;
and if the number of times of retransmitting the data to the second kernel is greater than a preset number of times threshold, updating the data packet array and the count value data.
In another aspect, a dual-core communication control device is provided, and the dual-core communication control device is applied to a second core, where the second core is a core other than the first core in dual-core communication, and the device includes:
the second receiving module is used for receiving the first data packet and the first sending count value sent by the first kernel;
and the second sending module is used for sending the response count value to the first kernel.
In another aspect, a computer device is provided, where the computer device includes a processor and a memory, where the memory stores at least one instruction, at least one program, a code set, or an instruction set, and the processor may load and execute the at least one instruction, the at least one program, the code set, or the instruction set, to implement the dual-core communication control method provided in the embodiment of the application.
In another aspect, a computer readable storage medium is provided, where at least one instruction, at least one program, a code set, or an instruction set is stored in the readable storage medium, and a processor may load and execute the at least one instruction, the at least one program, the code set, or the instruction set, so as to implement the dual-core communication control method provided in the embodiment of the present application.
In another aspect, a computer program product or computer program is provided, the computer program title or computer program comprising computer program instructions stored in a computer readable storage medium. The processor reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the computer device to perform the dual-core communication control method of any of the above embodiments.
In another aspect, a dual-core chip is provided for implementing the dual-core communication control method according to any one of the above embodiments.
The technical scheme provided by the application has the beneficial effects that at least: the embodiment of the application provides a dual-core communication control method, a dual-core communication control device, computer equipment and a dual-core chip, wherein the method is applied to a first core, and the first core is any core in dual-core communication and comprises the following steps: sending a first data packet and a first sending count value to a second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication; receiving a first response count value sent by a second kernel; and if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel. The method provided by the embodiment of the application can set the packet loss retransmission mechanism on the basis of dual-core communication, thereby improving the stability of dual-core communication.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an implementation flow of a dual-core communication control method according to an exemplary embodiment of the present application;
FIG. 2 is a schematic flow chart of another implementation of a dual-core communication control method according to an exemplary embodiment of the present application;
FIG. 3 is a flow chart illustrating another implementation of a dual-core communication control method according to an exemplary embodiment of the present application;
FIG. 4 is a schematic flow chart of a dual-core communication control method according to another exemplary embodiment of the present application;
fig. 5 is a block diagram showing a dual-core communication control apparatus according to an exemplary embodiment of the present application;
fig. 6 is a diagram showing still another structure of a dual-core communication control apparatus according to an exemplary embodiment of the present application;
fig. 7 is a schematic structural diagram of a computer device corresponding to a dual-core communication control method according to an exemplary embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
The dual-core communication control method provided by the application can effectively avoid the problem that the packet loss in dual-core communication affects the system operation
Embodiment 1,
Fig. 1 shows a schematic implementation flow diagram of a dual-core communication control method according to an embodiment of the present application.
Referring to fig. 1, the dual-core communication control method provided by the embodiment of the present application is applied to a first core, where the first core is any core in dual-core communication, and the method may include steps 101 to 103.
Step 101: sending a first data packet and a first sending count value to a second kernel; the second kernel is a kernel of dual-core communication except the first kernel.
In some embodiments, prior to step 101, the method further comprises:
establishing a data cache area of the first kernel, wherein the data cache area is used for storing a data packet array, and the number of bits of the data packet array is greater than one; the first data packet is the data packet in the first bit in the data packet array.
Optionally, the packet array holds a maximum of 20 packets. The content and format of the data packet are not limited in this embodiment.
Establishing a count value array of the first kernel; each count value in the count value array corresponds to one data packet in the data packet array, and each count value is the same as the serial number of the corresponding data packet; the first sending count value is a sending count value corresponding to the first data packet.
Step 102: and receiving a first response count value sent by the second kernel.
In some embodiments, if the first transmission count value and the first response count value agree, updating the packet data and the count value data;
updating the data packet array, including pushing each data packet in the data packet array forward by one bit;
updating the count value array includes pushing each count value in the count value array forward by one bit.
In some embodiments, each data transmission transmits a bit 0 data packet in the array, and after completing one normal data transmission, the data packet in the array is pushed forward by one bit in sequence, so as to ensure that each transmitted data is bit 0 in the array. When 20 bits of the array have data packets and new data packets need to be cached, the operation of pushing the data packets of the array forward by one bit is performed so as to empty the last bit of the original data packets to cache the new data packets.
Specifically, the data packets in the array are sequentially pushed forward by one bit, namely the original 0 th bit data packet is emptied, the 1 st bit data packet replaces the original 0 th bit, the 2 nd bit data packet replaces the original 1 st bit, and the data packets are pushed in this way, and finally the 19 th bit data packet replaces the original 18 th bit, and the 19 th bit is emptied to buffer the new data packet.
In the method provided by the embodiment of the application, the data buffer area is established to buffer each data update, so that when a retransmission event occurs, a certain kernel or dual-kernel data update can be buffered instead of being covered by the next update. When there is no retransmission event, the buffer area performs one-time data packet buffering and one-time data packet transmission, and when the retransmission event occurs, the buffer area can buffer multiple data updates, and after the retransmission event is finished, the data of the buffer area is sequentially transmitted.
When the first core sends a data packet to the second core, an independent count value is sent in a following manner.
In order to avoid that the data packet is cleared due to retransmission or buffer is full, a structure for transmitting the count value must be newly created and stored, and an array for storing the count value structure must be correspondingly created to implement a retransmission mechanism.
In a specific example, for a first core, sending a first count value is followed when sending a data packet to a second core, and the function is to transfer information that the data packet has been sent to the second core; the first kernel also receives a second count value from the second kernel, and the first kernel immediately sends the second count value back to the second kernel as a response count value after receiving the second count value so as to respond to the second kernel.
Alternatively, the first count value is ma_ping_cnt, and the second count value is ma_ack_cnt.
When the first kernel has data to update to the buffer, the first count value is synchronously increased and bound with the current data update. When the 0 th data packet in the first kernel cache area is pushed out, the corresponding first count value is synchronously pushed out; when the bit 0 data packet is retransmitted, the corresponding first count value is also retransmitted synchronously.
In some embodiments, the first core performs an update determination at a predetermined first period, and if there is a data update, the updated data packet is stored in the buffer.
And further performing transmission judgment, and if the transmission count value transmitted by the first kernel is consistent with the response count value transmitted by the second kernel, indicating that the data packet is successfully transmitted. If the data packet is judged to be normally transmitted, the next data packet is continuously transmitted. When the normal data packet is sent, the data packet of the 0 th bit in the array is sent every time, and the count value is sent every time, so that the second kernel can conveniently answer after receiving. After the second kernel receives the count value sent by the first kernel, the second kernel sends the response value of the second kernel back to the first kernel, and the process of data interaction is completed.
After the first kernel digitizes the information input by the outside, the data which needs to be sent to the second kernel is firstly stored in a buffer area for sending until the next outside data comes. Before this, the first kernel will process the data that the kernel needs to process.
And if the sending count value is inconsistent with the response count value and the number of continuous inconsistencies reaches a preset first time number threshold, triggering a retransmission event.
Step 103: and if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel.
In some embodiments, step 103 comprises: retransmitting the first data packet and the first transmission count value to the second kernel, and receiving a first response count value transmitted by the second kernel;
if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel;
and if the number of times of retransmitting the data to the second kernel is greater than a preset number of times threshold, updating the data packet array and the count value data.
In some embodiments, if a packet loss retransmission event occurs, the operation of sequentially advancing packets is stopped because the data that needs to be retransmitted at this time has already been sent out.
In some embodiments, an array of count values for the second core is established based on the same manner to hold count value data for the second core.
In some embodiments, the case of packet loss retransmission is as follows.
The first core marks the data packet being transmitted, indicating that the data packet is the latest transmitted data packet. If the packet is lost, the packet can be retransmitted based on the mark.
Specifically, when the packet loss condition meets the condition of the retransmission event, the last unsuccessful data packet is retransmitted every second preset period. And judging whether the transmission count value and the response count value are consistent or not at intervals of a third period in the retransmission process. And if the transmission count value is detected to be consistent with the response count value, the data packet retransmission is successful. And stopping retransmitting the data packet when the retransmission times of the data packet are successful and exceed the second time threshold or the buffer area is full, and continuing to sequentially transmit the subsequent data packet.
In some embodiments, the first core has a function of interacting with the outside world, and in combination with the peripheral circuits and related sensors, interaction of touch, visual, auditory, speech recognition, etc. functions can be achieved.
Interaction between the kernel and the outside is processed at a machine level, and various input messages are digitally processed.
The dual-core communication control method provided by the embodiment of the application can set the packet loss retransmission mechanism on the basis of dual-core communication, and compared with the method for judging whether to discard data or not by only relying on the receiving check value, the retransmission mechanism can ensure that the data is retransmitted for a limited time and a limited number of times when not successfully transmitted, and improves the stability of dual-core communication.
Embodiment II,
Fig. 2 is a schematic flow chart of another implementation of the dual-core communication control method according to the embodiment of the present application.
Referring to fig. 2, an embodiment of the present application provides a dual-core communication control method, which is applied to a second core, where the second core is a core in dual-core communication except for a first core, and the method includes:
step 201: receiving a first data packet and a first sending count value sent by a first kernel;
step 202: and sending a response count value to the first kernel.
In summary, the method provided by the embodiment of the application can set a packet loss retransmission mechanism on the basis of dual-core communication, thereby improving the stability of dual-core communication.
Third embodiment,
Fig. 3 is a schematic flow chart of another implementation of the dual-core communication control method according to the embodiment of the present application.
Fig. 4 shows a schematic flow chart of still another implementation of the method according to the embodiment of the present application.
Referring to fig. 3 and fig. 4, in a specific example, the implementation procedure of the dual-core communication control method provided by the embodiment of the present application is as follows.
For the kernel A, firstly judging whether 10 milliseconds are reached, if not, judging again until 10 milliseconds are reached.
And after reaching 10 milliseconds, judging whether data is updated or not, and if the data is not updated, returning to continuously judging the time.
When a data update is detected, it is further determined whether the buffer is full. If the buffer is full, the data in the buffer is pushed forward by one bit, i.e. the first bit of data is substituted for bit 0, the 2 nd bit of data is substituted for bit 1, and so on. And updating the data, storing the updated data in the buffer, and binding an incremental sending count value. If the buffer is not full, the data is directly updated and stored in the buffer, and an incremental sending count value is bound.
When 10 milliseconds are reached, it is additionally determined whether the transmission count value is equal to the acknowledgement count value.
And if the transmission count value is equal to the response count value, the 0 th bit data packet and the transmission count value are taken out from the buffer area, and the transmission data packet and the transmission count value are transmitted to the kernel B.
If the transmission count value is not equal to the response count value and the continuous X times are not equal, a retransmission event is performed, and the data packet is retransmitted and the transmission count value is incremented. And then judging whether the retransmission times are greater than Y times, if not, continuing retransmitting the data packet and increasing the transmission count value. When the retransmission times are greater than Y times, the retransmission is canceled, the buffer data is pushed forward by one bit, and the old 0 th bit data packet and the count value are discarded. A new bit 0 data packet and a transmit count value are retrieved from the buffer.
Wherein X is the number of times of maximum continuous judgment of whether the transmission count value and the response count value are equal, Y is the maximum retransmission number, and the product of X and Y is the maximum time consumption required for retransmitting the data packet. In the human-computer interaction application scene, the smaller the product is, the least time is occupied by retransmitting data, and the user experience is not affected.
For the kernel B, firstly judging whether a data packet is received or not, and if not, continuing to judge.
If there is a data packet received, the data packet is received and the calculated value is sent incrementally. On one hand, the sending count value of the kernel A is used as the response count value of the kernel B to be sent back to the kernel A, and on the other hand, the program processes the data packet.
It should be noted that, the processes executed by the kernel a and the kernel B may be interchanged, that is, the kernel B may send data, and the kernel a may receive data, and the implementation process is the same as that described above.
In summary, the dual-core communication control method provided by the embodiment of the application can increase the packet loss retransmission mechanism based on the original dual-core communication mechanism, and perform limited-time and limited-time data retransmission when the packet loss event occurs, so that the packet loss retransmission mechanism can be increased to improve the stability of dual-core communication, and the normal transmission of the next data can not be influenced after the limited-time and limited-time retransmission event, thereby improving the stability and reliability of the system operation and improving the user experience.
Fourth embodiment,
Fig. 5 shows a schematic structural diagram of a dual-core communication control device according to an embodiment of the present application.
Referring to fig. 5, an embodiment of the present application provides a dual-core communication control device, which is applied to a first core, where the first core is any core in dual-core communication, and the device includes:
a first sending module 301, configured to send a first data packet and a first sending count value to a second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication;
a first receiving module 302, configured to receive a first response count value sent by the second kernel;
and the data resending module 302 is configured to resend data to the second core if the first sending count value and the first response count value are inconsistent.
In some embodiments, the apparatus further includes a packet array construction module configured to establish a data buffer of the first core, where the data buffer is configured to store a packet array, and a number of bits of the packet array is greater than one bit; the first data packet is the data packet in the first bit in the data packet array.
In some embodiments, the apparatus further includes a count value array construction module for establishing a count value array for the first core; each count value in the count value array corresponds to one data packet in the data packet array, and each count value is the same as the serial number of the corresponding data packet; the first sending count value is a sending count value corresponding to the first data packet.
In some embodiments, the apparatus further includes an array update module configured to update the packet data and the count value data if the first transmit count value and the first reply count value agree;
updating the data packet array, including pushing each data packet in the data packet array forward by one bit;
updating the count value array includes pushing each count value in the count value array forward by one bit.
In some embodiments, the data retransmission module is specifically configured to:
retransmitting the first data packet and the first transmission count value to the second kernel, and receiving a first response count value transmitted by the second kernel;
if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel;
and if the number of times of retransmitting the data to the second kernel is greater than a preset number of times threshold, updating the data packet array and the count value data.
In summary, the device provided by the embodiment of the application can set a packet loss retransmission mechanism on the basis of dual-core communication, thereby improving the stability of dual-core communication.
Fifth embodiment (V),
Fig. 6 shows a schematic structural diagram of a dual-core communication control device according to an embodiment of the present application.
Referring to fig. 6, an embodiment of the present application provides a dual-core communication control device, which is applied to a second core, where the second core is a core in dual-core communication except for a first core, and the device includes:
a second receiving module 401, configured to receive a first data packet and a first sending count value sent by a first kernel;
a second sending module 402, configured to send an answer count value to the first kernel.
In summary, the device provided by the embodiment of the application can set a packet loss retransmission mechanism on the basis of dual-core communication, thereby improving the stability of dual-core communication.
Embodiment six,
Fig. 7 shows a schematic structural diagram of a computer device according to an exemplary embodiment of the present application, where the computer device includes:
processor 501, which includes one or more processing cores, executes various functional applications and data processing by running software programs and modules.
The receiver 502 and the transmitter 503 may be implemented as one communication component, which may be a communication chip. Alternatively, the communication component may be implemented to include a signaling function. That is, the transmitter 503 may be used to transmit control signals to the image acquisition device and the scanning device, and the receiver 502 may be used to receive corresponding feedback instructions.
The memory 504 is connected to the processor 501 via a bus 505.
The memory 504 may be used for storing at least one instruction, and the processor 501 is configured to execute the at least one instruction to implement steps 101 to 103 in the above-described method embodiment.
It will be appreciated by those skilled in the art that fig. 7 is merely an example of a computer device and is not limiting of a computer device, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the computer device may also include a network access device, etc.
The processor 501 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 504 may be an internal storage unit of the computer device, such as a hard disk or a memory of the computer device. The memory 504 may also be an external storage device of the computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like. Further, the memory 504 may also include both internal storage units and external storage devices of the computer device. The memory 504 is used for storing the computer program as well as other programs and data required by the terminal device. The memory 504 may also be used to temporarily store data that has been output or is to be output.
Embodiment seven,
The embodiment of the application also provides a computer readable storage medium, wherein at least one instruction, at least one section of program, code set or instruction set is stored in the readable storage medium, so as to be loaded and executed by a processor to realize the dual-core communication control method.
Alternatively, the computer-readable storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), solid state disk (SSD, solid State Drives), or optical disk, etc. The random access memory may include resistive random access memory (ReRAM, resistance Random Access Memory) and dynamic random access memory (DRAM, dynamic Random Access Memory), among others.
Example eight,
The present application also provides a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computer device to execute the dual-core communication control method according to any one of the above embodiments.
Example nine,
The application also provides a dual-core chip for realizing the dual-core communication control method.
The foregoing description of the embodiments of the present application is provided for the purpose of illustration only, and does not represent the advantages or disadvantages of the implementation.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc. It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (10)
1. A dual-core communication control method, applied to a first core, where the first core is any core in dual-core communication, the method comprising:
sending a first data packet and a first sending count value to a second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication;
receiving a first response count value sent by a second kernel;
and if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel.
2. The method of claim 1, wherein prior to issuing the first data packet and the first transmit count value to the second core, the method further comprises:
establishing a data cache area of the first kernel, wherein the data cache area is used for storing a data packet array, and the number of bits of the data packet array is greater than one; the first data packet is the data packet in the first bit in the data packet array.
3. The method of claim 2, wherein prior to issuing the first data packet and the first transmit count value to the second core, the method further comprises:
establishing a count value array of the first kernel; each count value in the count value array corresponds to one data packet in the data packet array, and each count value is the same as the serial number of the corresponding data packet; the first sending count value is a sending count value corresponding to the first data packet.
4. A method according to claim 3, characterized in that the method further comprises:
if the first sending count value is consistent with the first response count value, updating the data packet data and the count value data;
updating the data packet array, including pushing each data packet in the data packet array forward by one bit;
updating the count value array includes pushing each count value in the count value array forward by one bit.
5. A method according to claim 3, wherein said retransmitting data to said second core comprises:
retransmitting the first data packet and the first transmission count value to the second kernel, and receiving a first response count value transmitted by the second kernel;
if the first sending count value is inconsistent with the first response count value, retransmitting data to the second kernel;
and if the number of times of retransmitting the data to the second kernel is greater than a preset number of times threshold, updating the data packet array and the count value data.
6. A dual-core communication control method, applied to a second core, where the second core is a core in dual-core communication except for a first core, the method comprising:
receiving a first data packet and a first sending count value sent by a first kernel;
and sending a response count value to the first kernel.
7. A dual-core communication control device, applied to a first core, the first core being any core in dual-core communication, the device comprising:
the first sending module is used for sending a first data packet and a first sending count value to the second kernel; the second kernel is a kernel except the first kernel in dual-kernel communication;
the first receiving module is used for receiving the first response count value sent by the second kernel;
and the data retransmission module is used for retransmitting data to the second kernel if the first transmission count value is inconsistent with the first response count value.
8. A computer device comprising a processor and a memory having stored therein at least one instruction, at least one program, code set, or instruction set that is loaded and executed by the processor to implement the dual-core communication control method of any of claims 1 to 6.
9. A computer-readable storage medium, wherein at least one instruction, at least one program, a set of codes, or a set of instructions is stored in the readable storage medium, and the at least one instruction, at least one program, a set of codes, or a set of instructions is loaded and executed by a processor to implement the dual-core communication control method according to any one of claims 1 to 6.
10. A dual core chip for implementing the dual core communication control method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310440113.2A CN116644021A (en) | 2023-04-21 | 2023-04-21 | Dual-core communication control method and device, computer equipment and dual-core chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310440113.2A CN116644021A (en) | 2023-04-21 | 2023-04-21 | Dual-core communication control method and device, computer equipment and dual-core chip |
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| CN116644021A true CN116644021A (en) | 2023-08-25 |
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| CN202310440113.2A Pending CN116644021A (en) | 2023-04-21 | 2023-04-21 | Dual-core communication control method and device, computer equipment and dual-core chip |
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| CN (1) | CN116644021A (en) |
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