CN116643078A - Voltage detecting circuit - Google Patents
Voltage detecting circuit Download PDFInfo
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- CN116643078A CN116643078A CN202210500624.4A CN202210500624A CN116643078A CN 116643078 A CN116643078 A CN 116643078A CN 202210500624 A CN202210500624 A CN 202210500624A CN 116643078 A CN116643078 A CN 116643078A
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- 238000001514 detection method Methods 0.000 claims abstract description 81
- 239000003990 capacitor Substances 0.000 claims abstract description 46
- 238000006243 chemical reaction Methods 0.000 claims abstract description 29
- 238000005070 sampling Methods 0.000 claims abstract description 24
- 230000003287 optical effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 17
- 239000013256 coordination polymer Substances 0.000 description 10
- 230000007704 transition Effects 0.000 description 7
- 101100364827 Prochlorococcus marinus (strain SARG / CCMP1375 / SS120) ahcY gene Proteins 0.000 description 5
- 101150081953 SAM1 gene Proteins 0.000 description 5
- 101150021948 SAM2 gene Proteins 0.000 description 5
- 101710129178 Outer plastidial membrane protein porin Proteins 0.000 description 4
- 102100037820 Voltage-dependent anion-selective channel protein 1 Human genes 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
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- Analogue/Digital Conversion (AREA)
Abstract
A voltage detection circuit applied to a panel comprises an amplifying circuit, a comparing circuit and a time sequence control circuit. The panel is provided with a plurality of sensors for optically sensing a plurality of pixels thereof to generate a plurality of voltage signals. The input end of the amplifying circuit is coupled with a voltage signal through an input capacitor and a first switch, and the other input end of the amplifying circuit is coupled with a common mode voltage. The input end of the comparison circuit is coupled with the output end of the amplifying circuit through the second switch, and the other input end of the comparison circuit is coupled with the grounding voltage through the third switch. The time sequence control circuit is coupled with the output end of the comparison circuit and is coupled with the input end of the amplifying circuit through the fourth switch. The voltage detection circuit sequentially operates in a first sampling phase and a first conversion phase of the coarse adjustment phase and a second sampling phase and a second conversion phase of the fine adjustment phase to amplify the resolution of the voltage signal twice.
Description
Technical Field
The present invention relates to a panel, and more particularly, to a voltage detection circuit applied to a panel.
Background
Referring to fig. 1 to 3, in general, an optical fingerprint sensing mechanism under the basic application of an Organic Light-Emitting Diode (OLED) panel is to drive a current flowing through a photo Diode (photo Diode) to change due to the intensity difference of Light, convert the current into a voltage pattern, accumulate the voltage level through exposure for a certain time, and then distinguish the corresponding fingerprint pattern by detecting a final voltage difference caused by the intensity of Light caused by the peaks and troughs of the fingerprint.
However, in the demodulation process, the detected voltage level is unstable due to the difference of the mismatch between the sensors and the brightness difference of the background light, which results in different leakage speeds, and the leakage time limits the voltage difference between the peaks and the troughs of the fingerprint, so that the resolution is poor.
Therefore, in order to improve the resolution of fingerprint peaks and valleys, the following two solutions are currently common:
(1) Extending the exposure time to increase the voltage difference between the peaks and valleys; and
(2) A high resolution Analog-to-Digital Converter (ADC) is built in.
However, under limited loop back data conditions, extending the exposure time may result in the disadvantage of insufficient back information loop back time or the need to increase the demodulation speed of the ADC. As for the complicated circuit with built-in high-resolution ADC, the area requirement is high, and a pair-to-pair type ADC shown in fig. 4, i.e. a high-resolution ADC corresponding to the high speed ADC (Pipeline ADC) of multiple Analog Front Ends (AFEs) is usually adopted, so that the high resolution is not easy to be achieved, or a one-to-one type ADC shown in fig. 5, i.e. a high-resolution ADC corresponding to only the low-speed ADC of one AFE (e.g. Delta-Sigma ADC architecture) is adopted, which causes the disadvantages of poor stability and digital filter arrangement. In addition, if the conventional two-Step single slope (2-Step 1-slot) ADC architecture is adopted, the circuit complexity is greatly increased because sufficient resolution is required to be achieved within a limited time.
In view of the foregoing, the foregoing problems encountered in the prior art still need to be further solved.
Disclosure of Invention
Therefore, the present invention provides a voltage detection circuit applied in a low-speed and high-resolution voltage detection environment, which has the advantages of small area, low circuit complexity, low power consumption, high resolution, and meeting the circuit requirements, so as to effectively solve the above problems encountered in the prior art.
A preferred embodiment according to the present invention is a voltage detection circuit. In this embodiment, the voltage detection circuit is applied to the panel. The panel includes a plurality of pixels and is provided with a plurality of sensors. The plurality of sensors are used for respectively carrying out optical sensing on the plurality of pixels so as to generate a plurality of voltage signals. The voltage detection circuit comprises an amplifying circuit, a comparison circuit and a time sequence control circuit. One input end of the amplifying circuit is coupled with a voltage signal through the input capacitor and the first switch, and the other input end of the amplifying circuit is coupled with a common mode voltage. One input end of the comparison circuit is coupled with the output end of the amplifying circuit through the second switch, and the other input end of the comparison circuit is coupled with the grounding voltage through the third switch. The time sequence control circuit is coupled with the output end of the comparison circuit and is coupled with the input end of the amplifying circuit through the fourth switch. The voltage detection circuit sequentially operates in a first sampling (Sample) Phase and a first Conversion (Conversion) Phase of a Coarse Phase (Coarse Phase) and a second sampling Phase and a second Conversion Phase of a Fine Phase (Fine Phase) to amplify the resolution of the voltage signal twice.
In an embodiment, when the voltage detection circuit is operated in the first sampling phase of the coarse tuning phase, the first switch and the third switch are turned on, the second switch and the fourth switch are turned off, the output terminal and the input terminal of the amplifying circuit are coupled to each other, and the two input terminals of the comparing circuit are both coupled to the ground voltage.
In an embodiment, when the voltage detection circuit is operated in the first conversion stage of the coarse adjustment phase, the second switch is turned on, the first switch, the third switch and the fourth switch are turned off, the output end of the amplifying circuit is coupled to the input end of the comparing circuit and the input capacitor, and the two input ends of the comparing circuit have a first comparison voltage and a second comparison voltage respectively.
In an embodiment, when the voltage detection circuit is operated in the second sampling phase of the fine phase adjustment, the first switch and the third switch are turned on, the second switch and the fourth switch are turned off, the output end of the amplifying circuit is coupled to the input end of the amplifying circuit through the compensation capacitor and coupled to the input end of the comparing circuit through the capacitor, and both input ends of the comparing circuit are coupled to the ground voltage.
In an embodiment, when the voltage detection circuit is operated in the second switching stage of the fine phase adjustment, the first switch and the second switch are turned on, the third switch and the fourth switch are turned off, the output end of the amplifying circuit is coupled to the input end of the amplifying circuit through the compensation capacitor, and is coupled to the input end of the comparing circuit through the capacitor, and the other input end of the comparing circuit is coupled to the other capacitor, and the timing control circuit provides the feedback voltage to the input capacitor through the digital-analog switching circuit.
In one embodiment, the timing control circuit is used as a counter to provide the digital and circuit offset to the digital-to-analog conversion circuit, and the digital-to-analog conversion circuit converts the digital and circuit offset to a feedback voltage and provides the feedback voltage to the input capacitor.
In one embodiment, the voltage detection circuit is applied in a low-speed and high-resolution voltage detection environment.
In one embodiment, the voltage detection circuit has a one-stage analog-to-digital conversion (ADC) architecture.
In one embodiment, the panel is an Organic Light Emitting Diode (OLED) panel.
In one embodiment, the voltage detection circuit is applied to optical fingerprint detection.
Compared with the prior art, the voltage detection circuit can provide a low-speed analog-to-digital conversion circuit with the effects of small area, low circuit complexity, low power consumption, high resolution, meeting circuit requirements and the like through the Two-Step single-slope (Two-Step One-slope) ADC of the variation type of the voltage detection circuit so as to effectively solve the problems encountered by the prior art.
Drawings
Fig. 1 is a schematic diagram of a fingerprint sensing circuit in the prior art.
FIG. 2 is a diagram of detecting a voltage difference caused by strong and weak light due to a wave crest and a wave trough to distinguish fingerprint types in the prior art.
Fig. 3 to 5 are schematic diagrams of different types of voltage detection circuits in the prior art.
FIG. 6 is a schematic diagram of a voltage detection circuit according to a preferred embodiment of the invention.
FIG. 7 is a timing diagram of clock signals controlling switches in the voltage detection circuit.
FIG. 8 is a flow chart of a method of operating the voltage detection circuit.
FIG. 9 is a schematic diagram of the voltage detection circuit during a first sampling phase of the coarse phase.
FIG. 10 is a schematic diagram of the voltage detection circuit when operating in the first transition phase of the coarse phase.
FIG. 11 is a schematic diagram of the voltage detection circuit in the second sampling phase of the fine phase adjustment.
FIG. 12 is a schematic diagram of the voltage detection circuit in the second switching phase of the fine phase adjustment.
FIG. 13 is a schematic diagram of a voltage detection circuit employing a variable Two-Step One-slope (Two-Step One-slope) ADC to correspond One-to-One with an analog front end AFE to improve the resolution and reduce the complexity of the circuit.
FIG. 14 is a schematic diagram of the present invention for reducing circuit complexity through coarse and fine conversion.
FIG. 15 is a schematic diagram of the invention for two-degree amplification of ADC resolution by coarse phase and fine phase.
Description of main reference numerals:
120 … switch
130 … switch
140 … diode
150 … capacitor
170 … current source
Reset
RS. column select signal
Co
N1 … node
N2 … node
VN1 … Voltage
Vn2. voltage
VREF … reference voltage
Voltage difference of DeltaV …
GD … grid driver
PX … pixel
SE 11-SEMN … sensor
IC … readout integrated circuit
AFE … analog front end
ADC … analog-to-digital converter
MUX … multiplexer
Pipeline ADC … high-speed analog-to-digital converter
1-Slope ADC … single-Slope analog-to-digital converter
6 … voltage detection circuit
AMP … amplifying circuit
CMP … comparison circuit
+ … input terminal
- … input terminal
TON … time sequence control circuit
DAC … digital-to-analog conversion circuit
SW1 to SW12 … first to twelfth switches
Cin … input capacitor
Cf … compensation capacitor
Cc … capacitor
Clk_ S, CLK _s1, clk_s2, clk_ T, CLK _t1, clk_t2, clk_ph2 … clock signals
CN … counting digit
CO … path offset
VDAC … feedback voltage
VIN … input Voltage
VCM … common mode voltage
VSSA … ground voltage
CP … coarse phase
Fine phase adjustment of FP …
SAM1 … first sampling stage
SAM2 … second sampling stage
First transition stage of CON1 …
Second transition stage of CON2 …
Vcmp+ … first comparison voltage
Vcmp- … second comparison Voltage
S10-S18 … steps
2-Step 1-Slope ADC … two-Step single-Slope analog-to-digital converter
T C1 … first time length
T C2 … second time length
Detailed Description
A preferred embodiment according to the present invention is a voltage detection circuit. In this embodiment, the voltage detection circuit is applied to the panel. The panel includes a plurality of pixels and is provided with a plurality of sensors. The plurality of sensors are used for respectively carrying out optical sensing on the plurality of pixels so as to generate a plurality of voltage signals. It should be noted that the voltage detection circuit of the present invention is applied in a low-speed and high-resolution voltage detection environment, and has the advantages of small area, low circuit complexity, low power consumption, high resolution, and meeting the circuit requirements, so as to effectively solve the various problems encountered in the prior art.
Referring to fig. 6, fig. 6 is a schematic diagram of a voltage detection circuit in this embodiment. The voltage detection circuit 6 includes an amplifying circuit AMP, a comparing circuit CMP, a timing control circuit TON, a digital-to-analog conversion circuit DAC, first to twelfth switches SW1 to SW12, an input capacitor Cin, a compensation capacitor Cf and a capacitor Cc. The first to twelfth switches SW1 to SW12 are controlled by the clock signal clk_s, the clock signal clk_t, the clock signal clk_s, the clock signal clk_t2, the clock signal clk_s, the clock signal clk_t1, the clock signal clk_s, the clock signal clk_s2, the clock signal clk_ph2, the clock signal clk_s1 and the clock signal clk_s, respectively.
The input of the amplifying circuit AMP is coupled to the input capacitor Cin and the input of the amplifying circuit AMP is coupled to the common mode voltage VCM. The output terminal of the amplifying circuit AMP is coupled to the second switch SW2. The input capacitor Cin is coupled to the voltage signal VIN (i.e. the voltage signal generated by the sensor for optically sensing the pixels of the panel) through the first switch SW 1. The input capacitor Cin is coupled to the output terminal of the digital-to-analog conversion circuit DAC through the fourth switch SW 4. One end of the fifth switch SW5 is coupled between the input capacitor Cin and the input terminal of the amplifying circuit AMP, and the other end of the fifth switch SW5 is coupled to the sixth switch SW6, the seventh switch SW7 and the ninth switch SW9, respectively. One end of the sixth switch SW6 is coupled between the input capacitor Cin and the first switch SW1, and the other end of the sixth switch SW6 is coupled to the fifth switch SW5, the seventh switch SW7 and the ninth switch SW9, respectively.
The compensation capacitor Cf is coupled between the ninth switch SW9 and the tenth switch SW 10. The tenth switch SW10 is coupled between the output terminal of the amplifying circuit AMP and the second switch SW2. The seventh switch SW7 is coupled between the output terminal of the amplifying circuit AMP and the second switch SW2. The second switch SW2 is coupled to the capacitor Cc. The capacitor Cc is coupled to the input terminal+ of the comparison circuit CMP. One end of the eighth switch SW8 is coupled to the output end of the amplifying circuit AMP and the other end of the eighth switch SW8 is coupled between the second switch SW2 and the capacitor Cc. One end of the eleventh switch SW11 is coupled to the ground voltage VSSA and the other end of the eleventh switch SW11 is coupled between the second switch SW2 and the capacitor Cc. One end of the twelfth switch SW12 is coupled to the ground voltage VSSA and the other end of the twelfth switch SW12 is coupled between the capacitor Cc and the input terminal +of the comparison circuit CMP. The input of the comparison circuit CMP is coupled to the capacitor Cc. One end of the third switch SW3 is coupled between the input terminal-of the comparison circuit CMP and the capacitor Cc and the other end of the third switch SW3 is coupled to the ground voltage VSSA. The output end of the comparison circuit CMP is coupled to the timing control circuit TON. The timing control circuit TON is coupled to an input terminal of the digital-to-analog conversion circuit DAC.
It should be noted that, as shown in fig. 7, the voltage detection circuit 6 of the present invention sequentially operates under the first sampling phase SAM1 and the first conversion phase CON1 of the coarse adjustment phase CP and the second sampling phase SAM2 and the second conversion phase CON2 of the fine adjustment phase FP to amplify the resolution of the voltage signal VIN twice.
In detail, when the voltage detection circuit 6 operates in the first sampling phase SAM1 of the coarse phase CP, the clock signals clk_s and clk_s1 are at high level, and the clock signals clk_s2, clk_ T, CLK _t1, clk_t2, clk_ph2 are all at low level. Then, when the voltage detection circuit 6 is operated in the first transition stage CON1 of the coarse phase CP, the clock signals clk_s and clk_s1 are changed from high to low, the clock signals clk_s2, clk_t2 and clk_ph2 are maintained at low, and the clock signals clk_t and clk_t1 are changed from low to high.
When the voltage detection circuit 6 operates in the second sampling phase SAM2 of the fine phase FP, the clock signals clk_ S, CLK _s2 and clk_ph2 change from low to high, the clock signals clk_s1 and clk_t2 maintain low, and the clock signals clk_t and clk_t1 change from high to low. Then, when the voltage detection circuit 6 is operated in the second transition stage CON2 of the fine phase FP, the clock signals clk_s and clk_s2 are changed from the high level to the low level, the clock signals clk_s1 and clk_t1 are maintained at the low level, the clock signals clk_t and clk_t2 are changed from the low level to the high level, and the clk_ph2 is maintained at the high level.
Referring to fig. 8, in another embodiment, the operation method of the voltage detection circuit 6 of the present invention can achieve the effect of amplifying the resolution of the voltage signal VIN twice by executing the following steps S10 to S18:
step S10: the plurality of sensors are used for respectively carrying out optical sensing on a plurality of pixels of the panel to generate a plurality of voltage signals VIN;
step S12: the voltage detection circuit 6 operates in a first sampling phase SAM1 of the coarse phase CP;
step S14: the voltage detection circuit 6 operates in a first conversion stage CON1 of the coarse phase CP;
step S16: the voltage detection circuit 6 operates in a second sampling phase SAM2 of the fine phase FP;
step S18: the voltage detection circuit 6 operates in the second conversion stage CON2 of the fine-tuning phase FP.
Next, each operation stage of the voltage detection circuit will be described. Please refer to fig. 9 to 12. FIG. 9 is a schematic diagram of the voltage detection circuit in the first sampling phase of the coarse phase; FIG. 10 is a schematic diagram of the voltage detection circuit in the first switching phase of the coarse phase; FIG. 11 is a schematic diagram of the voltage detection circuit in the second sampling phase of the fine phase adjustment; FIG. 12 is a schematic diagram of the voltage detection circuit in the second switching phase of the fine phase adjustment.
As shown in fig. 9, when the voltage detection circuit 6 is operated in the first sampling phase SAM1 of the coarse tuning phase CP, the first switch SW1, the third switch SW3, the fifth switch SW5, the seventh switch SW7, the eleventh switch SW11 and the twelfth switch SW12 are turned on, the second switch SW2, the fourth switch SW4, the sixth switch SW6, the eighth switch SW8, the ninth switch SW9 and the tenth switch SW10 are turned off, the output terminal and the input terminal of the amplifying circuit AMP are coupled to each other, and the input terminal +and the input terminal-of the comparing circuit CMP are coupled to the ground voltage VSSA. The timing control circuit TON is used as a counter for providing the digital count CN and the path offset PO to the DAC.
As shown in fig. 10, when the voltage detection circuit 6 is operated in the first switching stage CON1 of the coarse tuning phase CP, the second switch SW2 and the sixth switch SW6 are turned on, and the first switch SW1, the third switch SW3 to the fifth switch SW5, and the seventh switch SW7 to the twelfth switch SW12 are turned off, the input terminal of the amplifying circuit AMP is coupled to the output terminal of the amplifying circuit AMP through the input capacitor Cin, and the output terminal of the amplifying circuit AMP is coupled to the input terminal+ of the comparing circuit CMP through the capacitor Cc. The input terminal + and the input terminal-of the comparison circuit CMP have a first comparison voltage Vcmp + and a second comparison voltage Vcmp-, respectively. The comparison circuit CMP outputs the comparison result of the first comparison voltage vcmp+ and the second comparison voltage Vcmp-to the timing control circuit TON. The timing control circuit TON is used as a counter for providing the count number CN and the circuit offset CO to the DAC, and the DAC converts the count number CN and the circuit offset CO into the feedback voltage VDAC.
As shown in fig. 11, when the voltage detection circuit 6 is operated in the second sampling phase SAM2 of the fine tuning phase FP, the first switch SW1, the third switch SW3, the fifth switch SW5, the seventh switch SW7, the eleventh switch SW11 and the twelfth switch SW12 are turned on, and the second switch SW2, the fourth switch SW4, the sixth switch SW6, the eighth switch SW8, the ninth switch SW9 and the tenth switch SW10 are turned off, the input terminal of the amplifying circuit AMP is coupled to the output terminal of the amplifying circuit AMP through the compensation capacitor Cf, and the output terminal of the amplifying circuit AMP is coupled to the input terminal+ of the comparing circuit CMP through the capacitor Ccp. The input terminal + and the input terminal-of the comparison circuit CMP are coupled to the ground voltage VSSA. The timing control circuit TON is used as a counter for providing the digital count CN and the path offset PO to the DAC.
As shown in fig. 12, when the voltage detection circuit 6 is operated in the second switching stage CON2 of the fine tuning phase FP, the first switch SW1 and the second switch SW2 are turned on, and none of the third switch SW3 to the twelfth switch SW12 is turned on, the input terminal of the amplifying circuit AMP is coupled to the output terminal of the amplifying circuit AMP through the compensation capacitor Cf, and the output terminal of the amplifying circuit AMP is coupled to the input terminal+ of the comparing circuit CMP through the capacitor Cc. The input terminal + and the input terminal-of the comparison circuit CMP have a first comparison voltage Vcmp + and a second comparison voltage Vcmp-, respectively. The comparison circuit CMP outputs the comparison result of the first comparison voltage vcmp+ and the second comparison voltage Vcmp-to the timing control circuit TON. The timing control circuit TON is used as a counter for providing the count number CN and the circuit offset CO to the DAC, and the DAC converts the count number CN and the circuit offset CO into the feedback voltage VDAC and provides the feedback voltage VDAC to the input capacitor Cin.
Referring to fig. 13, in another embodiment, the voltage detection circuit of the present invention may employ a plurality of variable Two-Step One-slot (Two-Step One-slot) ADC corresponding to a plurality of analog front ends AFE One-to-One, wherein the Two-Step One-to-One ADC is coupled between the analog front ends AFE and the timing controller TCON is coupled to the plurality of analog front ends AFE, so as to improve the resolution of the analog-to-digital conversion and reduce the complexity of the circuit.
Referring to fig. 14 and 15, as shown in fig. 14, the voltage detection circuit of the present invention can reduce the complexity of the circuit by coarse conversion and fine conversion. As shown in fig. 15, it is assumed that the first time length of the first transition stage CON1 of the coarse phase CP is T C1 And the second time length of the second transition stage CON2 of the fine-tuning phase FP is T C2 First time length T C1 ＝T comp *2 M And a second time length T C2 ＝T comp *2 N Therefore, the voltage detection circuit of the present invention sequentially operates in the coarse tuning phase CP and the fine tuning phase FP to amplify the resolution of the analog-to-digital conversion by two degrees to m+n.
Compared with the prior art, the voltage detection circuit can provide a low-speed analog-to-digital conversion circuit with the effects of small area, low circuit complexity, low power consumption, high resolution, meeting circuit requirements and the like through the Two-Step single-slope (Two-Step One-slope) ADC of the variation type of the voltage detection circuit so as to effectively solve the problems encountered by the prior art.
Claims (10)
1. The utility model provides a voltage detection circuit, is applied to a panel, and characterized in that, this panel includes a plurality of pixels and is provided with a plurality of sensors, and this a plurality of sensors are respectively to these a plurality of pixels optical sensing in order to produce a plurality of voltage signal, and this voltage detection circuit includes:
an amplifying circuit, one input end of which is coupled with a voltage signal through an input capacitor and a first switch, and the other input end of which is coupled with a common mode voltage;
one input end of the comparison circuit is coupled with the output end of the amplifying circuit through a second switch, and the other input end of the comparison circuit is coupled with a grounding voltage through a third switch; and
the time sequence control circuit is coupled with the output end of the comparison circuit and is coupled with the input end of the amplifying circuit through a fourth switch;
the voltage detection circuit sequentially operates in a first sampling phase and a first conversion phase of a coarse adjustment phase and a second sampling phase and a second conversion phase of a fine adjustment phase to amplify the resolution of the voltage signal twice.
2. The voltage detection circuit of claim 1, wherein when the voltage detection circuit is operated in the first sampling phase of the coarse phase, the first switch and the third switch are turned on and the second switch and the fourth switch are turned off, the output terminal and the input terminal of the amplifying circuit are coupled to each other, and both input terminals of the comparing circuit are coupled to the ground voltage.
3. The voltage detection circuit of claim 2, wherein when the voltage detection circuit is operated in the first switching phase of the coarse tuning phase, the second switch is turned on and the first switch, the third switch and the fourth switch are turned off, the output terminal of the amplifying circuit is coupled to the input terminal of the comparing circuit and the input capacitor, respectively, and the two input terminals of the comparing circuit have a first comparison voltage and a second comparison voltage, respectively.
4. The voltage detection circuit of claim 3, wherein when the voltage detection circuit is operated in the second sampling phase of the fine phase, the first switch and the third switch are turned on and the second switch and the fourth switch are turned off, the output terminal of the amplifying circuit is coupled to the input terminal of the amplifying circuit through a compensation capacitor and coupled to the input terminal of the comparing circuit through a capacitor, and both input terminals of the comparing circuit are coupled to the ground voltage.
5. The voltage detection circuit of claim 4, wherein when the voltage detection circuit is operated in the second switching stage of the fine phase, the first switch and the second switch are turned on and the third switch and the fourth switch are turned off, the output terminal of the amplifying circuit is coupled to the input terminal of the amplifying circuit through a compensation capacitor and to the input terminal of the comparing circuit through a capacitor, and the other input terminal of the comparing circuit is coupled to another capacitor, the timing control circuit provides a feedback voltage to the input capacitor through a digital-to-analog conversion circuit.
6. The voltage detection circuit of claim 5, wherein the timing control circuit acts as a counter for providing a count number and a circuit offset to the digital-to-analog conversion circuit, which converts the count number and the circuit offset to the feedback voltage and provides the feedback voltage to the input capacitor.
7. The voltage detection circuit of claim 1, wherein the voltage detection circuit is used in a low-speed and high-resolution voltage detection environment.
8. The voltage detection circuit of claim 1, wherein the voltage detection circuit has a primary analog-to-digital conversion architecture.
9. The voltage detection circuit of claim 1, wherein the panel is an organic light emitting diode panel.
10. The voltage detection circuit of claim 1, wherein the voltage detection circuit is used for optical fingerprint detection.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111105662A TWI800265B (en) | 2022-02-16 | 2022-02-16 | Voltage detection circuit |
| TW111105662 | 2022-02-16 |
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| Publication Number | Publication Date |
|---|---|
| CN116643078A true CN116643078A (en) | 2023-08-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210500624.4A Pending CN116643078A (en) | 2022-02-16 | 2022-05-09 | Voltage detecting circuit |
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| CN (1) | CN116643078A (en) |
| TW (1) | TWI800265B (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9960783B2 (en) * | 2015-09-18 | 2018-05-01 | Taiwan Semiconductor Manufacturing Company Ltd. | Conditional correlated multiple sampling single slope analog-to-digital converter, and associated image sensor system and method |
| KR20210100438A (en) * | 2020-02-06 | 2021-08-17 | 삼성전자주식회사 | Analog to Digtal Converting Apparatus and Operating Method |
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- 2022-02-16 TW TW111105662A patent/TWI800265B/en active
- 2022-05-09 CN CN202210500624.4A patent/CN116643078A/en active Pending
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| TW202334923A (en) | 2023-09-01 |
| TWI800265B (en) | 2023-04-21 |
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