CN116634297A - Correlated double sampling circuit - Google Patents

Correlated double sampling circuit Download PDF

Info

Publication number
CN116634297A
CN116634297A CN202310568351.1A CN202310568351A CN116634297A CN 116634297 A CN116634297 A CN 116634297A CN 202310568351 A CN202310568351 A CN 202310568351A CN 116634297 A CN116634297 A CN 116634297A
Authority
CN
China
Prior art keywords
circuit
sampling
switch
signal
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310568351.1A
Other languages
Chinese (zh)
Inventor
刘伟峰
余志宝
高少航
温裕雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202310568351.1A priority Critical patent/CN116634297A/en
Publication of CN116634297A publication Critical patent/CN116634297A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention discloses a correlated double sampling circuit, which comprises a signal sampling circuit and a signal output circuit; the signal sampling circuit samples signals of a reset stage and an integration stage of the front-stage circuit respectively by controlling on and off of a switch, and utilizes the characteristic that charges on a capacitor cannot be suddenly changed to realize subtraction operation of the reset signal and the integration signal, so that low-frequency noise, KTC noise and FPN noise in an output signal of the front-stage circuit are eliminated; the signal output circuit outputs the effective signal after noise reduction by a circuit composed of a grounding switch, a reference voltage switch and a capacitor, and the effective signal is output by the characteristic that the charge of the capacitor cannot be suddenly changed. The circuit realizes the noise reduction function of the correlated double sampling circuit and the accurate output of effective signals after noise reduction, and improves the signal-to-noise ratio of output signals; meanwhile, the circuit can be simplified, and the power consumption, the area and the noise of the whole circuit are reduced.

Description

Correlated double sampling circuit
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a correlated double sampling circuit.
Background
A CMOS image sensor is a typical solid-state imaging sensor, which is generally composed of an image sensor cell array, a row driver, a column driver, timing control logic, an AD converter, a data bus output interface, a control interface, and the like, which are generally integrated on the same silicon chip. The working process can be generally divided into resetting, photoelectric conversion, integration and reading.
Among them, for the design of the readout circuit, various noise and irrational factors generated by the front-stage integrating amplifying circuit are important factors, which are key parameters of whether the effective signal can be correctly output and whether the output image quality can be higher, that is, the higher the signal-to-noise ratio of the output signal is, the better the output image quality is. Noise in the output signal of the front-stage integral amplifying circuit generally comprises thermal noise generated by random free thermal motion of carriers in the MOS tube or the passive resistor and 'flicker' noise (1/f noise) generated in leakage current because part of carriers of the MOS tube are randomly captured and released; the switching tube is periodically turned on and off, and the charge injection effect and the clock feedthrough effect periodically charge and discharge the integrating capacitor to generate reset noise (KTC noise); and fixed pattern noise (Fixed Pattern Noise, FPN) in which the deviations of different pixel cells are fixed for the same cell structure due to device parameter inconsistencies or deviations in the output signals caused by other factors in the production process. An analog correlated double sampling technique (Correlated Double Sampling, CDS) is generally used to reduce the effects of low frequency noise, KTC noise, and FPN noise generated by the front-stage integrating amplifying circuit on the output signal.
Such as the conventional correlated double sampling circuit shown in fig. 1. The output signal of the preceding stage integrating amplifying circuit is used as the input signal of the CDS circuit. During a reset phase, the switch S1 is closed, the switch S2 is opened, and the capacitor C1 samples a reset signal and a noise signal; during the integration phase, the switch S1 is opened, the switch S2 is closed, and the capacitor C2 samples an integrated signal and a noise signal; in the same period, the correlation of the twice sampled signals is utilized to subtract the twice sampled signal values, and the difference value is used as an output signal value, so that low-frequency noise, KTC noise and FPN noise are eliminated theoretically.
However, the conventional CDS circuit needs to perform subtraction operation on the twice sampled signal values through a subtractor, but cannot directly perform subtraction operation on the twice sampled signal values in a single signal transmission process; and the signal is sampled through two paths, which may cause certain deviation to influence the output result. In addition, the conventional CDS circuit includes an operational amplifier, and the CDS circuit can only reduce noise in the output signal of the preceding stage integrating amplifying circuit, but cannot reduce noise generated by the CDS circuit, so that power consumption, area, noise and the like are relatively increased.
Fig. 2 shows another exemplary correlated double sampling circuit, in which the switching state of the CDS circuit coincides with that of the preceding-stage integrating amplifying circuit. When the pre-stage circuit is reset, the CDS circuit closes the switch S1, opens the switch S2 and also starts to reset, and meanwhile, the sampling capacitor C1 performs first sampling to sample a reset signal output by the pre-stage circuit; when the front-stage circuit integrates, the switch S1 is opened, the switch S2 is closed, the CDS circuit performs second sampling, subtraction operation of two sampling signal values is realized according to conservation of X point charge, low-frequency noise, KTC noise and FPN noise generated by the front-stage integrating amplifying circuit contained in the output signal of the CDS circuit are eliminated, and the output voltage of the CDS circuit is as follows:
V OS the offset voltage of the CDS circuit; v (V) 1 Outputting a signal to a front-stage integrating amplifying circuit in a reset stage; v (V) 2 The signal is output by the integrating amplifying circuit at the front stage of the integrating stage.
However, the gain of the operational amplifier cannot be infinity, that is, the offset voltage cannot be 0, so that the output voltage of the CDS circuit is affected by the offset voltage, and the gain of the operational amplifier in the CDS circuit needs to be increased as much as possible, so as to improve the noise elimination capability; the CDS circuit can only reduce noise in the output signal of the front-stage integrating amplifying circuit and cannot reduce noise generated by the CDS circuit, and the CDS circuit adopts a switched capacitor circuit comprising an operational amplifier structure, so that power consumption, area, noise and the like are relatively increased, and the implementation of a readout circuit with low power consumption, low noise and a large array is not facilitated.
Further, patent document CN201910040380.4 also provides a method of outputting a difference value between a reset signal and an integrated signal using a switched capacitor circuit including an operational amplifier. However, this design requires a suitable operational amplifier structure, and because the CDS circuit cannot reduce noise generated by its own circuit, the overall power consumption, noise, and the like of the readout circuit are additionally increased.
In summary, the existing correlated double sampling circuits all need to use an operational amplifier structure, so that the problems of increasing circuit power consumption, area and noise are existed, which is not beneficial to accurate output of effective signals after noise reduction.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a correlated double sampling circuit that can subtract two signal sampling values, eliminate low frequency noise, KTC noise and FPN noise, and does not use an operational amplifier for signal transmission.
The technical problems to be solved by the invention are realized by the following technical scheme:
a correlated double sampling circuit comprises a signal sampling circuit and a signal output circuit;
the signal sampling circuit is used for collecting a reset signal or an integrated signal output by the front-stage integrating amplifying circuit and comprises a first sampling switch, a second sampling switch, a first sampling capacitor, a second sampling capacitor, a first MOS switch and a second MOS switch;
one end of the first sampling switch and one end of the second sampling switch are connected with the output end of the front-stage integrating amplifying circuit together, the other end of the first sampling switch is connected with the upper polar plate of the second sampling capacitor, and the other end of the second sampling switch is connected with the upper polar plate of the first sampling capacitor and the source electrode of the first MOS switch; the lower polar plates of the first sampling capacitor and the second sampling capacitor are commonly connected to the drain electrode of the second MOS switch; the drain electrode of the first MOS switch and the source electrode of the second MOS switch are grounded;
the signal output circuit comprises a holding capacitor, a third MOS switch and a fourth MOS switch;
the left polar plate of the holding capacitor is connected with the common end of the first sampling switch and the second sampling capacitor and the drain electrode of the third MOS switch; the right polar plate of the holding capacitor is connected with the drain electrode of the fourth MOS switch; the source electrode of the third MOS switch is grounded, and the source electrode of the fourth MOS switch is connected with a reference voltage end;
the common terminal of the holding capacitor and the fourth MOS switch is used as the output terminal of the whole correlated double sampling circuit to output voltage V OUT 。
In one embodiment of the present invention, the first sampling switch and the second sampling switch are analog switches adopting a transmission gate structure.
Another embodiment of the present invention also provides a CMOS image sensor readout circuit, which includes the correlated double sampling circuit described in the above embodiment.
The invention has the beneficial effects that:
1. the related double sampling circuit is designed to sample signals of a reset stage and an integration stage of a pre-stage circuit respectively by controlling on and off of a switch, and the subtraction operation of the reset signal and the integration signal is realized by utilizing the characteristic that charges on a capacitor cannot be suddenly changed, so that low-frequency noise, KTC noise and FPN noise in an output signal of the pre-stage circuit are eliminated; for the output of the effective signal after noise reduction, the effective signal is accurately output by utilizing the characteristic that the capacitance charge does not generate abrupt change; the circuit can realize the noise reduction function of the related double sampling circuit and the accurate output of effective signals after noise reduction without additional complex circuits such as an operational amplifier, thereby improving the signal-to-noise ratio of the output signals and further improving the quality of the output images; meanwhile, the circuit structure is simplified, and the power consumption, the area, the noise and the like of the whole circuit are reduced;
2. the transmission gate structure is used for part of the switches in the circuit, so that errors caused by charge injection effect and clock feed-through effect are reduced;
3. the circuit provided by the invention can be realized by adopting a BCD process for manufacturing Bipolar, CMOS and DMOS devices on the same chip, and the process complexity is reduced.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a conventional correlated double sampling circuit;
FIG. 2 is a schematic diagram of a typical related double sampling circuit structure in the prior art;
fig. 3 is a schematic diagram of a related double sampling circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 3, fig. 3 is a schematic diagram of a related double sampling circuit according to an embodiment of the present invention, which includes a signal sampling circuit and a signal output circuit; wherein, the liquid crystal display device comprises a liquid crystal display device,
the signal sampling circuit is used for collecting a reset signal or an integrated signal output by the front-stage integrating amplifying circuit and comprises a first sampling switch TG1, a second sampling switch TG2, a first sampling capacitor C1, a second sampling capacitor C2, a first MOS switch MN1 and a second MOS switch MN2;
one end of the first sampling switch TG1 and one end of the second sampling switch TG2 are connected with the output end of the front-stage integrating amplifying circuit together, the other end of the first sampling switch TG1 is connected with the upper polar plate of the second sampling capacitor C2, and the other end of the second sampling switch TG2 is connected with the upper polar plate of the first sampling capacitor C1 and the source electrode of the first MOS switch MN 1; the lower polar plates of the first sampling capacitor C1 and the second sampling capacitor C2 are commonly connected to the drain electrode of the second MOS switch MN2; the drain of the first MOS switch MN1 and the source of the second MOS switch MN2 are grounded;
the signal output circuit comprises a holding capacitor C3, a third MOS switch MN3 and a fourth MOS switch MN4;
the left polar plate of the holding capacitor C3 is connected with the common end of the first sampling switch TG1 and the second sampling capacitor C2 and the drain electrode of the third MOS switch MN 3; the right polar plate of the holding capacitor C3 is connected with the drain electrode of the fourth MOS switch MN4; the source electrode of the third MOS switch MN3 is grounded, and the source electrode of the fourth MOS switch MN4 is connected with a reference voltage end;
the common terminal of the holding capacitor C3 and the fourth MOS switch MN4 is used as the output terminal of the whole correlated double sampling circuit to output the voltage V OUT 。
It can be understood that in the present embodiment, the first MOS switch MN1, the second MOS switch MN2, the third MOS switch MN3, and the fourth MOS switch MN4 are all implemented by N-type MOS transistors, and the gates thereof are generally connected to the voltage VDD or the ground GND when the switches are used. The first MOS switch MN1, the second MOS switch MN2, and the third MOS switch MN3 may be referred to as a ground switch, and the fourth MOS switch MN4 may be referred to as a ground reference voltage switch.
Specifically, in fig. 3, a front-stage integrating amplifying circuit is arranged in a left frame, the front-stage integrating amplifying circuit can sequentially perform two stages of resetting and integrating in the same period, and in the resetting stage, a first sampling switch TG1 is closed, and a CDS circuit samples a reset signal output by the front-stage circuit; in the integration phase, the second sampling switch TG2 is closed, and the CDS circuit samples the integrated signal.
In this embodiment, the first sampling switch TG1 and the second sampling switch TG2 are analog switches with a transmission gate structure, so that the influence of the charge injection effect can be reduced.
Further, in the sampling process, the second MOS switch MN2 is always turned on, and the lower electrode plates of the first sampling capacitor C1 and the second sampling capacitor C2 are sampled, so that the non-linearities caused by the charge injection effect and the clock feed-through effect can be effectively reduced by the sampling mode, and the second MOS switch MN2 is turned off rapidly after the sampling process is ended.
It can be understood that the CDS circuit functions to cancel noise in the effective signal by using the correlation of the reset signal and the integrated signal of the same period. Therefore, the embodiment uses the characteristic that the capacitance charge does not suddenly change by closing the first MOS switch MN1, and the voltage of the upper plate of the first sampling capacitor C1 is integrated with the signal V s The voltage of the upper polar plate of the second sampling capacitor C2 is reduced to 0, so that the voltage of the upper polar plate of the second sampling capacitor C2 is also reduced from V r Drop by one V s I.e. the subtraction of the reset signal value and the integral signal value is realized, thereby eliminating the inclusion in the output signal of the preceding-stage integral amplifying circuitReset noise, fixed pattern noise, etc.
At the time of T0, the fourth MOS switch MN4 is closed, the right polar plate of the capacitor C3 is charged, and meanwhile, the left polar plate obtains the difference value of the reset signal and the integral signal; at time T1, the fourth MOS switch MN4 is turned off, the third MOS switch MN3 is turned on, the difference value between the reset signal and the integral signal is output by utilizing the characteristic that the capacitance charge cannot be suddenly changed, and the output of the effective signal after noise reduction is finished, namely
Q TO ＝C 3 ·[V cm -(V r -V s )]；
Q T1 ＝C 3 ·V OUT ；
Then:
V OUT ＝V cm -(V r -V s )；
wherein V is r A sampled reset signal; v (V) s Is a sampled integrated signal; v (V) cm Is the reference voltage.
Therefore, the structure can subtract the signal values sampled twice by the front-stage circuit, thereby achieving the purpose of reducing noise; meanwhile, the difference value of the two signals can be well transmitted without an additional switch capacitor circuit, so that the power consumption, noise and the like of the traditional correlated double sampling circuit are effectively reduced.
The related double sampling circuit is designed to sample signals of a reset stage and an integration stage of a pre-stage circuit respectively by controlling on and off of a switch, and the subtraction operation of the reset signal and the integration signal is realized by utilizing the characteristic that charges on a capacitor cannot be suddenly changed, so that low-frequency noise, KTC noise and FPN noise in an output signal of the pre-stage circuit are eliminated; for the output of the effective signal after noise reduction, the effective signal is accurately output by utilizing the characteristic that the capacitance charge does not generate abrupt change; the circuit can realize the noise reduction function of the related double sampling circuit and the accurate output of effective signals after noise reduction without additional complex circuits such as an operational amplifier, thereby improving the signal-to-noise ratio of the output signals and further improving the quality of the output images; meanwhile, the circuit structure is simplified, and the power consumption, the area, the noise and the like of the whole circuit are reduced.
In addition, the circuit provided by the invention can be realized by adopting a BCD process for manufacturing Bipolar, CMOS and DMOS devices on the same chip, and the process complexity is reduced.
Another embodiment of the present invention further provides a CMOS image sensor readout circuit, which includes the correlated double sampling circuit provided in the above embodiment. Therefore, the readout circuit can also improve the quality of the output image; meanwhile, the device has the advantages of simple structure, low power consumption, small area and low noise.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (3)

1. The correlated double sampling circuit is characterized by comprising a signal sampling circuit and a signal output circuit;
the signal sampling circuit is used for collecting a reset signal or an integrated signal output by the front-stage integrating amplifying circuit and comprises a first sampling switch (TG 1), a second sampling switch (TG 2), a first sampling capacitor (C1), a second sampling capacitor (C2), a first MOS switch (MN 1) and a second MOS switch (MN 2);
one end of the first sampling switch (TG 1) and one end of the second sampling switch (TG 2) are connected with the output end of the front-stage integrating amplifying circuit together, the other end of the first sampling switch (TG 1) is connected with the upper polar plate of the second sampling capacitor (C2), and the other end of the second sampling switch (TG 2) is connected with the upper polar plate of the first sampling capacitor (C1) and the source electrode of the first MOS switch (MN 1); the lower polar plates of the first sampling capacitor (C1) and the second sampling capacitor (C2) are commonly connected to the drain electrode of the second MOS switch (MN 2); the drain of the first MOS switch (MN 1) and the source of the second MOS switch (MN 2) are grounded;
the signal output circuit comprises a holding capacitor (C3), a third MOS switch (MN 3) and a fourth MOS switch (MN 4);
wherein the left polar plate of the holding capacitor (C3) is connected with the common end of the first sampling switch (TG 1) and the second sampling capacitor (C2) and the drain electrode of the third MOS switch (MN 3); the right polar plate of the holding capacitor (C3) is connected with the drain electrode of the fourth MOS switch (MN 4); the source electrode of the third MOS switch (MN 3) is grounded, and the source electrode of the fourth MOS switch (MN 4) is connected with a reference voltage end;
the common end of the holding capacitor (C3) and the fourth MOS switch (MN 4) is used as the output end of the whole correlated double sampling circuit to output voltage V OUT 。
2. The correlated double sampling circuit according to claim 1, wherein the first sampling switch (TG 1) and the second sampling switch (TG 2) are analog switches employing a transmission gate structure.
3. A CMOS image sensor readout circuit comprising the correlated double sampling circuit of any one of claims 1-2.
CN202310568351.1A 2023-05-18 2023-05-18 Correlated double sampling circuit Pending CN116634297A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310568351.1A CN116634297A (en) 2023-05-18 2023-05-18 Correlated double sampling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310568351.1A CN116634297A (en) 2023-05-18 2023-05-18 Correlated double sampling circuit

Publications (1)

Publication Number Publication Date
CN116634297A true CN116634297A (en) 2023-08-22

Family

ID=87612707

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310568351.1A Pending CN116634297A (en) 2023-05-18 2023-05-18 Correlated double sampling circuit

Country Status (1)

Country Link
CN (1) CN116634297A (en)

Similar Documents

Publication Publication Date Title
KR100660193B1 (en) Self compensating correlated double sampling circuit
US9756271B2 (en) CMOS image sensor, pixel unit and control method thereof
TW548962B (en) X-Y address type solid-state image pickup device
KR100399954B1 (en) Comparator performing analog correlated double sample for cmos image sensor
US20030010896A1 (en) Image sensing apparatus capable of outputting image by converting resolution by adding and reading out a plurality of pixels, its control method, and image sensing system
US20070029467A1 (en) Analog-to-digital converter with noise compensation in CMOS image sensor
JP2008271280A (en) Solid-state imaging apparatus, driving method of solid-state imaging apparatus, signal processing method of solid-state imaging apparatus, and imaging apparatus
JPH0927883A (en) Image read signal processing unit
KR100359770B1 (en) Active pixel circuit in CMOS image sensor
US8634008B2 (en) Imaging signal processing methods and apparatus
US6864919B2 (en) Image sensor with correlated double sampling technique using switched-capacitor technology
WO2021035605A1 (en) Dark current correlated double sampler, image sensor, and dark current compensation method
US7268815B1 (en) Differential readout of a pixel array with elimination of pixel- and column-wise fixed pattern noise
CN116634297A (en) Correlated double sampling circuit
JP2000022118A (en) Image-pickup device
WO2022262111A1 (en) Circuit for eliminating fixed pattern noise, and image sensor
Xu et al. A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18/spl mu/m CMOS technology
JP4027087B2 (en) Image sensor pixel output signal processing method and readout circuit
US7760250B2 (en) Method and apparatus for minimizing noise pickup in image sensors
CN216313265U (en) Dual-storage CMOS image sensor circuit
CN111263088A (en) High-speed sampling circuit for 8T pixel and control method thereof
CN109862289B (en) Pixel information acquisition related double-sampling reading circuit
Shih et al. An optimized CMOS pseudo-active-pixel-sensor structure for low-dark-current imager applications
TWI827488B (en) Image sensor and operation method thereof
CN215344818U (en) Image sensor for eliminating fixed pattern noise

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination