CN116632007A - Longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure - Google Patents
Longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure Download PDFInfo
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- 239000000377 silicon dioxide Substances 0.000 claims abstract description 28
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- 239000011810 insulating material Substances 0.000 claims description 9
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- 230000036961 partial effect Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
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- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims description 2
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- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 2
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
A vertical channel field effect transistor (HVTFET) integrated circuit structure of a vertical stacked heterojunction relates to the field of microelectronic technology and integrated circuits. The invention provides a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure, which is longitudinally provided with a first source region, a first semiconductor channel region, a first drain region, a silicon dioxide isolation region, a second drain region, a second semiconductor channel region and a second source region respectively, and simultaneously realizes NMOS and PMOS, and the area of the PMOS is three times that of NMOS by a special process. Both NMOS and PMOS employ heavily and lightly doped drain regions of the channel region to suppress DIBL effects. The periphery of the device surrounds the grid electrode area in a grooving mode, a grid dielectric layer is arranged between the grid electrode and the semiconductor area, and the grid electrodes and the source electrode and the drain electrode of the two devices can be independently led out. The key technical problems to be solved by the invention are as follows: a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure is provided for improving the basic integration level of a digital circuit.
Description
Technical Field
The present invention relates to microelectronics and integrated circuit technology.
Background
Moore's law has long been the core criteria in the semiconductor industry. This law is derived from the intel co-creator gordon mole, which, based on long-term observation and summary, directs the semiconductor development route for decades. According to moore's law, every 18 months the number of transistors on an integrated circuit will double and the performance will double.
Currently, the development of transistor technology evolves according to the order of Planar FET Planar field effect transistor ("FinFET fin field effect transistor (currently mainstream)", "rib FET all around gate field effect transistor"). At small dimensions, DIBL effects prevent further scaling of transistor dimensions.
To further increase the integration of basic cells in digital circuits, vertically stacked device technology is beginning to enter the field of view. Longitudinally stacking devices refers to stacking multiple transistors or other devices vertically together to form a more compact device. The vertical stack can greatly reduce the area occupied by the device and improve the integration level of the circuit compared with the conventional horizontal arrangement. In addition, the vertical stacking may also increase the connections between components in the circuit, thereby improving the speed and reliability of the circuit. Currently, the vertical stacking technology has been widely used in various types of integrated circuits, including processors, memories, sensors, and the like. For example, intel's three-dimensional transistor technology (Tri-Gate) is a vertical stack-based technology that can greatly improve the performance and power consumption efficiency of transistors. In addition, samsung, SK Hynix, and the like also employ vertical stack technology to produce high density memory devices such as 3D NAND flash and HBM (High Bandwidth Memory).
The present invention provides a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that inherits the basic structures of the HVT and NWAFET prior to the present invention [1-3] The DIBL effect is restrained by adopting a longitudinal design scheme and a combined structure of lightly doping the channel region heavily doped drift region. One PMOS and one NMOS are stacked simultaneously in the longitudinal direction, and isolation between the NMOS and PMOS is performed by silicon dioxide implantation. The electrodes of the two devices may be individually drawn to construct various digital basic cells. Meanwhile, the process in the manufacturing process also realizes that the area of the PMOS is 3 times that of the NMOS.
Reference to the literature
[1] Liao Yongbo, liping Tang Ruifeng, etc. A novel digital gate IC structure [ P ]. Chinese, invention patent,
application number: CN111048579.1.2020.
[2] Liping, tang Ruifeng, liao Yongbo, a new DRAM structure and its realization method [ P ]. Chinese, invention is special
Advantageously, application number: CN202110252584.1.2021.
[3] Liao Yongbo, liu Jinming, li Pingdeng A high-integration nanometer wall integrated circuit structure [ P ]. China, invention
Patent, application number: CN202210413345.4.2022.
Disclosure of Invention
The invention discloses a vertical channel heterojunction field effect transistor (HVTFET) integrated circuit structure with a vertical stack, as shown in fig. 1. Wherein a P-well silicon single crystal semiconductor region 101 is arranged at the lowest part of the structure, and a silicon single crystal n+ drain region 102 of the structure is formed at the upper part of the P-well silicon single crystal semiconductor region 101; above the n+ drain region 102 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region is a p+ -type channel semiconductor region 104; above the p+ channel semiconductor region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic source region 120, above the N-silicon single crystal or narrow bandgap pseudomorphic source region 120 region is an n+ silicon single crystal source region 105; above the n+ silicon single crystal source region 105 is a silicon dioxide isolation region 106; above the silicon dioxide isolation region is an n+ silicon single crystal region 107; above the n+ silicon single crystal region 107 is a p+ drain region 108, above the p+ drain region 108 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109 is an n+ channel semiconductor region 113; above the n+ channel semiconductor region 113 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 121; above the P-silicon single crystal or narrow bandgap pseudomorphic source region 121 is a p+ source region 114; the n+ drain region 102 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 101; the upper part of the n+ drain region 102, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the p+ channel semiconductor region 104, the N-silicon single crystal or narrow bandgap pseudomorphic source region 120, the n+ silicon single crystal source region 105, the silicon dioxide isolation region 106, the n+ silicon single crystal region 107, the p+ drain region 108, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109, the n+ channel semiconductor region 113, the P-silicon single crystal or narrow bandgap pseudomorphic source region 121 and the p+ source region 114 are provided with grooves with different depths, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-area 110 is higher than the lower surface of the n+ drain area 102 and lower than the upper surface of the n+ drain area 102, for guiding out the drain electrode; the lower surface of the source electrode-region 111 is higher than the lower surface of the n+ silicon single crystal source region 105 and lower than the upper surface of the n+ silicon single crystal source region 105, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 108 and lower than the upper surface of the p+ drain region 108; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 104, lower than the lower surface of n+ silicon single crystal source region 105; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 113 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; an insulated gate dielectric 118 is used to isolate the gate electrode 114 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
The second technical scheme of the invention is a heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, as shown in fig. 2. Wherein a P-well silicon single crystal semiconductor region 201 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 202 of the structure is formed at the upper part of the P-well silicon single crystal semiconductor region 201; above the N + drain region 202 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 203; above the N-drain region is a p+ -type channel semiconductor region 204; above the p+ channel semiconductor region 204 is an N-silicon single crystal or narrow bandgap pseudomorphic source region 220, above the N-silicon single crystal or narrow bandgap pseudomorphic source region 220 region is an n+ silicon single crystal source region 205; above the n+ silicon single crystal source region 205 is a silicon dioxide isolation region 206; above the silicon dioxide isolation region is an n+ silicon single crystal region 207; above the n+ silicon single crystal region 207 is a p+ drain region 208, above the p+ drain region 208 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209 is an n+ channel semiconductor region 213; above the n+ channel semiconductor region 213 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 221; above the P-silicon single crystal or narrow bandgap pseudomorphic source region 221 is a p+ source region 214; the n+ drain region 202 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 201; the upper part of the n+ drain region 202, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the p+ channel semiconductor region 204, the N-silicon single crystal or narrow bandgap pseudomorphic source region 220, the n+ silicon single crystal source region 205, the silicon dioxide isolation region 206, the n+ silicon single crystal region 207, the p+ drain region 208, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209, the n+ channel semiconductor region 213, the P-silicon single crystal or narrow bandgap pseudomorphic source region 221 and the p+ source region 214 are provided with grooves with different depths, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-region 110 is higher than the lower surface of the n+ drain region 202 and lower than the upper surface of the n+ drain region 202, for guiding out the drain electrode; the lower surface of the source electrode one region 111 is higher than the lower surface of the n+ silicon single crystal source region 205 and lower than the upper surface of the n+ silicon single crystal source region 205, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 208 and lower than the upper surface of the p+ drain region 208; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 204, lower than the lower surface of n+ silicon single crystal source region 205; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 213 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; insulated gate dielectric 118 is used to isolate gate electrode 214 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
The third technical scheme of the invention is a heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, as shown in fig. 3. Wherein a P-well silicon single crystal semiconductor region 101 is arranged at the lowest part of the structure, and a silicon single crystal n+ drain region 102 of the structure is formed at the upper part of the P-well silicon single crystal semiconductor region 101; above the n+ drain region 102 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region is a p+ -type channel semiconductor region 104; above the p+ -type channel semiconductor region 104 is an n+ -silicon single crystal source region 105; above the n+ silicon single crystal source region 105 is a silicon dioxide isolation region 106; above the silicon dioxide isolation region is an n+ silicon single crystal region 107; above the n+ silicon single crystal region 107 is a p+ drain region 108, above the p+ drain region 108 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109 is an n+ channel semiconductor region 113; above the n+ channel semiconductor region 113 is a p+ source region 114; the n+ drain region 102 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 101; the upper part of the n+ drain region 102, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the p+ channel semiconductor region 104, the n+ silicon single crystal source region 105, the silicon dioxide isolation region 106, the n+ silicon single crystal region 107, the p+ drain region 108, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109, the n+ channel semiconductor region 113 and the p+ source region 114 are provided with grooves with different depths on the side surfaces, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-area 110 is higher than the lower surface of the n+ drain area 102 and lower than the upper surface of the n+ drain area 102, for guiding out the drain electrode; the lower surface of the source electrode-region 111 is higher than the lower surface of the n+ silicon single crystal source region 105 and lower than the upper surface of the n+ silicon single crystal source region 105, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 108 and lower than the upper surface of the p+ drain region 108; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 104, lower than the lower surface of n+ silicon single crystal source region 105; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 113 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; an insulated gate dielectric 118 is used to isolate the gate electrode 114 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
The fourth technical solution of the present invention is a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure, as shown in fig. 4. Wherein a P-well silicon single crystal semiconductor region 201 is formed at the lowermost part of the structure, and a silicon single crystal n+ drain region 202 of the structure is formed at the upper part of the P-well silicon single crystal semiconductor region 201; above the N + drain region 202 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 203; above the N-drain region is a p+ -type channel semiconductor region 204; above the p+ channel semiconductor region 204 is an n+ silicon single crystal source region 205; above the n+ silicon single crystal source region 205 is a silicon dioxide isolation region 206; above the silicon dioxide isolation region is an n+ silicon single crystal region 207; above the n+ silicon single crystal region 207 is a p+ drain region 208, above the p+ drain region 208 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209 is an n+ channel semiconductor region 213; above the n+ channel semiconductor region 213 is a p+ source region 214; the n+ drain region 202 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 201; the upper part of the n+ drain region 202, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the p+ channel semiconductor region 204, the n+ silicon single crystal source region 205, the silicon dioxide isolation region 206, the n+ silicon single crystal region 207, the p+ drain region 208, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209, the n+ channel semiconductor region 213 and the p+ source region 214 are provided with grooves with different depths on the sides, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-region 110 is higher than the lower surface of the n+ drain region 202 and lower than the upper surface of the n+ drain region 202, for guiding out the drain electrode; the lower surface of the source electrode one region 111 is higher than the lower surface of the n+ silicon single crystal source region 205 and lower than the upper surface of the n+ silicon single crystal source region 205, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 208 and lower than the upper surface of the p+ drain region 208; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 204, lower than the lower surface of n+ silicon single crystal source region 205; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 213 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; insulated gate dielectric 118 is used to isolate gate electrode 214 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
Further, any one of the longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structures is characterized by a thickness of the p+ -type channel semiconductor regions 104, 213 and the n+ -type channel semiconductor regions 113, 204 that is less than 15nm.
Further, any of the vertically stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structures described herein is characterized by p+ channel semiconductor regions 104, 213 and n+ channel semiconductor regions 113, 204 having a doping concentration that is two orders of magnitude higher than N-drain region 103 and P-drain region 203.
Further, in any one of the longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structures, when the channel semiconductor region (104, 113, 204, 213), the heavily doped drain region (102, 202), the semiconductor substrate or the well (101, 201) is monocrystalline silicon, the lightly doped drain region (103, 203, 109, 209), the lightly doped source region (120, 121, 209, 221) is monocrystalline silicon, the heavily doped source region (105, 205) is monocrystalline silicon, and the heavily doped source region (114, 214) is polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb, or a combination thereof; when the channel semiconductor region (104, 113, 204, 213), the heavily doped drain region (102, 202), the semiconductor substrate or the well (101, 201) is a wide band gap single crystal semiconductor material (such as SiC single crystal or GaN single crystal), the lightly doped drain region (103, 203, 109, 209), the lightly doped source region (120, 121, 209, 221) is a pseudomorphic Si semiconductor material, the heavily doped source region (214) is a single crystal Si semiconductor material, and the heavily doped source region (105, 205) is a polycrystalline Si semiconductor material.
Further, in any one of the longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structures, the first gate electrode region 117 and the second gate electrode region 119 are disposed in a full region of one side of the semiconductor region or in a partial region of one side of the semiconductor region, as shown in fig. 5 (a); further, the first gate electrode region 117 and the second gate electrode region 119 are provided in the entire region of both sides of the semiconductor region, or in the entire region of one side and a partial region of the other side of the semiconductor region, as shown in fig. 5 (b); further, the first gate electrode region 117 and the second gate electrode region 119 are provided in all of three side surfaces of the semiconductor region, or in all of two side surfaces of the semiconductor region and a partial region with the other side surface, as shown in fig. 5 (c).
Further, in any one of the longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structures, the thickness of all layers is 1nm-100nm, and the doping concentration is 1e14cm -3 -1e20 cm -3 。
The invention adopts the principle of HVT and NWAFET structure, and adopts the heavy doped channel region, the light doped source region and the light doped drain region to form a unilateral abrupt junction, the junction depth of the depletion region in the channel region can be ignored, so that the influence of ionization acceptor charge controlled by the source region and the drain region on threshold voltage is small, thereby powerfully avoiding the problems of reduced threshold voltage, increased drain current and increased static power consumption caused by downsizing. Meanwhile, when the power supply voltage is applied, the barrier of the channel region is reduced under the influence of the power supply voltage due to the characteristic of a unilateral abrupt junction formed by the power supply voltage, so that the capability of the device for inhibiting the DIBL effect is effectively improved.
Drawings
Fig. 1 is a cross-sectional view of a vertically stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of the present invention, p-well, with a lightly doped source region.
Fig. 2 is a cross-sectional view of an n-well with a lightly doped source region of a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of the present invention.
Fig. 3 is a cross-sectional view of a p-well non-lightly doped source region of a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of the present invention.
Fig. 4 is a cross-sectional view of an n-well non-lightly doped source region of a longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of the present invention.
Fig. 5 is a top view of a vertical channel field effect transistor (HVTFET) integrated circuit structure trench gate electrode vertically stacked to form MOSFETs of different gate widths in accordance with the present invention.
Fig. 6-17 are basic process flows of example 1.
Detailed Description
Example 1:
for the integrated circuit structure of a vertical channel heterojunction field effect transistor (HVTFET) with a vertical stack proposed in the technical scheme 1 of this patent, a brief process flow for realizing the same is as follows:
as shown in fig. 6, n+, N, P +, N-, n+ regions are sequentially deposited in the P-well of the epitaxial wafer.
As shown in fig. 7, oxygen ion implantation is performed in the n+ region and then annealing is performed to form a buried silicon oxide layer.
Epitaxial growth is continued to form p+, P-, n+, P-, p+ regions, as shown in fig. 8.
As shown in fig. 9, a recess is formed by photolithography for extracting the drain of the upper PMOS.
As shown in fig. 10, a recess is formed by photolithography for extracting the source of the underlying NMOS.
As shown in fig. 11, a recess is continuously formed by photolithography for extracting the drain of the lower NMOS.
As shown in fig. 12, the grooves formed in the first three steps are filled with an insulating substance.
As shown in fig. 13, three electrode through holes are formed in the stepped groove by photolithography, and the electrode through holes are filled with metal as extraction of the corresponding electrodes.
As shown in fig. 14, grooves for subsequent gate electrodes are formed on the right by photolithography.
As shown in fig. 15, the sidewall oxidation is now performed inside the recess to form a gate oxide layer, then polysilicon, silicon dioxide and polysilicon are filled in sequence, and the silicon dioxide isolates the two portions of polysilicon gate.
As shown in fig. 16, photolithography is continued in the right half of the gate recess, and then an insulating material is filled for isolation from other devices.
As shown in fig. 17, the photoresist used in the previous step is removed to form the final device structure.
Claims (9)
1. A heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, wherein a P-well silicon single crystal semiconductor region 101 is disposed at a lowermost portion of the structure, and a silicon single crystal n+ drain region 102 of the structure is formed above the P-well silicon single crystal semiconductor region 101; above the n+ drain region 102 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region is a p+ -type channel semiconductor region 104; above the p+ channel semiconductor region 104 is an N-silicon single crystal or narrow bandgap pseudomorphic source region 120, above the N-silicon single crystal or narrow bandgap pseudomorphic source region 120 region is an n+ silicon single crystal source region 105; above the n+ silicon single crystal source region 105 is a silicon dioxide isolation region 106; above the silicon dioxide isolation region is an n+ silicon single crystal region 107; above the n+ silicon single crystal region 107 is a p+ drain region 108, above the p+ drain region 108 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109 is an n+ channel semiconductor region 113; above the n+ channel semiconductor region 113 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 121; above the P-silicon single crystal or narrow bandgap pseudomorphic source region 121 is a p+ source region 114; the n+ drain region 102 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 101; the upper part of the n+ drain region 102, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the p+ channel semiconductor region 104, the N-silicon single crystal or narrow bandgap pseudomorphic source region 120, the n+ silicon single crystal source region 105, the silicon dioxide isolation region 106, the n+ silicon single crystal region 107, the p+ drain region 108, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109, the n+ channel semiconductor region 113, the P-silicon single crystal or narrow bandgap pseudomorphic source region 121 and the p+ source region 114 are provided with grooves with different depths, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-area 110 is higher than the lower surface of the n+ drain area 102 and lower than the upper surface of the n+ drain area 102, for guiding out the drain electrode; the lower surface of the source electrode-region 111 is higher than the lower surface of the n+ silicon single crystal source region 105 and lower than the upper surface of the n+ silicon single crystal source region 105, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 108 and lower than the upper surface of the p+ drain region 108; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 104, lower than the lower surface of n+ silicon single crystal source region 105; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 113 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; an insulated gate dielectric 118 is used to isolate the gate electrode 114 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
2. A heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, wherein a P-well silicon single crystal semiconductor region 201 is disposed at a lowermost portion of the structure, and a silicon single crystal n+ drain region 202 of the structure is formed above the P-well silicon single crystal semiconductor region 201; above the N + drain region 202 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 203; above the N-drain region is a p+ -type channel semiconductor region 204; above the p+ channel semiconductor region 204 is an N-silicon single crystal or narrow bandgap pseudomorphic source region 220, above the N-silicon single crystal or narrow bandgap pseudomorphic source region 220 region is an n+ silicon single crystal source region 205; above the n+ silicon single crystal source region 205 is a silicon dioxide isolation region 206; above the silicon dioxide isolation region is an n+ silicon single crystal region 207; above the n+ silicon single crystal region 207 is a p+ drain region 208, above the p+ drain region 208 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209 is an n+ channel semiconductor region 213; above the n+ channel semiconductor region 213 is a P-silicon single crystal or narrow bandgap pseudomorphic source region 221; above the P-silicon single crystal or narrow bandgap pseudomorphic source region 221 is a p+ source region 214; the n+ drain region 202 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 201; the upper part of the n+ drain region 202, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the p+ channel semiconductor region 204, the N-silicon single crystal or narrow bandgap pseudomorphic source region 220, the n+ silicon single crystal source region 205, the silicon dioxide isolation region 206, the n+ silicon single crystal region 207, the p+ drain region 208, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209, the n+ channel semiconductor region 213, the P-silicon single crystal or narrow bandgap pseudomorphic source region 221 and the p+ source region 214 are provided with grooves with different depths, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-region 110 is higher than the lower surface of the n+ drain region 202 and lower than the upper surface of the n+ drain region 202, for guiding out the drain electrode; the lower surface of the source electrode one region 111 is higher than the lower surface of the n+ silicon single crystal source region 205 and lower than the upper surface of the n+ silicon single crystal source region 205, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 208 and lower than the upper surface of the p+ drain region 208; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 204, lower than the lower surface of n+ silicon single crystal source region 205; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 213 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; insulated gate dielectric 118 is used to isolate gate electrode 214 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
3. A heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, wherein a P-well silicon single crystal semiconductor region 101 is disposed at a lowermost portion of the structure, and a silicon single crystal n+ drain region 102 of the structure is formed above the P-well silicon single crystal semiconductor region 101; above the n+ drain region 102 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 103; above the N-drain region is a p+ -type channel semiconductor region 104; above the p+ -type channel semiconductor region 104 is an n+ -silicon single crystal source region 105; above the n+ silicon single crystal source region 105 is a silicon dioxide isolation region 106; above the silicon dioxide isolation region is an n+ silicon single crystal region 107; above the n+ silicon single crystal region 107 is a p+ drain region 108, above the p+ drain region 108 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109 is an n+ channel semiconductor region 113; above the n+ channel semiconductor region 113 is a p+ source region 114; the n+ drain region 102 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 101; the upper part of the n+ drain region 102, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the p+ channel semiconductor region 104, the n+ silicon single crystal source region 105, the silicon dioxide isolation region 106, the n+ silicon single crystal region 107, the p+ drain region 108, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109, the n+ channel semiconductor region 113 and the p+ source region 114 are provided with grooves with different depths on the side surfaces, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-area 110 is higher than the lower surface of the n+ drain area 102 and lower than the upper surface of the n+ drain area 102, for guiding out the drain electrode; the lower surface of the source electrode-region 111 is higher than the lower surface of the n+ silicon single crystal source region 105 and lower than the upper surface of the n+ silicon single crystal source region 105, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 108 and lower than the upper surface of the p+ drain region 108; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 103, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 104, lower than the lower surface of n+ silicon single crystal source region 105; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 113 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 109; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; an insulated gate dielectric 118 is used to isolate the gate electrode 114 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
4. A heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure that is vertically stacked, wherein a P-well silicon single crystal semiconductor region 201 is disposed at a lowermost portion of the structure, and a silicon single crystal n+ drain region 202 of the structure is formed above the P-well silicon single crystal semiconductor region 201; above the N + drain region 202 is an N-silicon single crystal or narrow bandgap pseudomorphic drain region 203; above the N-drain region is a p+ -type channel semiconductor region 204; above the p+ channel semiconductor region 204 is an n+ silicon single crystal source region 205; above the n+ silicon single crystal source region 205 is a silicon dioxide isolation region 206; above the silicon dioxide isolation region is an n+ silicon single crystal region 207; above the n+ silicon single crystal region 207 is a p+ drain region 208, above the p+ drain region 208 is a P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; above the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209 is an n+ channel semiconductor region 213; above the n+ channel semiconductor region 213 is a p+ source region 214; the n+ drain region 202 includes an upper portion and a lower portion wider than the upper portion, the lower surface and sides of the lower portion being surrounded by the P-well region 201; the upper part of the n+ drain region 202, the N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the p+ channel semiconductor region 204, the n+ silicon single crystal source region 205, the silicon dioxide isolation region 206, the n+ silicon single crystal region 207, the p+ drain region 208, the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209, the n+ channel semiconductor region 213 and the p+ source region 214 are provided with grooves with different depths on the sides, and the grooves are used for leading out source-drain electrodes and gates; the lower surface of the drain electrode-region 110 is higher than the lower surface of the n+ drain region 202 and lower than the upper surface of the n+ drain region 202, for guiding out the drain electrode; the lower surface of the source electrode one region 111 is higher than the lower surface of the n+ silicon single crystal source region 205 and lower than the upper surface of the n+ silicon single crystal source region 205, for extracting the source electrode; the lower surface of the drain electrode two region 112 is higher than the lower surface of the p+ drain region 208 and lower than the upper surface of the p+ drain region 208; the lower surface of gate electrode one region 117 is lower than the upper surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, higher than the lower surface of N-silicon single crystal or narrow bandgap pseudomorphic drain region 203, the upper surface of gate electrode one region 117 is higher than the upper surface of p+ channel semiconductor region 204, lower than the lower surface of n+ silicon single crystal source region 205; the lower surface of the gate electrode two region 119 is lower than the lower surface of the n+ channel semiconductor region 213 and higher than the upper surface of the P-silicon single crystal or narrow bandgap pseudomorphic drain region 209; the first gate electrode region 117 and the second gate electrode region 119 are isolated by the gate electrode silicon oxide isolation region 116; the first gate electrode region 117 and the second gate electrode region 119 are comprised of heavily doped poly or refractory metal silicide or a combination thereof; insulated gate dielectric 118 is used to isolate gate electrode 214 from other semiconductor regions. The insulating material 115 isolates the first drain electrode region 110, the first source electrode region 111, the second drain electrode region 112, the first gate electrode region 117, and the second gate electrode region 119 from each other and from the semiconductor functional region.
5. The longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of any of claims 1-4, wherein the thickness of the p+ -type channel semiconductor regions 104, 213 and the n+ -type channel semiconductor regions 113, 204 is less than 15nm.
6. The longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of any of claims 1-4, wherein the doping concentration of the p+ -type channel semiconductor regions 104, 213 and the n+ -type channel semiconductor regions 113, 204 is two orders of magnitude higher than the N-drain region 103 and the P-drain region 203.
7. The vertically stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of any of claims 1-6, wherein when the channel semiconductor region (104, 113, 204, 213), the heavily doped drain region (102, 202), the semiconductor substrate or well (101, 201) is monocrystalline silicon, the lightly doped drain region (103, 203, 109, 209), the lightly doped source region (120, 121, 209, 221) is monocrystalline silicon, the heavily doped source region (105, 205) is monocrystalline silicon, the heavily doped source region (114, 214) is polycrystalline Ge, polycrystalline SiGe, polycrystalline TWS (mercury cadmium telluride), polycrystalline InP, polycrystalline InSb, or a combination thereof; when the channel semiconductor region (104, 113, 204, 213), the heavily doped drain region (102, 202), the semiconductor substrate or the well (101, 201) is a wide band gap single crystal semiconductor material (such as SiC single crystal or GaN single crystal), the lightly doped drain region (103, 203, 109, 209), the lightly doped source region (120, 121, 209, 221) is a pseudomorphic Si semiconductor material, the heavily doped source region (214) is a single crystal Si semiconductor material, and the heavily doped source region (105, 205) is a polycrystalline Si semiconductor material.
8. The longitudinally stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of any of claims 1-6, wherein the gate electrode one region 117 and the gate electrode two region 119 are disposed in a full region of one side of the semiconductor region, or a partial region of one side of the semiconductor region, as shown in fig. 5 (a); further, the first gate electrode region 117 and the second gate electrode region 119 are provided in the entire region of both sides of the semiconductor region, or in the entire region of one side and a partial region of the other side of the semiconductor region, as shown in fig. 5 (b); further, the first gate electrode region 117 and the second gate electrode region 119 are provided in all of three side surfaces of the semiconductor region, or in all of two side surfaces of the semiconductor region and a partial region with the other side surface, as shown in fig. 5 (c).
9. The vertically stacked heterojunction vertical channel field effect transistor (HVTFET) integrated circuit structure of any of claims 1-6, wherein all layers have a thickness of 1nm to 100nm and a doping concentration of 1e14cm -3 -1e20 cm -3 。
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