CN116632001A

CN116632001A - Semiconductor device and design assisting device for semiconductor device

Info

Publication number: CN116632001A
Application number: CN202310904287.XA
Authority: CN
Inventors: 伊藤真浩; 熊谷裕弘
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2023-07-24
Filing date: 2023-07-24
Publication date: 2023-08-22
Anticipated expiration: 2043-07-24
Also published as: CN116632001B

Abstract

The application discloses a semiconductor device and a design auxiliary device of the semiconductor device, which belong to the technical field of semiconductors, and the semiconductor device comprises: a MOM capacitor including a plurality of first electrodes and a plurality of second electrodes, the first electrodes and the second electrodes being alternately arranged in a first direction, the first electrodes or the second electrodes being stacked in a second direction; a first shielding part located at one side of the MOM capacitor in a second direction, and electrically insulated from a region between the MOM capacitor and the first shielding part; and a second shielding part located at the other side of the MOM capacitor in a second direction, and electrically insulated from the MOM capacitor in a region between the second shielding part and the MOM capacitor. The semiconductor device and the design auxiliary device of the semiconductor device can improve the freedom degree of circuit design and reduce the volume of the semiconductor device.

Description

Semiconductor device and design assisting device for semiconductor device

Technical Field

The present application relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a design assisting apparatus for the semiconductor device.

Background

Capacitors are important building blocks in integrated circuits and are widely used in memory, microwave, radio frequency or smart card chips. In a semiconductor device, a metal-oxide-metal (MOM) capacitor has an electrode group in which a plurality of electrodes face each other, and a pair of shield portions provided so as to face each other with a MOM capacitor interposed therebetween. In the semiconductor device, each shielding portion is connected to the ground potential, and the MOM capacitor is surrounded by the shielding portion, so that noise received by the MOM capacitor from the peripheral signal line can be suppressed. But the shielding portions need to be connected to each other, increasing the layout area.

Disclosure of Invention

The application aims to provide a semiconductor device and a design auxiliary device of the semiconductor device, which can improve the freedom of circuit design, realize the miniaturization of the semiconductor device and improve the efficiency of design operation.

In order to solve the technical problems, the application is realized by the following technical scheme:

the present application provides a semiconductor device including:

a MOM capacitor including a plurality of first electrodes and a plurality of second electrodes, the first electrodes and the second electrodes being alternately arranged in a first direction, the first electrodes or the second electrodes being stacked in a second direction, wherein the first direction and the second direction are perpendicular;

a first shielding part located at one side of the MOM capacitor in a second direction, and electrically insulated from a region between the MOM capacitor and the first shielding part; and

a second shielding part is positioned at the other side of the MOM capacitor in a second direction, and the second shielding part is electrically insulated from the region between the MOM capacitor.

In one embodiment of the present application, the first shielding portion and the second shielding portion are connected to ground terminals having different electric potentials.

In an embodiment of the present application, the ground terminal includes a first ground terminal and a second ground terminal, and the first ground terminal and the second ground terminal are different in potential.

In an embodiment of the present application, the first shielding portion is connected to the first ground terminal or the second ground terminal, and the second shielding portion is connected to the second ground terminal or the first ground terminal.

In an embodiment of the application, the first electrode has at least one first main line.

In an embodiment of the application, the second electrode has at least one second main line, and the second main line and the first main line are alternately arranged in the first direction.

In an embodiment of the present application, a wiring space is provided on both sides of the MOM capacitor in the first direction, and the first shielding part and the second shielding part are electrically insulated in the wiring space.

The application also provides a design assisting device of the semiconductor device, which is used for the semiconductor device and comprises:

a memory unit configured to store a plurality of symbols constituting connection states of a plurality of elements in the semiconductor device, the symbols including four-terminal connection symbols indicating connection states of the first electrode, the second electrode, the first shielding portion, and the second shielding portion; and

a circuit diagram design assisting unit for calling the symbol stored in the memory unit to design a circuit diagram of the semiconductor device.

In an embodiment of the present application, the design assistance device further includes:

a layout design assisting unit configured to assist design of a layout of the semiconductor device; and

and a verification unit for comparing the connection information between the elements in the circuit diagram data with the connection information between the elements in the layout data to verify whether the connection information is matched.

In one embodiment of the present application, connection information between each element in the circuit diagram data and connection information between each element in the layout data are stored in the storage unit.

As described above, the present application provides a semiconductor device and a design support device for a semiconductor device, which can reduce the number of connections of wires and the area of a wire space in the semiconductor device, and can miniaturize the semiconductor device. The degree of freedom of wiring of each terminal of the semiconductor device can be improved, wiring requirements of different circuits can be satisfied, and the degree of freedom of design of the semiconductor device related to the wiring can be improved. The error output related to the connection information in LVS verification can be reduced, and the efficiency of design operation is improved.

Of course, it is not necessary for any one product to practice the application to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an electronic device circuit of a semiconductor device according to an embodiment of the application.

Fig. 2 is a cross-sectional view of a four-terminal semiconductor device having MOM capacitors in accordance with an embodiment of the present application.

Fig. 3 is a top view of the semiconductor device shown in fig. 2.

Part (a) in fig. 4 is a schematic diagram of a connection relationship between the first shielding portion and the second shielding portion and the ground terminal, and part (b) in fig. 4 is a schematic diagram of another connection relationship between the first shielding portion and the second shielding portion and the ground terminal.

Fig. 5 is a schematic structural diagram of a hardware structure of the design assistance device according to an embodiment of the application.

Fig. 6 is a functional block diagram of one functional example of the design assistance device in an embodiment of the present application.

Fig. 7 is a schematic diagram of parasitic capacitance of the MOM capacitor according to an embodiment of the present application when the first shielding portion and the second shielding portion are metal-bonded and then connected to the ground terminal.

Fig. 8 is a schematic diagram of connection symbols when the first shielding part and the second shielding part of the MOM capacitor are connected to the ground terminal after metal bonding in an embodiment of the application.

Fig. 9 is a schematic diagram of parasitic capacitance when the first shielding portion and the second shielding portion of the MOM capacitor are connected to different ground terminals according to an embodiment of the present application.

Fig. 10 is a schematic diagram of connection symbols when the first shielding portion and the second shielding portion of the MOM capacitor are connected to different ground terminals according to an embodiment of the present application.

FIG. 11 is a flow chart illustrating a layout ratio schematic verification process according to an embodiment of the application.

Fig. 12 is a cross-sectional view of a three-terminal semiconductor device in the related art.

Reference numerals illustrate:

1. a semiconductor device; 2. MOM capacitance; 3. a first electrode; 4. a second electrode; 5. a first shielding part; 6. a second shielding part; 8. an electronic device circuit; 10. designing an auxiliary device; 11. a CPU; 12. an auxiliary storage device; 13. a main storage device; 14. a communication interface; 15. an input unit; 16. a display unit; 18. a bus; 31. a first main line; 41. a second main line; 101. a storage unit; 102a, a circuit diagram design auxiliary unit; 102b, a layout design auxiliary unit; 103. a verification unit; 103a, netlist extraction part; 103b, a comparison part; GND1, a first ground terminal; GND2, a second ground terminal; LD, layout data; s, wiring space; SD, circuit diagram data; sym, symbol data; v1, a first supply voltage terminal; v2, a second supply voltage terminal; 1', a three-terminal semiconductor device; 2', a first MOM capacitance; 3', a electrodes; 4', B electrodes; 5', three terminal first shield; 6', a three terminal second shield; s', first wiring space.

Detailed Description

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Referring to fig. 1, in an embodiment of the present application, a schematic diagram of an electronic device circuit having a semiconductor device according to the present application is provided. The electronic device circuit 8 includes a first supply voltage terminal V1, a second supply voltage terminal V2, a first ground terminal GND1, a second ground terminal GND2, and the semiconductor device 1, wherein the first supply voltage terminal V1 and the second supply voltage terminal V2 are connected to supply voltages of different values, and the first ground terminal GND1 and the second ground terminal GND2 are connected to different ground potentials. The electronic device circuit 8 is a device in which a single-function semiconductor device such as a diode, a transistor, a resistor, or a capacitor is integrated into one chip. In the present embodiment, the semiconductor apparatus 1 in the electronic device circuit 8 includes, for example, MOM capacitance.

Referring to fig. 2, in an embodiment of the present application, fig. 2 is a cross-sectional view of a semiconductor device 1, for example, a four-terminal semiconductor device with MOM capacitor. The direction in which the first electrodes 3 and the second electrodes 4 are alternately arranged is referred to as a first direction X, and the direction perpendicular to the first direction X is referred to as a second direction Y. The cross section shown in fig. 2 is continuously formed within a predetermined range in the depth direction perpendicular to the first direction X and the second direction Y, which is not described in detail in the present application.

Referring to fig. 2 to 3, in an embodiment of the present application, fig. 3 is a top view of the semiconductor device shown in fig. 2. The semiconductor device 1 includes a MOM capacitor 2, a first shielding portion 5, and a second shielding portion 6, wherein the MOM capacitor 2 is a capacitor element using a coupling capacitance between wirings, the MOM capacitor 2 includes a first electrode 3 and a second electrode 4, and the first electrode 3 and the second electrode 4 are alternately arranged. The first shielding portion 5 is provided in the stacking direction of the semiconductor device 1, that is, in the second direction Y, the first shielding portion 5 is provided on one side of the first electrode 3 and the second electrode 4, and the second shielding portion 6 is provided on the other side of the first electrode 3 and the second electrode 4 in the second direction Y. That is, in the second direction Y, the first shielding part 5 and the second shielding part 6 are disposed at both sides of the MOM capacitor 2, and the first shielding part 5 and the second shielding part 6 are disposed to be electrically insulated in a region between both sides of the MOM capacitor 2.

Referring to fig. 2 to 3, in an embodiment of the application, in the MOM capacitor 2, the first electrode 3 has more than one first main line 31, and the second electrode 4 also has more than one second main line 41. The one or more first main lines 31 and the one or more second main lines 41 are alternately arranged in the predetermined first direction X. The one or more first main lines 31 and the second main lines 41 are disposed adjacent to each other along a line segment l-l' connecting the first electrode 3 and the second electrode 4. By the structure provided by the present application, a coupling capacitance (parasitic capacitance) is generated between the first main line 31 and the second main line 41.

Referring to fig. 2 to 3, in an embodiment of the present application, in a second direction Y perpendicular to the first direction X, a first shielding portion 5 is disposed on one side of the MOM capacitor 2 so as to act with a second shielding portion 6, and the MOM capacitor 2 is disposed between the first shielding portion 5 and the second shielding portion 6. The first shielding portion 5 is covered on the MOM capacitor 2, and can suppress a coupling capacitance generated between a signal line (not shown) disposed near the MOM capacitor 2 and the MOM capacitor 2 to suppress noise received by the MOM capacitor 2 from the signal line. And the first shielding part 5 can suppress a coupling capacitance generated between the signal line of the layer wiring provided above the first shielding part 5 and the MOM capacitance 2, thereby suppressing noise received by the MOM capacitance 2 from the signal line.

Referring to fig. 2 to 3, in an embodiment of the application, the second shielding portion 6 is disposed on a side of the MOM capacitor 2 away from the first shielding portion 5 in the second direction Y. The second shielding portion 6 is provided so as to cover the MOM capacitor 2, and suppresses a coupling capacitance generated between a signal line (not shown) disposed near the MOM capacitor 2 and the MOM capacitor 2, thereby suppressing noise received by the MOM capacitor 2 from the signal line. In addition, the second shielding portion 6 can suppress coupling electricity generated between the signal line of the layer wiring provided below the first shielding portion 5 and the MOM capacitor 2, and thus noise received by the MOM capacitor 2 from the signal line can be suppressed. At the same time, in the vertical direction in which the first electrodes 3 and the second electrodes 4 are alternately arranged, the space for the metal connection of the first shielding portion 5 and the second shielding portion 6 can be reduced, and the effect of achieving miniaturization can be achieved.

Referring to fig. 12, in another embodiment of the present application, fig. 12 is a cross-sectional view of a three-terminal semiconductor device including a three-terminal connection symbol having MOM capacitance, for example. In the third direction Y, the three-terminal semiconductor device 1 'is metal-bonded to the three-terminal semiconductor device 1' in the first wiring space S 'around the first MOM capacitor 2'. That is, the three-terminal first shielding portion 5 'and the three-terminal second shielding portion 6' are at the same potential, and can be electrically regarded as one structure. Thus, the three-terminal semiconductor device 1' is a semiconductor device including three terminals, i.e., the a electrode 3', the B electrode 4', the three-terminal first shield portion 5', and the three-terminal second shield portion 6 '.

As shown in fig. 2, in another embodiment of the present application, the first shielding portion 5 and the second shielding portion 6 are not metal-bonded in the second direction Y in the wiring space S around the MOM capacitor 2, so that the number of connections of the wirings and the area of the wiring space S in the semiconductor device 1 can be reduced, and the semiconductor device 1 can be miniaturized.

Referring to fig. 2 to 4, in the four-terminal semiconductor device 1 according to an embodiment of the present application, the first shielding portion 5 and the second shielding portion 6 may have different terminals. Fig. 4 is a schematic diagram showing a connection relationship between the first shield part 5 and the second shield part 6 of the semiconductor device according to the present application and different ground terminals. In the example of parts (a) and (b) in fig. 4, the first shield part 5 and the second shield part 6 are connected to different ground terminals, respectively, i.e., the first shield part 5 and the second shield part 6 are two terminals.

Referring to fig. 4, in an embodiment of the present application, in part (a) of fig. 4, a first shielding part 5 is connected to a first ground terminal GND1 having a predetermined potential, a second shielding part 6 is connected to a second ground terminal GND2, and the second ground terminal GND2 and the first ground terminal GND1 have different potentials. In another embodiment of the present application, as in (b) of fig. 4, the first shield part 5 is connected to the second ground terminal GND2 having a prescribed potential, the second shield part 6 is connected to the first ground terminal GND1, and the first ground terminal GND1 and the second ground terminal GND2 have different potentials. In the four-terminal semiconductor device 1 according to the present application, the first shielding portion 5 and the second shielding portion 6 are not metal-bonded to each other in the second direction Y, that is, the first shielding portion 5 and the second shielding portion 6 are provided in an insulating manner. Thus, the first shielding portion 5 and the second shielding portion 6 have terminals independent of each other, and are connected to the ground terminals having different electric potentials, respectively, so that the degree of freedom of wiring of each terminal of the semiconductor device can be increased, the wiring requirements of different circuits can be satisfied, and the degree of freedom of design related to the wiring of the semiconductor device 1 can be increased.

The present application also provides a design assistance device of a semiconductor device, as shown in fig. 5, in an embodiment of the present application, a schematic diagram of a hardware structure of the design assistance device is provided, and a design assistance device 10 of the semiconductor device includes a computer system, for example, including a CPU11, an auxiliary storage device 12, a main storage device 13, a communication interface 14, an input portion 15, a display portion 16, and a bus 18. The auxiliary storage device 12 is for storing a program executed by the CPU11, data referred to by the program, and the like, and the auxiliary storage device 12 is, for example, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like. The main storage device 13 is used for storing a work area when executing each program, and the main storage device 13 is, for example, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like. The communication interface 14 is used for connecting to a network, the input unit 15 includes an input device such as a keyboard or a mouse, the display unit 16 is a liquid crystal display device or the like for displaying data, and the respective components are connected via a bus 18, for example.

Referring to fig. 5, in an embodiment of the present application, a series of programs for realizing various functions described later, including, for example, a design auxiliary program, are stored in the auxiliary storage device 12, and the programs are read into the main storage device 13 by the CPU11 to perform processing and arithmetic processing of information, thereby realizing various functions. In other embodiments, the program may be selected in other suitable forms, such as a form that is pre-installed in the secondary storage device 12, a form that is provided in a state that is stored in another computer-readable storage medium, or a form that is transmitted via a wired or wireless communication unit. Wherein the computer readable storage medium is a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, or a semiconductor memory, etc.

Referring to fig. 6, in an embodiment of the present application, a functional block diagram of one functional example of the design assistance device 10 is taken as an example, where the design assistance device 10 includes a storage unit 101, a circuit diagram design assistance unit 102a, a layout diagram design assistance unit 102b, and a verification unit 103.

Referring to fig. 2 and 6, in the design assistance device 10 according to an embodiment of the present application, a design diagram of the semiconductor device 1, such as symbol data and physical characteristic values of elements used in manufacturing a circuit diagram, is stored in the memory unit 101, and symbol types are sym-format, and symbols of elements stored in the memory unit 101 are symbols of semiconductor elements such as a resistor element, a capacitor element, and a transistor. In other embodiments, the elements stored in the storage unit 101 may also include symbols of various elements not disclosed in the present embodiment, such as a power supply element or a control IC, or the like. The memory cell 101 also stores a plurality of symbols including, for example, four-terminal connection symbols of connection states of the first electrode 3, the second electrode 4, the first shielding portion 5, and the second shielding portion 6 corresponding to the semiconductor device 1 in the present embodiment, and a plurality of symbols of connection states of a plurality of elements necessary for designing an electronic device circuit.

Referring to fig. 2, 7 and 8, in an embodiment of the application, fig. 7 is a schematic diagram of parasitic capacitance of the MOM capacitor when the first shielding portion and the second shielding portion are metal-bonded and then connected to the ground terminal. Fig. 8 is a schematic diagram of connection symbols when the first shielding part and the second shielding part are connected to the ground terminal after metal bonding in the MOM capacitor. In the present embodiment, when the first shielding portion 5 and the second shielding portion 6 are at the same potential, the connection symbol thereof is a three-terminal connection symbol including a terminal of the first electrode, a terminal of the second electrode, and one ground terminal, as shown in fig. 8.

Referring to fig. 2, 9 and 10, in another embodiment of the present application, fig. 9 is a schematic diagram of parasitic capacitance when the first shielding portion and the second shielding portion of the MOM capacitor are connected to different ground terminals, and fig. 10 is a schematic diagram of connection symbols when the first shielding portion and the second shielding portion of the MOM capacitor are connected to different ground terminals. In the present embodiment, when the first shielding portion 5 and the second shielding portion 6 are respectively different in potential, the connection symbols thereof are as shown in fig. 10, and the connection symbols include four-terminal connection symbols of the terminal of the first electrode, the terminal of the second electrode, the first ground terminal GND1 and the second ground terminal GND 2. In the four-terminal connection symbol, the first ground terminal GND1 and the second ground terminal GND2 may be denoted by a common GND, or may be used as a three-terminal connection symbol.

Referring to fig. 6 to 10, in an embodiment of the present application, a three-terminal connection symbol and a four-terminal connection symbol are stored in the memory unit 101 in the form of symbol data sym as symbols representing connection states of the MOM capacitor and the first shielding part and the second shielding part disposed at both sides of the MOM capacitor. The memory unit 101 also stores connection information of wiring between each element in a circuit diagram and a layout diagram generated by an operation of a designer described later. Specifically, for example, the memory unit 101 stores circuit diagram data SD including connection information (netlist) between elements in the circuit diagram, and layout data LD including connection information (netlist) between elements in the layout diagram.

Referring to fig. 5 to 10, in the design assistance device 10, a circuit diagram design assistance unit 102a assists the circuit design of the semiconductor device by using the stored symbol data sym. The circuit diagram design support unit 102a receives an input operation via the input unit 15, and is connected to the storage unit 101 in a bidirectional communication manner. By using the circuit diagram design support unit 102a, a circuit diagram of an electronic device circuit to be designed can be created using the symbol data sym stored in the storage unit 101. The circuit diagram data SD created by the circuit diagram design assistance unit 102a may be stored in the storage unit 101. In this embodiment, the circuit design support technique of the semiconductor device other than the four-terminal connection symbol may be any implementation, that is, the circuit diagram design support unit 102a according to this embodiment may be any implementation known technique, and the present application is not limited thereto.

Referring to fig. 5 to 6, in the design assistance device 10, a layout design assistance unit 102b assists the design of the layout of the semiconductor device. The map design support unit 102b receives an input operation via the input section 15, and is connected to the storage unit 101 so as to be capable of bidirectional communication. By using the layout design support unit 102b, a layout of an electronic device circuit to be designed can be created using the symbol data sym stored in the storage unit 101. The layout data LD created by the layout design assistance unit 102b can be stored in the storage unit 101. The present application is not limited to the specific implementation of the design assistance technique of the layout of the semiconductor device, and any known technique that can be implemented may be selected.

Referring to fig. 5 to 6, in the design assistance device 10, a verification unit 103 is used to verify whether the connection information between the components shown in the layout and the circuit of the semiconductor device matches. Specifically, the verification unit 103 compares connection information between elements in the circuit diagram data SD with connection information between elements in the layout data LD based on the circuit diagram data SD and the layout data LD stored in the storage unit 101 to verify whether the connection information matches. The verification unit 103 further includes, for example, a netlist extraction unit 103a and a comparison unit 103b for performing layout schematic (Layout Versus Schematics, LVS) verification described later.

Referring to fig. 5 to 6, in the design assistance apparatus 10, the netlist extraction unit 103a extracts netlists by taking as input circuit diagram data SD and layout data LD of electronic device circuits stored in the memory unit 101. The comparison unit 103b compares the netlist extracted from the circuit diagram data SD with the netlist extracted from the layout data LD, and determines whether or not the netlists are equal to each other. The verification unit 103 displays the comparison result of the comparison unit 103b on the display unit 16, and notifies the designer of the evaluation result as to whether or not the connection information of the circuit diagram and the layout diagram match, that is, are equal.

Referring to fig. 5 to 6, in another embodiment of the present application, the layout design assistance unit 102b and the verification unit 103 may not be disposed in the design assistance device 10, for example, the layout design assistance unit 102b may be selectively implemented by using other computer systems. At the same time, the verification unit 103 also selects another computer system to acquire the circuit diagram data designed by the design assistance device 10 and the layout data designed by the other computer system via the communication medium, and uses these data to perform LVS verification.

Referring to fig. 1 and 11, fig. 11 is a flowchart of an LVS verification process according to an embodiment of the present application. In LVS verification, it is verified whether or not the manufactured elements and connection information between the elements are properly implemented in the layout design at the logic circuit design stage. Specifically, in LVS verification, the netlist extracted based on the circuit diagram data SD is compared with the netlist extracted based on the layout data LD of the electronic device circuit 8 to verify whether or not it is equivalent.

Referring to fig. 6 and 11, in step S11, the netlist extraction unit 103a in the verification unit 103 extracts a netlist including connection information between elements obtained from the circuit diagram data SD. In step S12, the netlist extraction unit 103a in the verification unit 103 extracts a netlist from the connection information between the elements in the layout data LD restored from the layout data LD.

Referring to fig. 6 and 11, in an embodiment of the present application, in step S13 to step S16, the verification unit 103 performs LVS verification. Specifically, verification section 103 compares the netlist extracted from circuit diagram data SD with the netlist extracted from layout data LD, and determines whether or not the netlist of circuit diagram data SD matches the netlist extracted from layout data LD. If the netlist of the circuit diagram data SD matches the netlist extracted from the layout data LD, a normal judgment is made, and if the netlist of the circuit diagram data SD does not match the netlist extracted from the layout data LD, the verification unit 103 makes an error judgment.

Referring to fig. 1 to 10, in an embodiment of the application, a design assisting device 10 of a semiconductor device, in a semiconductor device 1 having MOM capacitor 2, has four terminal connection symbols indicating that a first shielding part 5 and a second shielding part 6 are connected to different ground terminals, i.e. the design of the semiconductor device in which the first shielding part 5 and the second shielding part 6 are connected to different ground terminals can be performed. The problem of the disadvantage of the layout due to the excessive area caused by the direct connection of the first shielding part 5 and the second shielding part 6 can be avoided. The design support device 10 can prevent the failure of design due to the absence of a connection symbol representing such a circuit in the three-terminal connection symbol when the first shielding portion 5 and the second shielding portion 6 are connected to different ground terminals, and ensure smooth design. Meanwhile, when designing the connection mode in which the first shielding part 5 and the second shielding part 6 are connected with different ground terminals, it is possible to avoid the existence of three-terminal connection symbols instead of the above, and to avoid causing the netlist extracted based on the circuit diagram data SD to become inconsistent with the netlist extracted based on the layout data LD, thereby avoiding causing erroneous determination in LVS verification and ensuring LVS verification accuracy of the semiconductor device. Therefore, the first shielding part and the second shielding part are connected with the semiconductor device through different grounding terminals, and the limitation of the semiconductor device with the three-terminal connection symbol is broken through.

Referring to fig. 10 and 12, in the design assistance device of the semiconductor device according to the embodiment of the application, since the four-terminal connection symbol is one of the connection symbols, the degree of freedom of the design of the semiconductor device can be improved by using the four-terminal connection symbol in the circuit design. By using the design assistance device of the semiconductor device according to the present embodiment, the first shield portion and the second shield portion are allowed to be connected to different ground terminals, and it is possible to avoid the need to connect the shield metal layers at both ends so as to surround the MOM capacitor, as shown in fig. 12. That is, the semiconductor device provided by the present application can improve the degree of freedom of wiring processing, and can improve the degree of freedom of circuit design, thereby realizing miniaturization of the semiconductor device. Further, by using symbols corresponding to actual circuits when manufacturing the design drawing, erroneous output related to connection information in LVS verification can be reduced, and efficiency of design work can be improved.

As described above, the present application provides a semiconductor device and a design support device for a semiconductor device, which can reduce the number of connections of wirings and the area of the wiring space in the semiconductor device and can miniaturize the semiconductor device by disconnecting the first shield portion from the second shield portion in the wiring space. The first shielding part and the second shielding part are provided with mutually independent terminals and are connected with the grounding terminals with different potentials, so that the freedom degree of wiring of each terminal of the semiconductor device can be improved, the wiring requirements of different circuits can be met, and the freedom degree of design related to the semiconductor device and the wiring can be improved. By using symbols corresponding to actual circuits when manufacturing the design drawing, erroneous output related to connection information in LVS verification can be reduced, and efficiency of design work can be improved.

Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment (a specific embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily in all embodiments, of the application. Thus, the appearances of the phrases "in one embodiment (in one embodiment)", "in an embodiment (in an embodiment)", or "in a specific embodiment (in a specific embodiment)" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present application may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the application described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the application.

The embodiments of the application disclosed above are intended only to help illustrate the application. The examples are not intended to be exhaustive or to limit the application to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and the full scope and equivalents thereof.

Claims

1. A semiconductor device, comprising:

2. The semiconductor device according to claim 1, wherein the first shield portion and the second shield portion are connected to ground terminals having different electric potentials.

3. The semiconductor device according to claim 2, wherein the ground terminal includes a first ground terminal and a second ground terminal, and wherein potentials of the first ground terminal and the second ground terminal are different.

4. The semiconductor device according to claim 3, wherein the first shield portion is connected to the first ground terminal or the second ground terminal, and wherein the second shield portion is connected to the second ground terminal or the first ground terminal.

5. The semiconductor device according to claim 1, wherein the first electrode has at least one first main line.

6. The semiconductor device according to claim 5, wherein the second electrode has at least one second main line, and wherein the second main line and the first main line are alternately arranged in the first direction.

7. The semiconductor device according to claim 1, wherein a wiring space is provided on both sides of the MOM capacitor in the first direction, and wherein the first shielding portion and the second shielding portion are electrically insulated in the wiring space.

8. A design assist device for a semiconductor device according to any one of claims 1 to 7, comprising:

9. The design assist device for a semiconductor device according to claim 8, further comprising:

10. The design assist device for a semiconductor device according to claim 9, wherein connection information between elements in the circuit diagram data and connection information between elements in the layout data are stored in the storage unit.