CN213691454U - Flash memory storage circuit, circuit board and flash memory - Google Patents
Flash memory storage circuit, circuit board and flash memory Download PDFInfo
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- CN213691454U CN213691454U CN202022230659.XU CN202022230659U CN213691454U CN 213691454 U CN213691454 U CN 213691454U CN 202022230659 U CN202022230659 U CN 202022230659U CN 213691454 U CN213691454 U CN 213691454U
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Abstract
The utility model discloses a flash memory storage circuit to a circuit board with flash memory storage circuit is disclosed, the flash memory storage of circuit board has. The flash memory circuit comprises a flash memory circuit module and a redundancy circuit module. The flash memory circuit module is provided with at least three flash memory chips. The redundant circuit module is provided with a logic gate and a data selector. The data selector is provided with two. The data selector is matched to the flash memory chip. The flash memory chip is connected with the data selector, the logic gate is connected with the data selector, and the data selector is used for outputting corresponding second data according to the first data output by the flash memory chip. The logic gate is used for carrying out logic operation on the first data or the second data so as to enable the redundancy circuit module to output correct data. The utility model provides high flash memory storage circuit's stability and reliability.
Description
Technical Field
The utility model relates to a memory field, in particular to flash memory storage circuit, circuit board and flash memory.
Background
Flash memory is a type of non-volatile memory that is suitable for use in electronic systems as a storage for programs or data. The stability and reliability of flash memory is critical to electronic systems, especially in applications where stability and reliability are highly desirable.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a flash memory storage circuit can improve stability and reliability.
The utility model discloses still provide a circuit board that has above-mentioned flash memory storage circuit.
The utility model discloses still provide a flash memory of having above-mentioned circuit board.
In a first aspect, a flash memory circuit includes: the flash memory circuit module is provided with at least three flash memory chips; the redundancy circuit module is provided with two logic gates and two data selectors, the two data selectors are matched with the flash memory chip, the flash memory chip is connected with the data selectors, the logic gates are connected with the data selectors, and the data selectors are used for outputting corresponding second data according to first data output by the flash memory chip; the logic gate is used for carrying out logic operation on the first data or the second data so as to enable the redundancy circuit module to output correct data.
According to the utility model discloses flash memory storage circuit has following beneficial effect at least: the flash memory chip is connected with the data selector, the data selector is connected with the logic gate, the flash memory chip is provided with more than three chips, and when one flash memory chip is damaged, the rest flash memory chips still can normally work through the redundant circuit module, so that the stability and the reliability of the flash memory storage circuit are improved.
According to some embodiments of the invention, the logic gate comprises an or gate, the data selector comprises a first data selector and a second data selector, the first data selector sets a first output, the second data selector sets a second output, the or gate is provided with a first input and a second input, the first output with the first input is connected, the second output with the second input is connected.
According to some embodiments of the present invention, the logic gate further comprises a not gate, the second data selector sets an enable terminal, and the not gate passes through the enable terminal and the second data selector are connected.
According to some embodiments of the present invention, the flash memory circuit module sets up three flash memory chips, the data selector is a 4-to-1 data selector.
In a second aspect, a wiring board includes the flash memory circuit of the first aspect.
According to the utility model discloses circuit board has following beneficial effect at least: the circuit board uses the flash memory circuit of the first aspect, which is beneficial to improving the stability and reliability of the equipment using the circuit board in the aspect of memory function.
According to the utility model discloses a some embodiments, the circuit board includes data selection layer and flash memory circuit layer, the data selector sets up the data selection layer, the flash memory chip sets up the flash memory circuit layer.
According to some embodiments of the utility model, the circuit board still includes the lead frame layer, the upside on data selection layer is provided with first insulation board, the upside on flash memory circuit layer is provided with the second insulation board, the upside on lead frame layer is provided with the third insulation board.
According to some embodiments of the invention, the data selection layer is located flash memory circuit layer top, the lead frame layer is located flash memory circuit layer below.
In a third aspect, a flash memory comprises the circuit board of the second aspect.
According to the utility model discloses flash memory has following beneficial effect at least: the flash memory is applied to the circuit board in the second aspect, and the stability and the reliability of the storage function of the flash memory are improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a structural diagram of a flash memory circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a flash memory circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another embodiment of the flash memory circuit shown in FIG. 2;
fig. 4 is a stacked view of a circuit board according to an embodiment of the present invention.
The reference numbers are as follows:
a flash memory circuit module 1000, a flash memory chip 1100, a redundancy circuit module 2000, a data selector 2100, a logic gate 2200;
a first flash memory chip 1110, a second flash memory chip 1120, a third flash memory chip 1130, and a fourth flash memory chip 1140;
a first data selector 2110, a second data selector 2120, a first output 2111, a second output 2121, an enable 2122;
an or gate 2211, a first input 2211A, a second input 2211B, a not gate 2221;
the wiring board 3000, the data selection layer 3100, the first bridge wire 3110, the first insulating plate 3120, the flash memory circuit layer 3200, the second bridge wire 3210, the second insulating plate 3220, the lead frame layer 3300, the third bridge wire 3310, and the third insulating plate 3320.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated with respect to the orientation description, such as up, down, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means are one or more, a plurality of means are two or more, and the terms greater than, less than, exceeding, etc. are understood as not including the present number, and the terms greater than, less than, within, etc. are understood as including the present number. If any description to first, second, third or fourth is for the purpose of distinguishing between technical features, it is not to be understood as indicating or implying relative importance or implying any indication of the number of technical features indicated or the order in which the technical features are indicated.
In the description of the present invention, unless there is an explicit limitation, the words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in combination with the specific contents of the technical solution.
Referring to fig. 1, a flash memory circuit includes a flash memory circuit block 1000 and a redundancy circuit block 2000. The flash memory circuit module 1000 is provided with at least three flash memory chips 1100. The redundancy circuit block 2000 is provided with a logic gate 2200 and a data selector 2100. The data selector 2100 is provided with two. The data selector 2100 is matched to the flash memory chip 1100. The flash memory chip 1100 is connected to a data selector 2100, the logic gate 2200 is connected to the data selector 2100, and the data selector 2100 is configured to output corresponding second data according to the first data output by the flash memory chip 1100. The logic gate 2200 is used for performing a logic operation on the first data or the second data so that the redundancy circuit module 2000 outputs correct data.
Specifically, three or more flash memory chips 1100 are connected to the data selector 2100, and the logic gate 2200 is connected to the data selector 2100. Each flash chip 1100 outputs a first data, all the first data enters two data selectors 2100, the two data selectors 2100 output corresponding second data according to the first data from the flash chip 1100, and the logic gate 2200 performs a logic operation on the second data and finally outputs a correct data. When all the first data are the same, the correct data are the same as the first data; when one first data is not identical to the other first data, i.e., one flash memory chip 1100 is broken, the correct data is identical to the other first data. All the first data are uniquely determined as a correct data through the data selector 2100 and the logic gate 2200, thereby improving the stability and reliability of the flash memory storage circuit.
Referring to fig. 2, in some embodiments of the present invention, logic gate 2200 includes an or gate 2211 and a not gate 2221. The data selector 2100 includes a first data selector 2110 and a second data selector 2120, the first data selector 2110 is provided with a first output 2111, the second data selector 2120 is provided with a second output 2121, the or gate 2211 is provided with a first input 2211A and a second input 2211B, the first output 2111 is connected with the first input 2211A, and the second output 2121 is connected with the second input 2211B. The second data selector 2120 sets an enable terminal 2122, and the not gate 2221 is connected to the second data selector 2120 through the enable terminal 2122.
Specifically, the or gate 2211 performs an or logical operation on the second data output from the first data selector 2110 and the second data output from the second data selector 2120. The not gate 2221 is connected to the enable terminal 2122 of the second data selector 2120, and the not gate 2221 performs a negation logic operation on the first data to be input to the enable terminal 2122. Through the arrangement of the or gate 2211 and the not gate 2221, the redundant circuit module 2000 realizes that the first data of more than three inputs is uniquely determined as one correct data, which is beneficial to improving the stability and the reliability.
Referring to fig. 2, in some embodiments of the present invention, the flash memory chip 1100 includes a first flash memory chip 1110, a second flash memory chip 1120, and a third flash memory chip 1130, and the first data selector 2110 and the second data selector 2120 are both 1-out-of-4 data selectors. Specifically, the 1-out-of-4 data selector is provided with an a input terminal, a B input terminal, a D0 input terminal, a D1 input terminal, a D2 input terminal, a D3 input terminal, an S control terminal, and an output terminal. The first flash chip 1110 is provided with an S1 output terminal, the second flash chip 1120 is provided with an S2 output terminal, and the third flash chip 1130 is provided with an S3 output terminal. The output end of the S1 is connected with the input end A of each 1-from-4 data selector; the output end of the S2 is connected with the B input end of each 1-from-4 data selector; the output terminal of S3 is connected to the S control terminal of first data selector 2110, and to the S control terminal of second data selector 2120, also referred to as enable terminal 2122, through not gate 2221.
The D0 input terminal, the D1 input terminal, and the D2 input terminal of the first data selector 2110 input "0", and the D3 input terminal of the first data selector 2110 input "1". The D0 input terminal of the second data selector 2120 inputs "0", and the D1 input terminal, the D2 input terminal and the D3 input terminal of the second data selector 2120 inputs "1". The relationship between the first data output from the flash chip 1100 and the correct data obtained through the logic gate 2200 is shown in table 1.
TABLE 1
In table 1, S1 indicates the first data output from the first flash chip 1110, S2 indicates the first data output from the second flash chip 1120, S3 indicates the first data output from the third flash chip 1130, and S0 indicates correct data. As can be seen from table 1, when there are more than two identical first data, the correct data are identical to the more than two identical first data. If S1 is the same as S2, and S1 is different from S3, S0 is the same as S1; s1 is the same as S2, S1 is the same as S3, and S0 is the same as S1. With the arrangement of fig. 2, when one flash memory chip 1100 is damaged, correct data can be obtained, so that the stability and reliability of the flash memory circuit are improved.
It should be noted that "0" or "1" input through the D0 input terminal, the D1 input terminal, the D2 input terminal, and the D3 input terminal refers to an electronic signal, and also refers to the second data mentioned in some embodiments, where "0" is low level and "1" is high level.
Referring to fig. 3, in other embodiments, a flash memory chip 1100 includes a first flash memory chip 1110, a second flash memory chip 1120, a third flash memory chip 1130, and a fourth flash memory chip 1140. The first data selector 2110 and the second data selector 2120 are both 1-out-of-8 data selectors. Specifically, the 1-out-of-8 selector is provided with an a input terminal, a B input terminal, a C input terminal, a D0 input terminal, a D1 input terminal, a D2 input terminal, a D3 input terminal, a D4 input terminal, a D5 input terminal, a D6 input terminal, a D7 input terminal, an S control terminal, and an output terminal. The first flash chip 1110 is provided with an S1 output terminal, the second flash chip 1120 is provided with an S2 output terminal, the third flash chip 1130 is provided with an S3 output terminal, and the fourth flash chip 1140 is provided with an S4 output terminal.
The output end of the S1 is connected with the input end A of each 8-to-1 data selector; the output end of the S2 is connected with the B input end of each 8-to-1 data selector; the output end of the S3 is connected with the C input end of each 8-to-1 data selector; the output terminal of S4 is connected to the S control terminal of first data selector 2110, and to the S control terminal of second data selector 2120, also referred to as enable terminal 2122, through not gate 2221.
The D0 input terminal, D1 input terminal, D2 input terminal, D3 input terminal, D4 input terminal, D5 input terminal, and D6 input terminal of the first data selector 2110 input "0", and the D7 input terminal of the first data selector 2110 input "1". The D0 input terminal, D1 input terminal, D2 input terminal, D3 input terminal, and D5 input terminal of the second data selector 2120 all input "0", and the D4 input terminal, D6 input terminal, and D7 input terminal of the second data selector 2120 all input "1". The relationship between the first data output from the flash chip 1100 and the correct data obtained through the logic gate 2200 is shown in table 2.
| S1 | S2 | S3 | S4 | S0 |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 1 | 0 |
| 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
TABLE 2
In table 2, S1 indicates the first data output from the first flash chip 1110, S2 indicates the first data output from the second flash chip 1120, S3 indicates the first data output from the third flash chip 1130, S4 indicates the first data output from the fourth flash chip 1140, and S0 indicates correct data. As can be seen from table 2, when there are more than three identical first data, the correct data are identical to the more than three identical first data; when there are not three or more identical first data, the correct data is "0". If S1 is the same as S2, S1 is the same as S3, and S1 is different from S4, S0 is the same as S1. With the arrangement of fig. 3, when one flash memory chip 1100 is damaged, correct data can be obtained, so that the stability and reliability of the flash memory circuit are improved.
It should be noted that "0" or "1" input through the D0 input terminal, the D1 input terminal, the D2 input terminal, the D3 input terminal, the D4 input terminal, the D5 input terminal, the D6 input terminal, and the D7 input terminal refers to an electronic signal and also refers to the second data mentioned in some embodiments, "0" is low level, and "1" is high level.
Referring to fig. 4, a wiring board 3000 is provided with the flash memory circuit of the first aspect. Wiring board 3000 includes data selection layer 3100, flash memory circuit layer 3200, and leadframe layer 3300, with data selector 2100 disposed on data selection layer 3100, and flash memory chip 1100 disposed on flash memory circuit layer 3200. The upper side of the data selection layer 3100 is provided with a first insulation plate 3120, the upper side of the flash memory circuit layer 3200 is provided with a second insulation plate 3220, and the upper side of the lead frame layer 3300 is provided with a third insulation plate 3320. The data selection layer 3100 is located above the flash memory circuit layer 3200, and the leadframe layer 3300 is located below the flash memory circuit layer 3200.
Specifically, the wiring board 3000 is divided into three layers, namely, a data selection layer 3100, a flash memory circuit layer 3200, and a lead frame layer 3300 from top to bottom. And an insulating plate is arranged between each two layers and is used for forming a separation gap between the layers so as to avoid the interference of an unnecessary circuit structure between the layers. Each layer is provided with a bridge such as the data select layer 3100 provides a first bridge 3110, the flash circuitry layer 3200 provides a second bridge 3210, and the leadframe layer 3300 provides a third bridge 3310 for connections to the outside of the wiring board 3000. The circuit board 3000 is provided with the flash memory circuit of the first aspect, and the three-dimensional three-layer design is adopted, so that the circuit board 3000 provided with the flash memory circuit is miniaturized, and the miniaturization packaging is facilitated.
In some embodiments, the flash memory employs the wiring board 3000 of the second aspect. Specifically, the circuit board 3000 of the second aspect is provided with the flash memory circuit of the first aspect, and the circuit board 3000 provided with the flash memory circuit is miniaturized by adopting a three-dimensional three-layer design, which is beneficial to the realization of the miniaturized design of the flash memory using the circuit board 3000.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (9)
1. A flash memory storage circuit, comprising:
the flash memory circuit module is provided with at least three flash memory chips;
the redundancy circuit module is provided with two logic gates and two data selectors, the two data selectors are matched with the flash memory chip, the flash memory chip is connected with the data selectors, the logic gates are connected with the data selectors, and the data selectors are used for outputting corresponding second data according to first data output by the flash memory chip;
the logic gate is used for carrying out logic operation on the first data or the second data so as to enable the redundancy circuit module to output correct data.
2. The flash memory circuit of claim 1, wherein the logic gate comprises an OR gate, the data selector comprises a first data selector and a second data selector, the first data selector provides a first output, the second data selector provides a second output, the OR gate provides a first input and a second input, the first output is coupled to the first input, and the second output is coupled to the second input.
3. The flash memory circuit of claim 2, wherein the logic gate further comprises a not gate, the second data selector setting an enable terminal, the not gate being connected to the second data selector through the enable terminal.
4. The flash memory circuit of claim 1, wherein said flash memory circuit module is configured with three said flash memory chips, and said data selector is a 1-out-of-4 data selector.
5. A circuit board provided with a flash memory circuit according to any one of claims 1 to 4.
6. The wiring board of claim 5, wherein the wiring board comprises a data selection layer and a flash memory circuit layer, the data selector is disposed on the data selection layer, and the flash memory chip is disposed on the flash memory circuit layer.
7. The wiring board of claim 6, further comprising a leadframe layer, wherein the data selection layer is provided with a first insulating plate on an upper side, the flash memory circuit layer is provided with a second insulating plate on an upper side, and the leadframe layer is provided with a third insulating plate on an upper side.
8. The wiring board of claim 7, wherein the data selection layer is located above the flash memory circuit layer and the leadframe layer is located below the flash memory circuit layer.
9. A flash memory comprising the wiring board according to any one of claims 5 to 8.
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| CN202022230659.XU CN213691454U (en) | 2020-10-09 | 2020-10-09 | Flash memory storage circuit, circuit board and flash memory |
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| CN202022230659.XU CN213691454U (en) | 2020-10-09 | 2020-10-09 | Flash memory storage circuit, circuit board and flash memory |
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