CN115705461A - MOS (Metal oxide semiconductor) tube capacitor layout and forming method and verification method thereof - Google Patents
MOS (Metal oxide semiconductor) tube capacitor layout and forming method and verification method thereof Download PDFInfo
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Abstract
The embodiment of the application relates to the field of semiconductors, in particular to an MOS (metal oxide semiconductor) transistor capacitor layout, a forming method and a verification method thereof, wherein the MOS transistor capacitor layout comprises the following steps: the working layer comprises an active layer, a gate layer, a source layer and a drain layer, wherein the source layer is positioned on one side of the gate layer, the drain layer is positioned on the other side of the gate layer, and the gate layer, the source layer and the drain layer are all positioned right above the active layer; the capacitance identification layer at least covers partial area of the working layer. The embodiment of the application is beneficial to improving the consistency verification efficiency of the LVS.
Description
Technical Field
The embodiment of the application relates to the technical field of semiconductors, in particular to an MOS (metal oxide semiconductor) transistor capacitor layout and a forming method and a verification method thereof.
Background
As the construction of integrated circuits becomes more complex and semiconductor manufacturing processes become more elaborate, a large number of semiconductor devices can now be integrated in integrated circuits. Integrated circuits include a large number of components, such as transistors, resistors, capacitors, and the like.
The capacitor may be formed by one or more MOS (Metal-Oxide-Semiconductor) transistors, and the quality of layout (layout) of the MOS transistors is closely related to the performance of the capacitor. In order to verify whether the layout meets the requirement, layout Versus Schematic (LVS) consistency verification may be performed to verify whether the layout is the same as a schematic corresponding to the capacitor.
However, the current LVS verification for MOS transistor capacitance has a problem of low verification efficiency.
Disclosure of Invention
The technical problem solved by the embodiment of the application is to provide an MOS tube capacitor layout, and a forming method and a verification method thereof, so as to at least solve the problem of low LVS verification efficiency.
According to some embodiments of the present application, an aspect of the present application provides a MOS transistor capacitor layout, including: the working layer comprises an active layer, a grid layer, a source layer and a drain layer, wherein the source layer is positioned on one side of the grid layer, the drain layer is positioned on the other side of the grid layer, and the grid layer, the source layer and the drain layer are all positioned right above the active layer; the capacitance identification layer at least covers partial area of the working layer.
In addition, the capacitance recognition layer covers all areas of the working layer.
In addition, the capacitance recognition layer includes: the first identification layer is opposite to all areas of the working layer; the second recognition layer is positioned at the periphery of the working layer.
In addition, the capacitance identification layer is rectangular.
In addition, the capacitance identification layer is provided with a first boundary extending along a first direction and a second boundary extending along a second direction, the first direction is perpendicular to the second direction, and two ends of the second boundary are respectively connected with one first boundary; the first boundary is flush with a boundary of the gate layer.
In addition, the second boundary is located at a periphery of the active layer.
In addition, the capacitance identification layer is rectangular, and the width-length ratio of the capacitance identification layer is the same as the channel width-length ratio of the MOS tube corresponding to the working layer.
According to some embodiments of the present application, another aspect of the present application provides a method for forming a MOS transistor capacitor layout, including: establishing a working layer, wherein the working layer comprises an active layer, a gate layer, a source layer and a drain layer, the source layer is positioned on one side of the gate layer, the drain layer is positioned on the other side of the gate layer, and the gate layer, the source layer and the drain layer are all positioned right above the active layer; and establishing a capacitance identification layer, wherein the capacitance identification layer at least covers partial area of the working layer.
In addition, the method for establishing the capacitance identification layer comprises the following steps: acquiring the channel width-length ratio of the MOS tube capacitor corresponding to the working layer; and establishing the capacitance identification layer in a rectangular shape based on the channel width-length ratio, wherein the width-length ratio of the rectangular shape is the same as the channel width-length ratio.
According to some embodiments of the present application, a further aspect of the present application provides a layout schematic diagram consistency verification method, including: constructing an equivalent circuit diagram of the equivalent total capacitance of the MOS tube capacitor; constructing at least 2 MOS tube capacitor layouts according to the embodiment; identifying all the MOS tube capacitor layouts based on the capacitor identification layer; and acquiring the actual total capacitance of the identified capacitors corresponding to the MOS transistor capacitor layout, and verifying the consistency of the actual total capacitance and the equivalent total capacitance.
In addition, the method for constructing at least 2 MOS tube capacitor layouts comprises the following steps: and constructing at least 2 MOS tube capacitor layouts with different channel width-length ratios.
In addition, the capacitance identification layer is rectangular, and the width-to-length ratio of the capacitance identification layer is the same as the channel width-to-length ratio of the MOS tube corresponding to the MOS tube capacitance layout; identifying all MOS tube capacitor layouts, including: and identifying the width-length ratio of the capacitance identification layer corresponding to each MOS tube capacitance layout, and taking the width-length ratio as the channel width-length ratio of the MOS tube corresponding to the MOS tube capacitance layout.
In addition, a method of constructing an equivalent circuit diagram of an equivalent total capacitance, comprising: and generating a single MOS tube based on the equivalent total capacitance, wherein the grid electrode of the MOS tube is connected with a working power supply, and the source electrode and the drain electrode are both grounded.
In addition, the method for obtaining the actual total capacitance comprises the following steps: acquiring the layout area of each identified MOS tube capacitor layout; acquiring the sum of the layout areas of all the identified MOS tube capacitor layouts based on each layout area; and acquiring the actual total capacitance based on the layout area sum and a standard capacitance, wherein the standard capacitance is a capacitance value corresponding to the standard MOS tube capacitance layout, and the standard MOS tube capacitance layout has a channel width-length ratio of 1.
The technical scheme provided by the embodiment of the application has the following advantages:
according to the technical scheme of the MOS tube capacitor layout, the MOS tube capacitor layout design method and device comprises a working layer used for defining the MOS tube and a capacitor identification layer at least covering a partial region of the working layer, the capacitor identification layer is arranged, so that different MOS tube capacitor layouts can be identified simultaneously, time for positioning different MOS tube capacitor layouts is shortened, and consistency verification efficiency of the LVS is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of a circuit;
FIG. 2 is a circuit diagram of a MOS transistor corresponding to FIG. 1;
fig. 3 is a schematic diagram of a MOS transistor capacitor layout according to an embodiment of the present application;
fig. 4 is another schematic structural diagram of a MOS transistor capacitor layout provided in the embodiment of the present application;
fig. 5 is a schematic flow chart of a method for forming a MOS transistor capacitor layout according to an embodiment of the present application;
fig. 6 is a schematic flow chart of consistency verification of a layout schematic diagram provided in the embodiment of the present application;
FIG. 7 is an equivalent circuit diagram provided by an embodiment of the present application;
fig. 8 is a schematic structural diagram of a MOS transistor capacitor layout provided in the embodiment of the present application.
Detailed Description
The background art can know that the LVS consistency verification aiming at the MOS tube capacitor at present has the problem of low efficiency.
In order to reasonably utilize layout space, a plurality of MOS transistor capacitor layouts are usually laid out, and the channel width-length ratio of the MOS transistor corresponding to each MOS transistor capacitor layout may also be different, and correspondingly, the circuit schematic diagram also includes a plurality of MOS transistors. Specifically, taking a layout of 3 MOS transistors and capacitors as an example, fig. 1 is a schematic circuit diagram, and fig. 2 is a layout of a MOS transistor circuit corresponding to fig. 1.
Referring to fig. 1, a circuit schematic includes: the first MOS transistor 11, the second MOS transistor 12 and the third MOS transistor 13, and the gates of the first MOS transistor 11, the second MOS transistor 12 and the third MOS transistor 13 are all electrically connected to the working power VDD, and the drain and the source are all grounded VSS.
Referring to fig. 2, the mos transistor capacitor layout includes: the method comprises the following steps of firstly, obtaining a first layout 10, a second layout 20 and a third layout 30, wherein the first layout 10, the second layout 20 and the third layout 30 respectively comprise an active layer 21, a gate layer 22, a source layer 23 positioned on one side of the gate layer 22 and a drain layer 24 positioned on the other side of the gate layer 22; the channel width-length ratio corresponding to the first layout 10 is the same as the channel width-length ratio of the first MOS transistor 11, the channel width-length ratio corresponding to the second layout 20 is the same as the channel width-length ratio of the second MOS transistor 12, and the channel width-length ratio corresponding to the third layout 30 is the same as the channel width-length ratio of the third MOS transistor 13.
During the layout schematic diagram consistency verification, consistency verification needs to be performed on the first layout 10 and the first MOS transistor 11, consistency verification needs to be performed on the second layout 20 and the second MOS transistor 12, and consistency verification needs to be performed on the third layout 30 and the third MOS transistor 13. The consistency verification method has the advantages that the consistency verification steps are complex, the verification times required by consistency verification are increased when the number of the MOS tube capacitor layouts is increased, the consistency verification efficiency is low, and the consistency verification difficulty is increased along with the increase of the number of the MOS tube layouts. In addition, for the consistency verification, when a corresponding circuit schematic diagram is constructed, MOS transistors with the same number as the MOS transistor capacitor layout are required to be constructed, and the channel width-to-length ratios of the different MOS transistors are different, which will also result in a longer time required for constructing the circuit schematic diagram, and accordingly, the efficiency of the consistency verification will also be affected.
The application is implemented to provide a MOS pipe capacitor layout, including covering the electric capacity discernment layer of the subregion of working layer at least, this electric capacity discernment layer is convenient to be discerned simultaneously and is in different MOS pipe capacitor layout to shorten the time of discerning MOS pipe capacitor layout, thereby be favorable to promoting the efficiency that LVS verified.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
Fig. 3 is a schematic diagram of a capacitor layout of a MOS transistor according to an embodiment of the present application.
Referring to fig. 3, the mos transistor capacitor layout includes: an Active Area (AA) layer 101, a gate layer 102, a source layer 103 on one side of the gate layer 102, and a drain layer 104 on the other side of the gate layer 102, wherein the gate layer 102, the source layer 103, and the drain layer 104 are all located right above the Active layer 101; the capacitance recognition layer 110, the capacitance recognition layer 110 covers at least a partial area of the working layer 100.
The capacitor identification layer 110 is arranged, so that MOS tube capacitor layouts arranged in different regions can be identified simultaneously, the time required for extracting parameter information of the MOS tube capacitor layouts in the different regions is reduced, the time required for verifying the consistency of the schematic diagram by the layouts is shortened, and the consistency verification efficiency is improved
The MOS transistor capacitor layout provided in the embodiments of the present application will be described in more detail below with reference to the accompanying drawings.
The working layer 100 is used for actually defining the MOS transistor capacitor corresponding to the MOS transistor capacitor layout. Specifically, the active layer 100 may define the actual capacitance value of the MOS transistor capacitor.
The active layer 101 may be rectangular in shape to define the topography and dimensions of the active region of the MOS transistor. The source layer 103 and the drain layer 104 are distributed along the first direction X; the gate layer 102 may be rectangular, and the gate layer 102 crosses the active layer 101 in the second direction Y to define a channel of the MOS transistor and ensure a source and drain layer defined by the source layer 103. The source layer 103 may be rectangular in shape and is used to define a first conductive layer electrically connected to the source region of the MOS transistor; the drain layer 104 may be rectangular in shape and may be used to define a second conductive layer electrically connected to the drain region of the MOS transistor.
The number of source layers 103 is N, the number of drain layers 104 is N, and N is an integer greater than or equal to 1. In other embodiments, the number of the source layers 103 and the drain layers 104 may be 1.
In some embodiments, the length of the gate layer 102 in the second direction Y may be greater than the length of the active layer 101 to avoid unnecessary electrical connection of the source and drain regions. In other embodiments, the length of the gate layer 102 along the second direction Y may also be equal to the length of the active layer 101.
In addition, the width dimension of the active layer 101 in the second direction Y is defined as the width W of the channel of the MOS transistor, the width dimension of the gate layer 102 in the first direction X is defined as the length L of the channel of the MOS transistor, and W/L is the width-to-length ratio of the channel of the MOS transistor and is directly related to the actual capacitance of the MOS transistor.
The shape of the capacitance recognition layer 110 may be rectangular. The capacitance recognition layer 110 may cover all regions of the working layer 100, so that the capacitance recognition layer 110 has a relatively large area, thereby reducing difficulty in recognizing the capacitance recognition layer 110. It will be appreciated that in other embodiments, the capacitive identification layer may cover only a portion of the working layer, ensuring that the capacitive identification layer is identifiable.
In some embodiments, the capacitive identification layer 110 may include: a first recognition layer 111, the first recognition layer 111 facing all regions of the working layer 100; a second discriminating layer 112, the second discriminating layer 112 being located at the periphery of the working layer 100. Thus, the area of the capacitance recognition layer 110 is larger than that of the working layer 100, which is beneficial to reducing the difficulty of recognizing the capacitance recognition layer 110.
The shape of the first identification layer 111 may be rectangular, and the first identification layer 111 coincides with the gate layer 102; the second recognition layer 112 may be rectangular in shape, and the second recognition layer 112 is not only coincident with the source layer 103 and the drain layer 104, but also located at the periphery of the source layer 103 and the periphery of the drain layer 104. It is understood that in other embodiments, the second identification layer 112 may include only the area coinciding with the source layer 103 and the drain layer 104.
The capacitance identification layer 110 has a first boundary B1 extending along a first direction X and a second boundary B2 extending along a second direction Y, the first direction X may be perpendicular to the second direction Y, and two ends of the second boundary B2 are respectively connected to the first boundary B1. Here, the first boundary B1 is flush with the boundary of the gate layer 102, that is, the boundary of the first identification layer 111 is flush with the boundary of the gate layer 102. In some embodiments, the second boundary B2 is located at the periphery of the active layer 101, that is, the boundary of the second recognition layer 112 is located at the periphery of the active layer 101.
In some embodiments, the capacitance identification layer 110 is rectangular, and the width-to-length ratio of the capacitance identification layer 110 is the same as the channel width-to-length ratio of the MOS transistor corresponding to the operation layer 100. Therefore, the width-length ratio of the capacitance identification layer 110 is identified as the channel width-length ratio of the MOS transistor, so that the time required for identifying the width-length ratio of the MOS transistor corresponding to the MOS transistor layout is saved, the time for verifying the consistency of the LVS is favorably prolonged, and the efficiency for verifying the consistency of the LVS is further improved.
Fig. 4 is another schematic structural diagram of a MOS transistor capacitor layout provided in the embodiment of the present application, as shown in fig. 4, an orthogonal projection of the working layer 100 on a surface where the capacitor identification layer 110 is located may also be located in the capacitor identification layer 110, and in the second direction Y, a width of the working layer 100 is smaller than a width of the capacitor identification layer 110.
The MOS tube capacitor layout provided by the embodiment is beneficial to shortening the time for identifying different MOS tube capacitor layouts in the LVS consistency verification process, so that the LVS consistency verification efficiency is improved.
The embodiment of the application further provides a method for forming the MOS transistor capacitor layout, which can be used for forming the MOS transistor capacitor layout provided by the embodiment. The method for forming the MOS transistor capacitor layout provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings, where it is to be noted that the following embodiments may refer to the detailed description of the foregoing embodiments for the same or corresponding technical features as those in the foregoing embodiments, and no further description is given below.
Fig. 5 is a schematic flow chart of a method for forming a MOS transistor capacitor layout according to an embodiment of the present application.
Referring to fig. 5, the method for forming the mos transistor capacitor layout includes the following steps:
referring to fig. 3 and 5, step S11 is to establish the operation layer 100, where the operation layer 100 includes an active layer 101, a gate layer 102, a source layer 103 on one side of the gate layer 102, and a drain layer 104 on the other side of the gate layer 102, and the gate layer 102, the source layer 103, and the drain layer 104 are all located right above the active layer 101.
Specifically, an active layer 101 and a gate layer 102 are established to be sequentially stacked, and the gate layer 102 crosses the active layer 101 in the second direction Y; in addition, the source layer 103 is electrically connected to the active layer 101 on one side of the gate layer 102, and the drain layer 104 is electrically connected to the active layer 101 on the other side of the gate layer 102.
With reference to fig. 3 and fig. 5, in step S12, the capacitance identification layer 110 is established, and the capacitance identification layer 110 at least covers a partial area of the working layer 100.
In some embodiments, the working layer 100 may be established first and then the capacitive recognition layer 110. Further, the method of establishing the capacitance recognition layer 110 may include: acquiring the channel width-length ratio of the MOS tube capacitor corresponding to the working layer 100; the capacitance recognition layer 110 is established in a rectangular shape based on the channel width-to-length ratio, and the width-to-length ratio of the rectangular shape is the same as the channel width-to-length ratio.
In other embodiments, the capacitance recognition layer 110 may be established first and then the working layer 100 may be established.
For the correspondence between the capacitance identification layer 110 and the working layer 100, reference may be made to the detailed description of the foregoing embodiments, which are not repeated herein.
Correspondingly, the embodiment of the application also provides a method for verifying the consistency of the layout schematic diagram, and the MOS tube capacitor layout provided by the embodiment can be used for verifying the consistency of the LVS. The consistency verification of the layout schematic diagram provided in the embodiment of the present application will be described in detail below with reference to the accompanying drawings, and it should be noted that the following embodiments may refer to the detailed description of the foregoing embodiments for the same or corresponding technical features as those in the foregoing embodiments, and will not be described in detail below.
Fig. 6 is a schematic flowchart of consistency verification of a layout schematic diagram provided in an embodiment of the present application, fig. 7 is an equivalent circuit diagram provided in the embodiment of the present application, and fig. 8 is a schematic structural diagram of a MOS transistor capacitor layout provided in the embodiment of the present application.
With combined reference to fig. 6 and fig. 7, step S21 is to construct an equivalent circuit diagram 200 of the equivalent capacitance of the MOS transistor capacitor.
Specifically, when an engineer designs the MOS transistor capacitance required by the integrated circuit, the engineer will construct an equivalent circuit diagram according to the actual total capacitance required by the integrated circuit. The method of constructing the equivalent circuit diagram 200 of the equivalent total capacitance may include: based on the equivalent total capacitance, a single MOS tube 201 is generated, the grid electrode of the MOS tube 201 is connected with a working power supply VDD, and the source electrode and the drain electrode are both grounded VSS. In addition, constructing the MOS transistor capacitor further includes designing an equivalent channel width-to-length ratio of the MOS transistor 201.
With reference to fig. 6 and 8, in step S22, at least 2 MOS transistors and capacitors are built in the layout 300.
Each MOS transistor capacitor layout 300 has a capacitor identification layer 310. Specifically, based on the equivalent total capacitance and layout space limitation, the multiple MOS transistor capacitor layouts 300 are constructed in combination with the formation methods provided in the foregoing embodiments. Therefore, MOS tube capacitor layouts with different sizes can be distributed in different areas, and layout space is reasonably utilized.
In some embodiments, the method for constructing at least 2 MOS transistor capacitor layouts may comprise: and constructing at least 2 MOS tube capacitor layouts with different channel width-length ratios. In one example, the method for constructing the MOS transistor capacitor layout comprises the following steps: constructing a first MOS transistor capacitor layout 301 with a first channel width-length ratio, wherein the first channel width-length ratio can be 2/2; constructing a second MOS tube capacitor layout 302 with a second channel width-length ratio, wherein the second channel width-length ratio can be 4/4; and constructing a third MOS tube capacitor layout 303 with a third channel width-length ratio, wherein the third channel width-length ratio can be 8/8.
In addition, the gate layer of each MOS transistor capacitor layout 300 is electrically connected to the operating power supply, and the source layer and the drain layer of each MOS transistor capacitor layout are grounded.
Referring to fig. 6 and 8 in combination, in step S23, based on the capacitance identification layer 310, all the MOS transistors and the capacitor layout 300 are identified.
Because each MOS transistor capacitor layout 300 is provided with the capacitor identification layer 310, all the MOS transistor capacitor layouts 300 can be identified simultaneously by the method of identifying the capacitor identification layer 310, which is beneficial to shortening the time required for positioning the MOS transistor capacitor layouts 300.
In some embodiments, the capacitance identification layers 310 are rectangular, and the width-to-length ratio of each capacitance identification layer 310 may be the same as the channel width-to-length ratio of the MOS transistor corresponding to the corresponding MOS transistor capacitance layout; identifying all the MOS transistor capacitor layouts 300 further includes: and identifying the width-length ratio of the capacitor identification layer 310 corresponding to each MOS transistor capacitor layout, and taking the width-length ratio as the channel width-length ratio of the MOS transistor corresponding to the MOS transistor capacitor layout.
And S24, acquiring the actual total capacitance of the capacitors corresponding to all the identified MOS tube capacitor layouts, and verifying the consistency of the actual total capacitance and the equivalent total capacitance.
Specifically, if the actual total capacitance is consistent with the equivalent total capacitance, it is indicated that the capacitance of the MOS transistor capacitor layout meets the design requirement. If the actual total capacitance and the equivalent total capacitance have deviation, it is indicated that the capacitance of the MOS tube capacitance layout does not meet the design requirement. It should be noted that "consistent" as used herein includes the same situation, and also includes the situation where the difference between the actual total capacitance and the equivalent total capacitance is within the tolerance value.
In some embodiments, the method of obtaining the actual total capacitance may include: acquiring the layout area of each identified MOS tube capacitor layout; acquiring the sum of the layout areas of all identified MOS tube capacitor layouts based on the area of each layout; and acquiring the actual total capacitance based on the area sum of the layout and a standard capacitance, wherein the standard capacitance is a capacitance value corresponding to the standard MOS tube capacitance layout, and the channel width-length ratio of the standard MOS tube capacitance layout is 1. And determining the sum of the layout areas based on the width-to-length ratio of the identified capacitance identification layer.
Specifically, the standard capacitance of the standard MOS transistor capacitor layout is Cg, each MOS capacitor layout has an actual capacitance C = AREA Cg, and AREA is the product of the corresponding channel width and length, so that the sum of the actual capacitances of all the MOS capacitor layouts is the actual total capacitance. And, the actual total capacitance is actually obtained as the sum of the products of each channel width and length.
According to the verification method provided by the embodiment, different MOS tube capacitor layouts can be identified at one time, so that the time for verifying the consistency of the LVS is shortened, and the complexity for verifying the consistency of the LVS is reduced.
On the other hand, for the equivalent circuit diagram with only one MOS transistor, the capacitor layouts of the MOS transistors with different sizes can be arranged in different areas according to the layout space of the actual layout, so that the layout space is saved, the size of the integrated circuit is reduced, the development trend of miniaturization of the integrated circuit is met, and the difficulty of consistency verification of the LVS is not increased.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present application, and that various changes in form and details may be made therein without departing from the spirit and scope of the present application in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the application, and it is intended that the scope of the application be limited only by the claims appended hereto.
Claims (14)
1. A MOS transistor capacitor layout, comprising:
the working layer comprises an active layer, a gate layer, a source layer and a drain layer, wherein the source layer is positioned on one side of the gate layer, the drain layer is positioned on the other side of the gate layer, and the gate layer, the source layer and the drain layer are all positioned right above the active layer;
the capacitance identification layer at least covers partial area of the working layer.
2. The MOS transistor capacitance layout of claim 1, wherein the capacitance identification layer covers all regions of the working layer.
3. The MOS transistor capacitor layout of claim 2, wherein the capacitance identification layer comprises: the first identification layer is opposite to all areas of the working layer; and the second identification layer is positioned at the periphery of the working layer.
4. The MOS transistor capacitor layout of claim 1 or 2, wherein the capacitor identification layer is rectangular.
5. The MOS transistor capacitor layout as claimed in claim 4, wherein the capacitor identification layer has a first boundary extending along a first direction and a second boundary extending along a second direction, the first direction is perpendicular to the second direction, and two ends of the second boundary are respectively connected with one first boundary; the first boundary is flush with a boundary of the gate layer.
6. The MOS transistor capacitor layout of claim 5, wherein the second boundary is located at a periphery of the active layer.
7. The MOS transistor capacitor layout as claimed in claim 1, wherein the capacitor identification layer is rectangular, and the width-to-length ratio of the capacitor identification layer is the same as the channel width-to-length ratio of the MOS transistor corresponding to the working layer.
8. A method for forming a MOS transistor capacitor layout according to any of claims 1 to 7, comprising:
establishing a working layer, wherein the working layer comprises an active layer, a grid layer, a source layer positioned on one side of the grid layer and a drain layer positioned on the other side of the grid layer, and the grid layer, the source layer and the drain layer are all positioned right above the active layer;
and establishing a capacitance identification layer, wherein the capacitance identification layer at least covers partial area of the working layer.
9. The method of forming as defined in claim 8, wherein the method of creating the capacitive discrimination layer includes:
acquiring the channel width-length ratio of the MOS tube capacitor corresponding to the working layer;
and establishing the capacitance identification layer in a rectangular shape based on the channel width-length ratio, wherein the width-length ratio of the rectangular shape is the same as the channel width-length ratio.
10. A verification method for layout schematic diagram consistency is characterized by comprising the following steps:
constructing an equivalent circuit diagram of the equivalent total capacitance of the MOS tube capacitor;
constructing at least 2 MOS transistor capacitor layouts according to any of claims 1-7;
identifying all the MOS tube capacitor layouts based on the capacitor identification layer;
and acquiring the actual total capacitance of the identified capacitors corresponding to the MOS transistor capacitor layout, and verifying the consistency of the actual total capacitance and the equivalent total capacitance.
11. The verification method according to claim 10, wherein the method of constructing at least 2 of said MOS transistor capacitor layouts comprises:
and constructing at least 2 MOS tube capacitor layouts with different channel width-length ratios.
12. The verification method according to claim 11, wherein the capacitance identification layer is rectangular, and the width-to-length ratio of the capacitance identification layer is the same as the channel width-to-length ratio of the MOS transistor corresponding to the MOS transistor capacitance layout; identifying all MOS tube capacitor layouts, including:
and identifying the width-length ratio of the capacitance identification layer corresponding to each MOS tube capacitance layout, and taking the width-length ratio as the channel width-length ratio of the MOS tube corresponding to the MOS tube capacitance layout.
13. The verification method of claim 11, wherein the method of constructing an equivalent circuit diagram of equivalent total capacitance comprises:
and generating a single MOS tube based on the equivalent total capacitance, wherein the grid electrode of the MOS tube is connected with a working power supply, and the source electrode and the drain electrode are both grounded.
14. The verification method of claim 10, wherein the method of obtaining the actual total capacitance comprises:
acquiring the layout area of each identified MOS tube capacitor layout;
acquiring the sum of the layout areas of all the identified MOS tube capacitor layouts based on each layout area;
and acquiring the actual total capacitance based on the layout area sum and a standard capacitance, wherein the standard capacitance is a capacitance value corresponding to the standard MOS tube capacitance layout, and the standard MOS tube capacitance layout has a channel width-length ratio of 1.
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