CN116631999A - Circuit system and protective equipment with double grounding ends - Google Patents
Circuit system and protective equipment with double grounding ends Download PDFInfo
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- CN116631999A CN116631999A CN202210317350.5A CN202210317350A CN116631999A CN 116631999 A CN116631999 A CN 116631999A CN 202210317350 A CN202210317350 A CN 202210317350A CN 116631999 A CN116631999 A CN 116631999A
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- 230000001681 protective effect Effects 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 238000002955 isolation Methods 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims description 9
- 230000000694 effects Effects 0.000 abstract description 18
- 230000002457 bidirectional effect Effects 0.000 abstract description 6
- 230000005611 electricity Effects 0.000 abstract description 3
- 230000003068 static effect Effects 0.000 abstract description 3
- 101100489713 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND1 gene Proteins 0.000 description 35
- 101100489717 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) GND2 gene Proteins 0.000 description 35
- 125000006850 spacer group Chemical group 0.000 description 11
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 230000009977 dual effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000012530 fluid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
Abstract
The embodiment of the application provides a circuit system with double grounding ends and protective equipment, wherein the protective equipment mainly forms a bidirectional thyristor at the two grounding ends through a designed semiconductor structure, so that besides voltage isolation can be carried out on the two grounding ends, an electrostatic discharge path can be provided when the voltage difference of the grounding ends reaches a certain degree, thereby achieving the protection effect of electrostatic discharge and avoiding the circuit system from being damaged due to the impact of high-voltage static electricity.
Description
Technical Field
The present application relates to a protection device for a circuit system having dual ground terminals, and more particularly, to a protection device capable of isolating different ground terminals and achieving electrostatic protection, and a circuit system using the same.
Background
Referring to fig. 1, fig. 1 is a block diagram of a conventional circuit system. The circuit system 1 is an application of a driving device, and includes a front-end circuit 11 and a driving circuit 12. The front-end circuit 11 is electrically connected to the system voltage terminal VDD, and includes a low-side circuit 111 and a high-side circuit 112. The low-side circuit 111 and the high-side circuit 112 are electrically connected to the ground terminals GND1 and GND2, respectively, and the high-side circuit 112 is electrically connected to the driving circuit 12. The driving circuit 12 is electrically connected to the input signal terminal VIN and the output signal terminal VOUT.
In this application, due to the parasitic inductance of the circuit, the ground potential of the circuit is changed under high current operation, so that the different ground terminals GND1 and GND2 in the circuit system 1 are sometimes isolated to avoid the potential from being pulled. However, when the electrostatic discharge occurs, the two grounding terminals GND1 and GND2 are isolated from each other, and may block the electrostatic discharge, so that the static electricity cannot be dissipated, and the circuit system 1 is damaged.
Referring to fig. 1 and 2A, fig. 2A is a schematic cross-sectional view of a semiconductor structure of a conventional isolation device. Since the ground GND2 is usually operated under a large current, the parasitic inductance will cause the voltage of the ground GND2 to rise and generate a voltage difference with the ground GND1, and the circuit system 1 uses the isolation device formed by the semiconductor structure 21 of fig. 2A to isolate the two grounds GND1 and GND 2.
The semiconductor structure 21 includes a P-type substrate SUB, high-voltage wells HVW-HVW, wells W1-W7, doped regions D1-D11, gates G1, G2, and field spacers F1-F8, wherein the high-voltage wells HVW, HVW3 are high-voltage P-type wells, the high-voltage well HVW is a high-voltage N-type well, the wells W1, W3, W5, W7 are P-type wells, the wells W2, W4, W6 are N-type wells, the doped regions D1, D5, D7, and D11 are P-type doped regions, and the doped regions D2-D4, D8-D10 are N-type doped regions. The doped regions D4, D5 are electrically connected to the ground GND2, and the doped regions D7, D8 are electrically connected to the ground GND1. By the arrangement of the high pressure well HVW2, the wells W3 and W5 can be effectively isolated. The breakdown voltage values of the symmetrical semiconductor structure 21 in two directions (the direction from the ground GND1 to the ground GND2 and the direction from the ground GND2 to the ground GND 1) are the same.
Referring to fig. 1 and 2B, fig. 2B is a schematic cross-sectional view of a semiconductor structure of a conventional isolation device. The circuit system 1 may also use an isolation device formed as the semiconductor structure 22 of fig. 2B to achieve isolation of the two ground terminals GND1, GND 2. The semiconductor structure 22 includes a P-type substrate SUB, high-voltage wells HVW-HVW, wells W1-W7, doped regions D1-D9, gates G1, G2, and field spacers F1-F7, wherein the high-voltage wells HVW, HVW3 are high-voltage P-type wells, the high-voltage wells HVW2, HVW4 are high-voltage N-type wells, the wells W1, W3, W4, W6 are P-type wells, the wells W2, W5, W7 are N-type wells, the doped regions D1, D4, D6 are P-type doped regions, and the doped regions D2, D3, D5, D7-D9 are N-type doped regions. The doped regions D3, D4 are electrically connected to the ground GND2, and the doped regions D6, D7 are electrically connected to the ground GND1. By the arrangement of the high pressure wells HVW3, HVW4, the wells W3 and W6 can be effectively isolated. The breakdown voltage values of the asymmetric semiconductor structure 22 in two directions (the direction from the ground GND1 to the ground GND2 and the direction from the ground GND2 to the ground GND 1) are different from each other.
Regardless of the semiconductor structure of fig. 2A or fig. 2B, when the electrostatic discharge occurs, the two grounding terminals are isolated from each other to block the electrostatic discharge, so that the electrostatic discharge cannot be discharged, and the circuit system 1 is damaged. Therefore, there is a need to provide a protection device with isolation effect and capable of providing an electrostatic discharge path.
Disclosure of Invention
In order to solve the problems of the prior art and achieve at least one object of the present application, a protection device is provided, which is used for a circuit system having a first ground terminal and a second ground terminal and is composed of a semiconductor structure. The semiconductor structure comprises a first high-voltage P-type well, a first P-type doped region, a first N-type doped region, a first high-voltage N-type well, a second P-type doped region and a second N-type doped region, wherein the first P-type well, the first P-type doped region, the first N-type doped region, the first high-voltage N-type well, the second P-type doped region and the second N-type doped region are formed in the first high-voltage N-type well. The first P-type doped region and the first N-type doped region are formed in the first P-type well and exposed to the first P-type well, and are isolated from each other in the horizontal direction. The second P-type doped region and the second N-type doped region are formed in the second P-type well and exposed to the second P-type well, and are isolated from each other in the horizontal direction. The first N-type doped region is positioned on a first side of the first P-type well, which is close to the first high-voltage N-type well, the first P-type doped region is positioned on a second side of the first P-type well, which is far away from the first high-voltage N-type well, the second N-type doped region is positioned on a first side of the second P-type well, which is close to the first high-voltage P-type well, the second P-type doped region is positioned on a second side of the second P-type well, which is far away from the first high-voltage P-type well, the first N-type doped region and the second N-type doped region are isolated from each other in the horizontal direction, the first N-type doped region and the first P-type doped region are used for electrically connecting the second grounding end, and the second N-type doped region and the second P-type doped region are used for electrically connecting the first grounding end.
The embodiment of the application also provides a circuit system which comprises the protective equipment, a front-end circuit and a driving circuit. The front-end circuit comprises a low-voltage side circuit and a high-voltage side circuit. The driving circuit is electrically connected with the high-voltage side circuit.
In summary, the protection device provided by the present application has an isolation effect and can provide an esd path, and compared with the conventional isolation device with only two grounding terminals, the protection device provided by the present application can effectively protect the circuit system from being damaged by high voltage static electricity.
For a further understanding of the technology, means, and effects of the present application, reference should be made to the following detailed description and accompanying drawings so that the objects, features, and concepts of the application may be fully and specifically understood. However, the following detailed description and drawings are merely for purposes of reference and illustration of implementations of the application and are not intended to limit the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application to those skilled in the art, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a block diagram of conventional circuitry.
Fig. 2A is a schematic cross-sectional view of a semiconductor structure of a conventional isolation device.
Fig. 2B is a schematic cross-sectional view of a semiconductor structure of a conventional isolation device.
FIG. 3 is a block diagram of circuitry according to an embodiment of the present application.
Fig. 4 is a schematic cross-sectional view of a symmetrical semiconductor structure of a protective device according to an embodiment of the present application.
Fig. 5 is a graph of ground voltage difference versus current for an asymmetric semiconductor structure of a protective device according to an embodiment of the present application.
Fig. 6A is a schematic cross-sectional view of an asymmetric semiconductor structure of a protective device in accordance with an embodiment of the present application.
Fig. 6B is a schematic cross-sectional view of an asymmetric semiconductor structure of a protective device in accordance with another embodiment of the present application.
Fig. 6C is a schematic cross-sectional view of an asymmetric semiconductor structure of a protective apparatus according to yet another embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In addition, the practice of the exemplary embodiments is only one implementation of the design concept of the present application, and the following examples are not intended to limit the present application.
In order to solve the problems of the prior art, the present application provides a protection device having an isolation effect and capable of providing an esd path, which is used for providing an esd path when a voltage difference between the two grounding terminals reaches a certain level, so as to achieve an esd protection effect. Further, the protection device may provide a bidirectional esd path, that is, when the voltage value of the first ground terminal is greater than the voltage value of the second ground terminal and the voltage difference between the ground terminals is greater than the first turn-on voltage value, the protection device provides an esd path from the first ground terminal to the second ground terminal, and when the voltage value of the second ground terminal is greater than the voltage value of the first ground terminal and the voltage difference between the ground terminals is greater than the second turn-on voltage value, the protection device provides an esd path from the second ground terminal to the first ground terminal.
In one embodiment, the protection device is composed of symmetrical semiconductor structures, so that the first turn-on voltage value and the second turn-on voltage value are identical to each other. In another embodiment, the protection device is formed of an asymmetric semiconductor structure, and when the second ground is electrically connected to the high-side current operated at a high current, the first turn-on voltage is designed to be greater than the second turn-on voltage so as to provide an electrostatic discharge path without losing the isolation effect. The asymmetry here means that the electrical properties of the first grounding end and the second grounding end corresponding to the high-voltage well region are different, one is a high-voltage N-type well, the other is a high-voltage P-type well, and therefore the breakdown voltage from the first grounding end to the second grounding end is not the same as the breakdown voltage from the second grounding end to the first grounding end.
Referring to fig. 3, fig. 3 is a block diagram of a circuit system according to an embodiment of the application. The circuit system 3 includes a protection device 33, a front-end circuit 31 and a driving circuit 32, wherein a high-voltage side circuit 312 of the front-end circuit 31 is electrically connected to the driving circuit 32, the front-end circuit 31 is electrically connected to a system voltage terminal VDD, and a ground terminal GND1 and a ground terminal GND2 are electrically connected to a low-voltage side circuit 311 and a high-voltage side circuit 312 of the front-end circuit 31, respectively. The protection device 33 is electrically connected between the ground GND1 and the ground GND2, thereby isolating the ground GND1 from the ground GND2 and providing a bidirectional electrostatic discharge path for achieving the electrostatic discharge protection effect.
In the embodiment of the application, the semiconductor structure of the protection device 33 is designed, so that the semiconductor structure can generate an electrostatic discharge path when the voltage difference of the ground terminal reaches a certain level, so as to avoid damaging the circuit system 3. Further, the on-voltage must be less than the breakdown voltage and not lower than the isolation voltage, so that the protection device 33 of the semiconductor structure can have an isolation effect and provide an esd path.
Next, referring to fig. 3 and 4, fig. 4 is a schematic cross-sectional view of a symmetrical semiconductor structure of a protection device according to an embodiment of the application. The shielding device 33 of fig. 3 may be implemented with the symmetrical semiconductor structure 4 of fig. 4. The semiconductor structure 4 includes a P-type substrate SUB, high-voltage wells HVW1, wells W1 to W3, doped regions D1 to D5, and field spacers F1 to F6, wherein the high-voltage well HVW is a high-voltage N-type well, the wells W1, W3 are P-type wells, the well W2 is an N-type well, the doped regions D1, D5 are P-type doped regions, and the doped regions D2 to D4 are N-type doped regions. The doped regions D1, D2 are electrically connected to the ground GND2, and the doped regions D4, D5 are electrically connected to the ground GND1.
The high-pressure well HVW1 is formed on the P-type substrate SUB, and the wells W1 to W3 are sequentially formed in the high-pressure well HVW in the horizontal direction (left-to-right direction). The left and right sides of well W2 are immediately adjacent to the right side of well W1 and the left side of well W3. Doped regions D1, D2 are formed over well W1 and exposed to well W1, and doped regions D1, D2 are isolated from each other in the horizontal direction (by field separator F2). Doped regions D4, D5 are formed over well W3 and exposed to well W3, and doped regions D4, D5 are isolated from each other in the horizontal direction (by field separator F5). The doped region D3 is formed over the wells W1-W3 and is horizontally isolated from the doped regions D2 and D4 (by field spacers F3, F4). Field isolation F1 is located over high pressure well HVW and well W1, field isolation F2, F3 are formed over well W1, field isolation F4, F5 are formed over well W3, and field isolation F6 is located over high pressure well HVW and well W3.
Further, a portion of the field separator F1 is located on the left side of the high pressure well HVW1, and another portion of the field separator F1 is located on the left side of the well W1. Doped region D1 is located on the side of well W1 remote from well W2 (i.e., the left side of well W1), and the left side of doped region D1 is immediately adjacent to the right side of field isolation F1. The left and right sides of the field isolation member F2 are respectively adjacent to the right side of the doped region D1 and the left side of the doped region D2. Doped region D2 is located on the side of well W1 adjacent well W2 (i.e., to the right of well W1). The left and right sides of the field isolation member F3 are respectively adjacent to the right side of the doped region D2 and the left side of the doped region D3. The left portion of doped region D3 is located over well W1, the middle portion of doped region D3 is located over well W2, and the right portion of doped region D3 is located over well W3. The left and right sides of the field isolation member F4 are respectively adjacent to the right side of the doped region D3 and the left side of the doped region D4. Doped region D4 is located on the side of well W3 adjacent well W2 (i.e., the left side of well W3). The left and right sides of the field isolation member F5 are respectively adjacent to the right side of the doped region D4 and the left side of the doped region D5. Doped region D5 is located on the side of well W3 remote from well W2 (i.e., the right side of well W3), and the right side of doped region D5 is immediately to the left of field separator F6. A portion of the field separator F6 is located to the right of the well W3 and another portion of the field separator F1 is located to the right of the high pressure well HVW1.
The semiconductor structure 4 is a symmetrical structure, so that the on-voltage values in two directions (the direction from the ground terminal GND1 to the ground terminal GND2 and the direction from the ground terminal GND2 to the ground terminal GND 1) are the same as each other, and similarly, the voltage values isolated in the two directions are the same as each other and the breakdown voltage values in the two directions are the same as each other. Through the above semiconductor structure 4, when the voltage value of the ground terminal GND2 is greater than the voltage value of the ground terminal GND1 (or the voltage value of the ground terminal GND1 is greater than the voltage value of the ground terminal GND 2), and the voltage difference of the ground terminals between the two is greater than the turn-on voltage value, the PNPN thyristor formed between the ground terminals GND1 and GND2 is turned on to provide an esd path, thereby achieving esd protection. In addition, the doped region D3 on the well W2 is an N-type doped region, so that the turn-on voltage value can be reduced, so that the turn-on voltage value is not too high. In addition, the on-voltage value can be adjusted by the width of the doped region D3, so that the on-voltage value is not too high or too low by proper adjustment, so that the protection device 33 can have an isolation effect and provide an electrostatic discharge path.
Referring to fig. 5, fig. 5 is a graph of voltage difference versus current at the ground of an asymmetric semiconductor structure of a protection device according to an embodiment of the application. As shown in fig. 5, the regions R11, R12, R13 are isolation regions, on regions, and breakdown regions in the direction from the ground GND1 to the ground GND2, respectively. In the region R11, the ground terminals GND1 and GND2 are isolated from each other and are not conductive, so as to generate a voltage isolation effect. In the region R12, the thyristor is turned on in the semiconductor structure to provide an electrostatic discharge path from the ground GND1 to the ground GND2, and the turn-on curve is shown as curve C2. In region R13, the semiconductor structure may break down, resulting in damage to the component. Since an esd path from the ground GND1 to the ground GND2 is provided in the region R12, the semiconductor structure can be prevented from operating in the region R13.
The regions R21, R22, R23 are isolation regions, on regions, and breakdown regions in the direction from the ground GND2 to the ground GND1, respectively. In the region R21, the ground terminals GND2 and GND1 are isolated from each other and are not conductive, so as to generate a voltage isolation effect. In the region R22, the thyristor is turned on in the semiconductor structure to provide an electrostatic discharge path from the ground GND2 to the ground GND1, and the turn-on curve is shown as curve C3. In region R23, the semiconductor structure may break down, resulting in damage to the component. Since an esd path from the ground GND1 to the ground GND2 is provided in the region R22, the semiconductor structure can be prevented from operating in the region R23.
The conducting voltage values of the asymmetrical semiconductor structure must be designed to be different in two directions, and if the conducting voltage values are designed to be the same, the gate fluid in the semiconductor structure will be conducted in the direction from the ground terminal GND1 to the ground terminal GND2 in the region R11, and the conducting curve is as shown in the curve C1, so that the voltage isolation effect of the ground terminals GND1 and GND2 is poor. Therefore, the asymmetric semiconductor structure of the embodiment of the application is hoped to form a bidirectional thyristor, and the conducting voltage values in two directions are different from each other, so as to achieve better isolation effect and electrostatic discharge protection effect.
Referring to fig. 3 and 6A, fig. 6A is a schematic cross-sectional view of an asymmetric semiconductor structure of a protection device according to an embodiment of the application. The shielding device 33 of fig. 3 may be implemented with the asymmetric semiconductor structure 61 of fig. 6A. The semiconductor structure 61 includes a P-type substrate SUB, high-voltage wells HVW1, HVW, HVW3, wells W1 to W3, doped regions D1 to D5, and field spacers F1 to F5, wherein the high-voltage wells HVW1, HVW3 are high-voltage P-type wells, the high-voltage well HVW2 is a high-voltage N-type well, the wells W1 to W3 are P-type wells, the doped regions D1, D4, D5 are P-type doped regions, and the doped regions D2, D3 are N-type doped regions. The doped regions D1, D2, D5 are electrically connected to the ground GND2, and the doped regions D3, D4 are electrically connected to the ground GND1.
The high-pressure wells HVW to HVW3 are formed on the P-type substrate SUB. The well W1 is formed in the high-pressure well HVW1. Doped regions D1, D2 are formed in the well W1 and exposed to the well W1, and in the horizontal direction, the doped regions D1, D2 are isolated from each other by the field separator F2. The left side of the high pressure well HVW is horizontally immediately adjacent to the right side of the high pressure well W1. Well W2 is formed in high pressure well HVW2. Doped regions D3, D4 are formed in well W2 and are exposed to well W2. In the horizontal direction, the doped regions D3, D4 are isolated from each other by the field isolation F4. The left side of the high-pressure well HVW is next to the right side of the high-pressure well HVW in the horizontal direction. Well W3 is formed in high pressure well HVW 3. Doped region D5 is formed in well W3 and is exposed to well W3.
Doped region D2 is located on one side of well W1 near high pressure well HVW2 (i.e., to the right of well W1), and doped region D1 is located on the other side of well W1 away from high pressure well HVW2 (i.e., to the left of well W1). Doped region D3 is located on the side of well W2 near high pressure well HVW1 (i.e., the left side of well W2), and doped region D4 is located on the side of well W2 remote from high pressure well HVW1 (i.e., the right side of well W2). The doped regions D2 and D3 are isolated from each other in the horizontal direction by the field isolation F3. The doped region D5 is horizontally isolated from the doped region D4 by a field isolation F5.
A portion of the field isolation member F1 is formed on the high-voltage well HVW1, and the other portion of the field isolation member F1 is formed over the well W1 and is positioned on a side of the doped region D1 remote from the high-voltage well HVW (i.e., on the left side of the doped region D1) in the horizontal direction. The field spacers F2 are formed over the well W1 and are located between the doped regions D1, D2 in the horizontal direction. Portions of the field isolation F3 are formed in the well W1, the high-voltage wells HVW, HVW, and the well W2, respectively, and are located between the doped regions D2, D3 in the horizontal direction. The field spacers F4 are formed over the well W2 and are located between the doped regions D3, D4 in the horizontal direction. Portions of the field isolation member F5 are formed on the well W2, the high-voltage wells HVW, HVW, and the well W3, respectively, and are located on a side of the doped region D4 away from the high-voltage well HVW (i.e., on the right side of the doped region D4) in the horizontal direction.
The high voltage wells HVW, HVW2, the wells W1, W2, the doped regions D1-D4 and the field spacers F1-F5 form a bi-directional thyristor and can be used to isolate the voltage between the ground terminals GND2, GND1. When the voltage difference between the ground terminal GND1 and the ground terminal GND2 is positive and greater than the first turn-on voltage, the bidirectional thyristor formed by the semiconductor structure 61 provides an electrostatic discharge path from the ground terminal GND1 to the ground terminal GND 2. When the voltage difference between the ground terminal GND2 and the ground terminal GND1 is positive and greater than the second turn-on voltage, the bidirectional thyristor formed by the semiconductor structure 61 provides an electrostatic discharge path from the ground terminal GND2 to the ground terminal GND1. In this embodiment, since the ground GND2 is electrically connected to the high-voltage side circuit 312 and the ground GND1 is electrically connected to the low-voltage side circuit 311, the first turn-on voltage is larger than the second turn-on voltage as shown in fig. 5. In the embodiment of the present application, the portions constituting the bi-directional thyristor are composed of the high-pressure wells HVW, HVW2, the wells W1, W2, the doped regions D1 to D4, and the field spacers F1 to F5. In other words, the doped region D4, the high-voltage well HVW, the well W3 and the P-type substrate SUB may be unnecessary components of the present application and can be removed.
Referring to fig. 3 and 6B, fig. 6B is a schematic cross-sectional view of an asymmetric semiconductor structure of a protection device according to another embodiment of the application. Unlike the embodiment of fig. 6A, semiconductor structure 62 further includes well W4. Well W4 is an N-well formed in high-pressure well HVW2 and is horizontally adjacent to well W2 and high-pressure well HVW1. The high voltage wells HVW, HVW2, the wells W1, W2, W4, the doped regions D1-D4 and the field spacers F1-F5 form a bi-directional thyristor, and similarly have voltage isolation and electrostatic discharge protection effects.
Referring to fig. 3 and 6C, fig. 6C is a schematic cross-sectional view of an asymmetric semiconductor structure of a protection device according to another embodiment of the application. Unlike the embodiment of fig. 6B, the semiconductor structure 63 further includes a doped region D6 and a field isolation F6. The doped region D6 is an N-type doped region, and portions of the doped region D6 are formed on the high-pressure wells HVW, W4 and HVW and exposed to the high-pressure wells HVW1, W4 and HVW2, respectively. The field separator F6 is formed on the well W2, and the field separator F3 is formed only on the well W1 and the high-pressure well HVW1. In the horizontal direction, the field separator F3 is used to isolate the doped regions D2 and D6, and the field separator F6 is used to isolate the doped regions D6 and D3. The high-voltage wells HVW, HVW2, the wells W1, W2, W4, the doped regions D1-D4, D6 and the field spacers F1-F6 form a bi-directional thyristor, and similarly have voltage isolation and electrostatic discharge protection effects.
In view of the foregoing, embodiments of the present application provide a protection device implemented by a semiconductor structure, which may be used in a circuit system with dual grounding terminals, and may perform voltage isolation on two grounding terminals, and may achieve an electrostatic discharge protection effect. The implementation mode of the semiconductor structure of the embodiment of the application is not complex and difficult, so that the semiconductor structure can be produced in mass and widely applied to various circuit systems with double grounding terminals, and has economic value and industrial applicability.
It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Claims (11)
1. A protective device for use in a circuit system having a first ground and a second ground, the protective device comprising a semiconductor structure, the semiconductor structure comprising:
a first high pressure P-well;
the first P-type well is formed in the first high-voltage P-type well;
the first P-type doped region and the first N-type doped region are formed in the first P-type well and exposed to the first P-type well, and the first P-type doped region and the first N-type doped region are isolated from each other in the horizontal direction;
a first high voltage N-well adjacent to the first high voltage P-well in the horizontal direction;
a second P-type well formed in the first high-voltage N-type well; and
a second P-type doped region and a second N-type doped region, wherein the second P-type doped region and the second N-type doped region are formed in and exposed to the second P-type well, and are isolated from each other in a horizontal direction;
the first P-type well is located on a first side of the first P-type well, the first P-type doped region is located on a second side of the first P-type well, the second P-type doped region is located on a first side of the second P-type well, the second P-type doped region is located on a second side of the second P-type well, the second P-type doped region is located on the first side of the first P-type well, the first N-type doped region and the second N-type doped region are isolated from each other in the horizontal direction, the first N-type doped region and the first P-type doped region are used for being electrically connected with the second ground terminal, and the second N-type doped region and the second P-type doped region are used for being electrically connected with the first ground terminal.
2. The protective apparatus of claim 1, wherein the semiconductor structure further comprises a P-type substrate, wherein the first high voltage P-type well and the first high voltage N-type well are formed on the P-type substrate.
3. The protective apparatus of claim 1, wherein the semiconductor structure further comprises:
the first field isolation piece is formed on the first high-voltage P-type well and the first P-type well and is positioned at one side of the first P-type doped region far away from the first high-voltage N-type well in the horizontal direction; and
the second field isolation piece is formed on the first high-voltage N-type well and the second P-type well and is positioned on one side of the second P-type doped region far away from the first high-voltage P-type well in the horizontal direction.
4. The protective apparatus of claim 1, wherein the semiconductor structure further comprises:
a third field isolation element formed on the first P-type well and located between the first P-type doped region and the first N-type doped region in the horizontal direction;
the fourth field isolation piece is formed on the first high-voltage P-type well, the first high-voltage N-type well and the second P-type well and is positioned between the first N-type doping region and the second N-type doping region in the horizontal direction; and
and a fifth field isolation element formed on the second P-type well and located between the second N-type doped region and the second P-type doped region in the horizontal direction.
5. The protective apparatus of claim 1, wherein the semiconductor structure further comprises:
a second high voltage P-well adjacent to the first high voltage N-well in the horizontal direction;
a third P-type well formed in the second high-voltage P-type well; and
the third P-type doped region is formed in the third P-type well and exposed to the third P-type well, the third P-type doped region is isolated from the second N-type doped region in the horizontal direction, and the third P-type doped region is electrically connected with the second grounding end.
6. The protective apparatus of claim 1, wherein the semiconductor structure further comprises:
the N-type well is formed in the first high-voltage N-type well and is adjacent to the second P-type well and the first high-voltage P-type well in the horizontal direction.
7. The protective apparatus of claim 6, wherein the semiconductor structure further comprises:
and a third N-type doped region formed on the N-type well, the first high-voltage N-type well and the first high-voltage P-type well, exposed to the N-type well, the first high-voltage N-type well and the first high-voltage P-type well, and isolated from the first N-type doped region and the second N-type doped region in the horizontal direction.
8. The protective apparatus of claim 1, wherein the semiconductor structure provides an electrostatic discharge path from the first ground to the second ground when a ground voltage difference from the first ground to the second ground is positive and greater than a first turn-on voltage value, and provides an electrostatic discharge path from the second ground to the first ground when a ground voltage difference from the second ground to the first ground is positive and greater than a second turn-on voltage value.
9. The protective apparatus of claim 8 wherein the first turn-on voltage value is greater than the second turn-on voltage value.
10. A circuit system, the circuit system comprising:
the protective apparatus of one of claims 1 to 9;
the front-end circuit comprises a low-voltage side circuit and a high-voltage side circuit; and
and the driving circuit is electrically connected with the high-voltage side circuit.
11. The circuitry of claim 10, wherein the first ground is electrically connected to the low side circuit and the second ground is electrically connected to the high side circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111105098A TWI790119B (en) | 2022-02-11 | 2022-02-11 | Protection apparatus used in circuit system having dual ground terminals |
| TW111105098 | 2022-02-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116631999A true CN116631999A (en) | 2023-08-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210317350.5A Pending CN116631999A (en) | 2022-02-11 | 2022-03-29 | Circuit system and protective equipment with double grounding ends |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116631999A (en) |
| TW (1) | TWI790119B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI827466B (en) * | 2023-02-14 | 2023-12-21 | 新唐科技股份有限公司 | Esd protection device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7834400B2 (en) * | 2007-05-11 | 2010-11-16 | System General Corp. | Semiconductor structure for protecting an internal integrated circuit and method for manufacturing the same |
| TWI416697B (en) * | 2009-10-21 | 2013-11-21 | Silicon Motion Inc | Electrostatic discharge (esd) protection device |
| US8324658B2 (en) * | 2010-02-01 | 2012-12-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit for RFID tag |
| WO2014041388A1 (en) * | 2012-09-12 | 2014-03-20 | Freescale Semiconductor, Inc. | A semiconductor device and an integrated circuit comprising an esd protection device, esd protection devices and a method of manufacturing the semiconductor device |
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- 2022-02-11 TW TW111105098A patent/TWI790119B/en active
- 2022-03-29 CN CN202210317350.5A patent/CN116631999A/en active Pending
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| TW202333337A (en) | 2023-08-16 |
| TWI790119B (en) | 2023-01-11 |
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