CN116631874A - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN116631874A CN116631874A CN202310240166.XA CN202310240166A CN116631874A CN 116631874 A CN116631874 A CN 116631874A CN 202310240166 A CN202310240166 A CN 202310240166A CN 116631874 A CN116631874 A CN 116631874A
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- 238000002360 preparation method Methods 0.000 title abstract description 10
- 239000003989 dielectric material Substances 0.000 claims abstract description 78
- 238000000034 method Methods 0.000 claims abstract description 71
- 238000005468 ion implantation Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims description 105
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 10
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- 238000001039 wet etching Methods 0.000 claims description 7
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- 125000006850 spacer group Chemical group 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
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- 238000005229 chemical vapour deposition Methods 0.000 description 10
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- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- -1 boron ions Chemical class 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
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- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
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- FEWHDZOJQQLPEN-UHFFFAOYSA-N [O].[N].[O] Chemical group [O].[N].[O] FEWHDZOJQQLPEN-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 2
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
- H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
Abstract
The invention provides a semiconductor device and a preparation method thereof, wherein the method comprises the following steps: providing a substrate, and forming an epitaxial layer on the substrate; forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer; performing a first ion implantation to form a first conductive type well region in the epitaxial layer; forming a side wall on the side wall of the pseudo gate structure, and performing second ion implantation to form a second conductivity type source region in the first conductivity type well region; forming a dielectric material layer covering the gate dielectric layer; removing the pseudo gate structure; and forming an isolation layer on the side wall of the side wall, and performing third ion implantation to form a JFET region in the epitaxial layer. The method can effectively reduce the overlay accuracy deviation caused by secondary photoetching, further ensure the stability of parameters, select low-energy injection, and simultaneously can not influence a channel, thereby reducing the resistance of the JFET region.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
In the process of manufacturing Junction Field-Effect Transistor (JFET), two ion implantation methods are mainly used, one is to use a photomask as a barrier layer for selective implantation, and the other is to use a Blank ion implantation method.
The first way has the disadvantage that the overlay accuracy (overlay) deviation exists in the two times of lithography, so that the resistance of the JFET region cannot be effectively reduced, and the channel is influenced; the second approach has the disadvantage that the implant energy cannot be too low, otherwise it can affect the surface channel, resulting in an inefficient reduction of the resistance of the JFET region.
In view of the above, the present invention provides a new semiconductor device and a method for manufacturing the same, which at least partially solve the above problems.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the problems existing at present, an aspect of the present invention provides a method for manufacturing a semiconductor device, including:
Providing a substrate, and forming an epitaxial layer on the substrate;
forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
performing first ion implantation to form a first conductive type well region in the epitaxial layer;
forming a side wall on the side wall of the pseudo gate structure, and performing second ion implantation to form a second conductivity type source region in the first conductivity type well region;
forming a dielectric material layer covering the gate dielectric layer;
removing the pseudo gate structure;
and forming an isolation layer on the side wall of the side wall, and performing third ion implantation to form a JFET region in the epitaxial layer.
Illustratively, the gate dielectric layer includes an oxide layer, the dummy gate structure includes a bottom-up disposed dummy gate material layer including a nitride layer, and a gate hard mask layer including an oxide layer.
Illustratively, forming a sidewall of the dummy gate structure includes:
depositing a sidewall material on the gate dielectric layer and the dummy gate structure;
and etching back the side wall material, wherein the side wall material remained on the side wall of the pseudo grid electrode structure is the side wall.
Illustratively, the forming a layer of dielectric material overlying the gate dielectric layer, removing the dummy gate structure, includes:
depositing a dielectric material on the gate dielectric layer, the side wall and the dummy gate structure;
performing chemical mechanical polishing on the dielectric material until the pseudo gate structure is exposed, wherein the dielectric material left on the gate dielectric layer is the dielectric material layer;
and removing the pseudo gate material layer.
The dummy gate material layer is illustratively removed by a high selectivity wet etch.
Illustratively, the forming an isolation layer on the sidewall of the sidewall includes:
depositing isolation layer materials on the dielectric material layer, the side wall of the side wall and the grid dielectric layer;
and removing the isolation layer materials on the dielectric material layer and the gate dielectric layer, and reserving the isolation layer materials on the side wall of the side wall so as to form the isolation layer on the side wall of the side wall.
In still another aspect, the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate, and forming an epitaxial layer on the substrate;
forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
Forming a side wall on the side wall of the pseudo gate structure, and performing first ion implantation to form a JFET region in the epitaxial layer;
forming a dielectric material layer covering the gate dielectric layer;
removing the pseudo gate structure;
performing a second ion implantation to form a first conductivity type well region in the epitaxial layer;
and forming an isolation layer on the side wall of the first side wall, and performing third ion implantation to form a second conduction type source region in the first conduction type well region.
The invention also provides a semiconductor device prepared by the preparation method of the semiconductor device.
Illustratively, the semiconductor device comprises a junction field effect transistor device.
According to the semiconductor device and the preparation method thereof, the first ion implantation, the second ion implantation and the third ion implantation are connected in series through the self-alignment process, and compared with a mode of adopting a photomask as a blocking layer for selective implantation, the semiconductor device can effectively reduce overlay precision deviation caused by secondary photoetching, and further ensure parameter stability; compared with a Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the resistance of the JFET region can be reduced.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.
In the accompanying drawings:
fig. 1 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2A to 2L are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, which is sequentially carried out to the obtained structure;
fig. 3 is a flowchart showing a method of manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 4A to 4J are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, which is sequentially carried out to the obtained structure.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.
It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Two ion implantation modes mainly exist in the preparation process of the junction field effect transistor, one is to adopt a photomask as a blocking layer for selective implantation, but the alignment precision deviation exists in the two times of photoetching, so that the resistance of the junction field effect transistor cannot be effectively reduced, and the influence on a channel can be caused; secondly, a Blank ion implantation mode is adopted, but implantation energy cannot be too low, otherwise a surface layer channel is affected, and the resistance of the junction field effect transistor cannot be effectively reduced.
Accordingly, in view of the foregoing technical problems, the present invention proposes a method for manufacturing a semiconductor device, as shown in fig. 1, including:
s110, providing a substrate, and forming an epitaxial layer on the substrate;
s120, forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
s130, performing first ion implantation to form a first conductive type well region in the epitaxial layer;
s140, forming a side wall on the side wall of the pseudo gate structure, and performing second ion implantation to form a second conduction type source region in the first conduction type well region;
s150, forming a dielectric material layer covering the gate dielectric layer;
S160, removing the pseudo gate structure;
s170, forming an isolation layer on the side wall of the side wall, and performing third ion implantation to form a JFET region in the epitaxial layer.
According to the preparation method of the semiconductor device, the first ion implantation for forming the first conductive type well region, the second ion implantation for forming the second conductive type source region and the third ion implantation for forming the JFET region are connected in series through the self-alignment process, and compared with a mode of adopting a photomask as a blocking layer for selective implantation, the preparation method of the semiconductor device can effectively reduce overlay precision deviation caused by secondary photoetching, and further ensure the stability of parameters; compared with a Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the resistance of the JFET region can be reduced.
In the following description, for a thorough understanding of the present invention, detailed steps and structures will be presented in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
Example 1
Next, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to fig. 2A to 2L, wherein fig. 2A to 2L show schematic cross-sectional views of semiconductor devices obtained by sequentially carrying out the method for manufacturing a semiconductor device according to one embodiment of the present invention.
Illustratively, the method of fabricating a semiconductor device of the present application includes the steps of:
first, step S110 is performed, as shown in fig. 2A, a substrate 201 is provided, and an epitaxial layer 203 is formed on the substrate 201.
In particular, the substrate 201 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or may be ceramic substrates such as alumina, quartz, or glass substrates, or the like.
In some embodiments of the present application, substrate 201 may be a single layer of semiconductor material, such as a silicon carbide substrate or the like.
On the substrate 201, the epitaxial layer 203 may be formed by an epitaxial growth process such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, and the like. The material of the epitaxial layer 203 may be the same as or different from the material of the substrate 201. Illustratively, the material of the epitaxial layer 203 is any suitable material such as silicon carbide.
In some embodiments of the present application, as shown in fig. 2A, before forming the epitaxial layer 203, a buffer layer 202 may also be formed on the substrate 201, where the buffer layer 202 is located between the substrate 201 and the epitaxial layer 203, and the buffer layer 202 can enable a better concentration matching between the epitaxial layer 203 and the substrate 201, so that the doping concentration of the epitaxial layer 203 can be accurately controlled during the growth process.
Next, step S120 is performed, as shown in fig. 2B, a gate dielectric layer 204 is formed on the epitaxial layer 203, and dummy gate structures are formed on the gate dielectric layer 204 at intervals.
In one example, a gate dielectric layer 204 is formed on the epitaxial layer 203, and dummy gate structures are formed on the gate dielectric layer 204 at intervals. Wherein the dummy gate structure includes a dummy gate material layer 205 and a gate hard mask layer 206 disposed from bottom to top.
The gate dielectric layer 204 may comprise, among other things, conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer 204 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. The gate dielectric layer 204 may be formed using any of several methods suitable for the material of the gate dielectric layer composition. Including, but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, and physical vapor deposition methods.
The dummy gate material layer 205 may include one or more of an oxide layer, a nitride layer, and an oxynitride layer. The formation process of the dummy gate material layer may employ any existing technique known to those skilled in the art, such as physical vapor deposition method, chemical vapor deposition method, or magnetron sputtering.
In one example, as shown in fig. 2B, the gate dielectric layer 204 is an oxide layer, the dummy gate material layer 205 is a nitride layer, such as a silicon nitride layer, the gate hard mask layer 206 is an oxide layer, and the gate dielectric layer 204 and the dummy gate structure together form an ONO (oxygen-nitrogen-oxygen) structure.
Next, step S130 is performed, and as shown in fig. 2C, a first ion implantation is performed to form a first conductivity type well region 207 in the epitaxial layer 203.
Specifically, with the dummy gate structure formed in step S120 as a mask, well region implantation windows (not shown in the figure) for defining well regions to be formed are formed on both sides of the dummy gate structure. A first ion implantation is performed using the dummy gate structure as a mask to form a well region 207 of the first conductivity type on the surface layer of the epitaxial layer 203 on both sides of the dummy gate structure. Wherein the first conductivity type ions may be boron ions, boron fluoride ions, or the like, and the implantation direction may be perpendicular to the surface of the epitaxial layer 203.
Next, step S140 is performed, as shown in fig. 2D to 2F, a sidewall 209 is formed on the sidewall of the dummy gate structure, and a second ion implantation is performed to form a second conductivity type source region 210 in the first conductivity type well region 207.
In one example, as shown in fig. 2D and fig. 2E, forming a sidewall 209 on a sidewall of the dummy gate structure includes: depositing sidewall material 208 over the gate dielectric layer 204 and over the dummy gate structure; and etching back the side wall material 208, wherein the side wall material 208 remained on the side wall of the pseudo gate structure is the side wall 209.
The sidewall material 208 may be deposited on the gate dielectric layer 204 and on the dummy gate structure by any conventional technique known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, etc., and the sidewall material 208 covers the entire device surface. The sidewall material 208 is, for example, polysilicon, silicon nitride, silicon oxide, silicon oxynitride, or the like. Here, polysilicon is preferably deposited by isotropic CVD, which, under the influence of the gate dielectric layer 204 and the oxide layer 206 in the dummy gate structure, forms the topography of fig. 2D.
In the process of etching back the sidewall material 208, the surface of the dummy gate structure is exposed, i.e., the sidewall material 208 on the surface of the dummy gate structure is etched completely. Those skilled in the art will understand that when the etching back is completed, the sidewall material 208 on the surface of the dummy gate structure is just etched completely, and only the sidewalls 209 are left on both sides of the dummy gate structure. The back etching process of the sidewall material 208 may be wet etching or dry etching, for example, when the sidewall material 208 is polysilicon, the back etching process may be performed by wet etching using a polysilicon etching solution, where the polysilicon etching solution may be formed by mixing nitric acid and hydrofluoric acid.
After forming the sidewall 209, a source region implantation window (not shown in the figure) for defining a source region to be formed is formed on both sides of the mask by using the sidewall 209 and the dummy gate structure as the mask. As shown in fig. 2F, a second ion implantation is performed using the sidewall 209 and the dummy gate structure as a mask, so as to form a source region 210 of a second conductivity type on the surface layer of the well region 207 of the first conductivity type on both sides of the mask. Wherein the second conductivity type ions may be phosphorus ions, arsenic ions, etc., and the implantation direction may be perpendicular to the surface of the epitaxial layer 203.
Next, step S150 is performed, and as shown in fig. 2G and fig. 2H, a dielectric material layer 212 is formed to cover the gate dielectric layer 204.
The dielectric material layer 212 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), among others. Alternatively, the dielectric material layer 212 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). The dielectric material layer 212 may be formed using any of several methods suitable for the material of the dielectric material layer composition. Including, but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, and physical vapor deposition methods.
In one example, as shown in fig. 2G and 2H, a dielectric material 211 is deposited on the gate dielectric layer 204, on the sidewalls, and on the dummy gate structure, the dielectric material 211 covering the entire device surface. Subsequently, chemical Mechanical Polishing (CMP) is performed to remove the dielectric material 211 on the dummy gate structure, and Chemical Mechanical Polishing (CMP) is performed to remove the gate hard mask layer 206 until the dummy gate material layer 205 is exposed, the dielectric material 211 remains as the dielectric material layer 212, and the dielectric material layer 212 is flush with the dummy gate material layer 205, as shown in fig. 2H. Wherein the dielectric material 211 may be an oxide.
Next, step S160 is performed, as shown in fig. 2G to 2H, to remove the dummy gate structure.
After the gate hard mask layer 206 is removed by Chemical Mechanical Polishing (CMP) until the dummy gate material layer 205 is exposed, the dummy gate material layer 205 is removed by wet etching with a high selectivity. In an embodiment of the present application, the dummy gate material layer 205 and the dielectric material layer 212 have a high etch selectivity. When the dummy gate material layer 205 is silicon nitride, a heat of 180deg.C, 85% H may be used 3 P0 4 Solution removal of the nitrogenAnd (5) a silicon layer.
Next, step S170 is performed, as shown in fig. 2J to 2L, an isolation layer 214 is formed on the sidewall of the sidewall 209, and a third ion implantation is performed to form a JFET region 215 in the epitaxial layer 203.
In one example, as shown in fig. 2J and fig. 2K, forming an isolation layer 214 on a sidewall of the sidewall 209 includes: depositing an isolation layer material 213 on the dielectric material layer 212, on the sidewalls of the sidewalls 209 and on the gate dielectric layer 204; and removing the isolation layer material 213 on the dielectric material layer 212 and the gate dielectric layer 204, and retaining the isolation layer material 213 on the sidewall of the sidewall 209 to form the isolation layer 214 on the sidewall of the sidewall 209.
Any prior art methods known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, etc., may be used to deposit the isolation layer material 213 on the dielectric material layer 212, on the sidewalls of the sidewall 209, and on the gate dielectric layer 204, where the isolation layer material 213 covers the entire device surface. The isolation layer material 213 is, for example, polysilicon, silicon nitride, silicon oxide, silicon oxynitride, or the like. Here, polysilicon is deposited, preferably by isotropic CVD, which will form the topography of FIG. 2J.
In the process of removing the isolation layer material 213, the surface of the dielectric material layer 212 is exposed, i.e., the isolation layer material 213 on the surface of the dielectric material layer 212 is completely etched. Those skilled in the art will appreciate that when the spacer material 213 on the surface of the dielectric material layer 212 is completely etched, the spacer material 213 on the surface of the gate dielectric layer 204 can just be completely etched, and only the spacer 214 remains on the sidewall of the sidewall 209.
It should be noted that, when the isolation layer material 213 is deposited on the dielectric material layer 212, the sidewall of the sidewall 209, and the gate dielectric layer 204, the isolation layer material 213 is inevitably deposited on the upper surface of the sidewall 209, and the thickness of the isolation layer material 213 is consistent with the thickness of the isolation layer material 213 on the dielectric material layer 212. When the silicon of the isolation layer 213 on the surface of the dielectric layer 212 is removed, the isolation layer 213 on the upper surface of the sidewall 209 may be removed.
Then, as shown in fig. 2L, a third ion implantation may be performed to form a JFET region 215 on the surface layer of the epitaxial layer 203 in the region corresponding to the dummy gate structure. Wherein the third conductivity type ions may be n-type ions and the implantation direction may be perpendicular to the surface of the epitaxial layer 203.
In some embodiments of the present application, the second conductivity type is n-type for an n-type trench semiconductor device, the first conductivity type is p-type, and the second conductivity type is p-type for a p-type trench semiconductor device, the first conductivity type is n-type. Among them, p-type impurities or ions are boron, boron fluoride, and the like, and n-type impurities or ions are phosphorus, and the like.
It should be noted that the order of the steps is merely an example, and the order of the steps may be exchanged or alternatively performed without conflict.
In summary, in the method for manufacturing a semiconductor device of the present invention, the first ion implantation for forming the well region of the first conductivity type, the second ion implantation for forming the source region of the second conductivity type, and the third ion implantation for forming the JFET region are connected in series by the self-alignment process, so that compared with the method of selectively implanting by using a photomask as a blocking layer, the method of the present invention can effectively reduce the overlay accuracy deviation caused by the secondary photolithography, thereby ensuring the stability of parameters; compared with a Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the resistance of the JFET region can be reduced.
Example two
The invention also provides a preparation method of the semiconductor device, as shown in fig. 3, comprising the following steps:
s310, providing a substrate, and forming an epitaxial layer on the substrate;
s320, forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
s330, forming a side wall on the side wall of the pseudo gate structure, and performing first ion implantation to form a JFET region in the epitaxial layer;
s340, forming a dielectric material layer covering the gate dielectric layer;
S350, removing the pseudo gate structure;
s360, performing second ion implantation to form a first conductive type well region in the epitaxial layer;
and S370, forming an isolation layer on the side wall of the first side wall, and performing third ion implantation to form a second conduction type source region in the first conduction type well region.
To further explain the method of manufacturing the semiconductor device, the above manufacturing method is described in detail below with reference to fig. 4A to 4J.
First, step S310 is performed, as shown in fig. 4A, a substrate 401 is provided, and an epitaxial layer 403 is formed on the substrate 401.
In particular, the substrate 401 may be any suitable semiconductor substrate, such as a bulk silicon substrate, which may also be at least one of the materials mentioned below: si, ge, siGe, siC, siGeC, inAs, gaAs, inP or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or may be ceramic substrates such as alumina, quartz, or glass substrates, or the like.
In some embodiments of the present application, substrate 401 may be a single layer of semiconductor material, such as a silicon carbide substrate or the like.
On the substrate 401, the epitaxial layer 403 may be formed by an epitaxial growth process such as vapor phase epitaxy, liquid phase epitaxy, molecular beam epitaxy, and the like. The material of the epitaxial layer 403 may be the same as or different from the material of the substrate 401. Illustratively, the material of epitaxial layer 403 is any suitable material such as silicon carbide.
In some embodiments of the present application, as shown in fig. 4A, a buffer layer 402 may also be formed on the substrate 401 before the epitaxial layer 403 is formed, where the buffer layer 402 is located between the substrate 401 and the epitaxial layer 403, and the buffer layer 402 can enable a better concentration matching between the epitaxial layer 403 and the substrate 401, so that the doping concentration of the epitaxial layer 403 can be accurately controlled during the growth process.
Next, step S320 is performed, as shown in fig. 4B, a gate dielectric layer 404 is formed on the epitaxial layer 403, and dummy gate structures are formed on the gate dielectric layer 404 at intervals.
In one example, a gate dielectric layer 404 is formed on the epitaxial layer 403, and dummy gate structures are formed on the gate dielectric layer 404 at intervals. Wherein the dummy gate structure includes a dummy gate material layer 405 and a gate hard mask layer 406 disposed from bottom to top.
The gate dielectric layer 404 may comprise, among other things, conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, the gate dielectric layer 404 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. The gate dielectric layer 404 may be formed using any of several methods suitable for the material of the gate dielectric layer composition. Including, but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, and physical vapor deposition methods.
The dummy gate material layer may include one or more of an oxide layer, a nitride layer, and an oxynitride layer. The formation process of the dummy gate material layer may employ any existing technique known to those skilled in the art, such as physical vapor deposition method, chemical vapor deposition method, or magnetron sputtering.
In one example, as shown in fig. 4B, the gate dielectric layer 404 is an oxide layer, the dummy gate material layer 405 is a nitride layer, such as a silicon nitride layer, the gate hard mask layer 406 is an oxide layer, and the gate dielectric layer 404 and the dummy gate structure together form an ONO (oxygen-nitrogen-oxygen) structure.
Next, step S330 is performed, as shown in fig. 4C and fig. 4D, a sidewall 407 is formed on the sidewall of the dummy gate structure, and a first ion implantation is performed to form a JFET region 408 in the epitaxial layer 403.
In one example, forming the sidewall 407 on the sidewall of the dummy gate structure includes: depositing sidewall material on the gate dielectric layer 404 and on the dummy gate structure; and etching back the side wall material, wherein the side wall material remained on the side wall of the pseudo gate structure is the side wall 407.
The sidewall material may be deposited on the gate dielectric layer 404 and on the dummy gate structure by any of the conventional techniques known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, etc., and covers the entire device surface. The side wall material is polysilicon, silicon nitride, silicon oxide or silicon oxynitride, for example. Here, polysilicon is preferably deposited by isotropic CVD.
In the process of etching back the side wall material, the surface of the pseudo gate structure is exposed, namely the side wall material on the surface of the pseudo gate structure is completely etched. Those skilled in the art will understand that when the etching back is completed, the sidewall material on the surface of the dummy gate structure can be etched completely, and only the sidewall 407 is left on two sides of the dummy gate structure. The back etching process of the side wall material can adopt wet etching or dry etching, for example, when the side wall material is polysilicon, the back etching process can adopt polysilicon etching liquid for wet etching, and the polysilicon etching liquid can be formed by mixing nitric acid and hydrofluoric acid.
After forming the sidewall 407, JFET region implantation windows (not shown) for defining JFET regions 408 to be formed are formed in regions between adjacent masks, using the sidewall 407 and the dummy gate structure as masks. As shown in fig. 4D, a first ion implantation is performed using the sidewall 407 and the dummy gate structure as masks, so as to form a JFET region 408 on the surface layer of the epitaxial layer 403 corresponding to the region between adjacent masks. Wherein the first conductivity type ions may be n-type ions or the like, and the implantation direction may be perpendicular to the surface of the epitaxial layer 403.
Next, step S340 is performed, and as shown in fig. 4E and fig. 4F, a dielectric material layer 410 is formed to cover the gate dielectric layer 404.
The dielectric material layer 410 may include, among other things, conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum). Alternatively, the dielectric material layer 410 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant electrolyte materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium Strontium Titanate (BSTs), and lead zirconate titanate (PZTs). The dielectric material layer 410 may be formed by any of several methods that are suitable for the material of the composition of the dielectric material layer 410. Including, but not limited to, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, and physical vapor deposition methods.
In one example, as shown in fig. 4E and 4F, a dielectric material 409 is deposited over the gate dielectric layer 404, over the sidewalls 407, and over the dummy gate structure, the dielectric material 409 covering the entire device surface. Subsequently, chemical Mechanical Polishing (CMP) is performed to remove the dielectric material 409 on the dummy gate structure, and the Chemical Mechanical Polishing (CMP) is performed to remove the gate hard mask layer 406 until the dummy gate material layer 405 is exposed, where the dielectric material 409 remains as the dielectric material layer 410, and the dielectric material layer 410 is flush with the dummy gate material layer 405, as shown in fig. 4F. Wherein the dielectric material 409 may be an oxide.
Next, step S350 is performed, as shown in fig. 4G, to remove the dummy gate structure.
After the gate hard mask layer 206 is removed by Chemical Mechanical Polishing (CMP) until the dummy gate material layer 405 is exposed, the dummy gate material layer 405 is removed by wet etching with a high selectivity. In an embodiment of the present application, the dummy gate material layer 405 and the dielectric material layer 410 have a high etch selectivity. When the dummy gate material layer 405 is silicon nitride, a heat of 180deg.C, 85% H may be used 3 P0 4 And removing the silicon nitride layer by the solution.
Next, step S360 is performed, and as shown in fig. 4H, a second ion implantation is performed to form a first conductivity type well region 411 in the epitaxial layer 403.
Specifically, with the dielectric material layer 410 and the sidewall 407 formed in the above steps as masks, well region implantation windows (not shown in the figure) for defining well regions to be formed are formed on both sides of the dielectric material layer 410 and the sidewall 407. A second ion implantation is performed with the dielectric material layer 410 and the sidewall 407 as masks, so as to form a well 411 of the first conductivity type on the surface layer of the epitaxial layer 403 at both sides of the dielectric material layer 410 and the sidewall 407. The second conductivity type ions may be boron ions, boron fluoride ions, or the like, and the implantation direction may be perpendicular to the surface of the epitaxial layer 403.
Next, step S370 is performed, as shown in fig. 4I and 4J, an isolation layer 412 is formed on the sidewall of the first sidewall 407, and a third ion implantation is performed to form a second conductivity type source region 413 in the first conductivity type well region 411.
In one example, forming the isolation layer 412 on the sidewall of the sidewall 407 includes: depositing an isolation layer material on the dielectric material layer 410, on the sidewalls of the sidewalls 407 and on the gate dielectric layer 404; the spacer material on the dielectric material layer 410 and on the gate dielectric layer 404 is removed, and the spacer material on the sidewalls of the sidewall spacers 407 is retained to form the spacers 412 on the sidewalls of the sidewall spacers 407.
Any prior art techniques known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, etc., may be used to deposit an isolation layer material over dielectric material layer 410, the sidewalls of sidewall spacers 407, and gate dielectric layer 404, which covers the entire device surface. The isolation layer material is, for example, polysilicon, silicon nitride, silicon oxide, silicon oxynitride, or the like. Here, polysilicon is preferably deposited by isotropic CVD.
In the process of removing the isolation layer material, the surface of the dielectric material layer 410 is exposed, i.e., the isolation layer material on the surface of the dielectric material layer 410 is completely etched. Those skilled in the art will appreciate that when the spacer material on the surface of the dielectric material layer 410 is completely etched, the spacer material on the surface of the gate dielectric layer 404 can just as well be completely etched, and only the spacer 412 remains on the sidewall of the sidewall 407.
It should be noted that, when the spacer material is deposited on the dielectric material layer 410, the sidewall of the sidewall 407, and the gate dielectric layer 404, the spacer material is inevitably deposited on the upper surface of the sidewall 407, where the thickness of the spacer material is consistent with the thickness of the spacer material on the dielectric material layer 410. When removing the spacer material on the surface of the dielectric material layer 410, the spacer material on the upper surface of the sidewall 407 may be removed together.
Then, as shown in fig. 4J, a third ion implantation may be performed to form a second conductive-type source region 413 at the surface layer of the first conductive-type well region 411. The third conductivity type ions may be phosphorus ions, arsenic ions, or the like, and the implantation direction may be perpendicular to the surface of the epitaxial layer 403.
In some embodiments of the present application, the second conductivity type is n-type for an n-type trench semiconductor device, the first conductivity type is p-type, and the second conductivity type is p-type for a p-type trench semiconductor device, the first conductivity type is n-type. Among them, p-type impurities or ions are boron, boron fluoride, and the like, and n-type impurities or ions are phosphorus, and the like.
It should be noted that the order of the steps is merely an example, and the order of the steps may be exchanged or alternatively performed without conflict.
In summary, in the method for manufacturing a semiconductor device of the present application, the first ion implantation for forming the JFET region, the second ion implantation for forming the first conductivity type well region, and the third ion implantation for forming the second conductivity type source region are connected in series by the self-alignment process, so that compared with the method of selectively implanting by using a photomask as a blocking layer, the method of the present application can effectively reduce the overlay accuracy deviation caused by the secondary lithography, and further ensure the stability of parameters; compared with a Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the resistance of the JFET region can be reduced.
Example III
The present invention also provides a semiconductor device which can be obtained by the method of the first embodiment.
In the following, the semiconductor device of the present invention will be described and illustrated in detail with reference to fig. 2L, and it should be noted that, in order to avoid repetition, only the same components and structures as those in the first embodiment are briefly described, and the detailed explanation and description thereof will be given with reference to the description in the first embodiment.
Specifically, as shown in fig. 2L, the semiconductor device of the present invention includes a substrate 201, wherein the substrate 201 includes a front surface and a back surface opposite to the front surface.
Further, an epitaxial layer 203 is formed on the substrate 201, and a gate dielectric layer 204 is formed on the epitaxial layer 203.
Further, the surface layer of the epitaxial layer 203 is formed with JFET regions 215 disposed at intervals, the surface layers of the epitaxial layer 203 on both sides of the JFET regions 215 are formed with first conductivity type well regions 207, and the surface layers of the first conductivity type well regions 207 are formed with second conductivity type source regions 210.
Further, a dielectric material layer 212 is formed on the gate dielectric layer 204 corresponding to the second conductivity type source region 210, a sidewall 209 is formed on the gate dielectric layer 204 corresponding to the first conductivity type well region 207, and an isolation layer 214 is formed on a sidewall of the sidewall 209.
In one example, a buffer layer 202 is further formed between the substrate 201 and the epitaxial layer 203, and the buffer layer 202 can enable better concentration matching between the epitaxial layer 203 and the substrate 201, so that the doping concentration of the epitaxial layer 203 can be accurately controlled in the growth process.
According to the semiconductor device, the semiconductor device is prepared by adopting the method of the embodiment, and the first ion implantation for forming the first conductive type well region, the second ion implantation for forming the second conductive type source region and the third ion implantation for forming the JFET region are connected in series through a self-alignment process, so that compared with the mode of adopting a photomask as a blocking layer for selective implantation, the semiconductor device can effectively reduce overlay precision deviation caused by secondary photoetching, and further ensure the stability of parameters; compared with the Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the electricity of the JFET region can be reduced.
Example IV
The present invention also provides a semiconductor device which can be obtained by the method in the second embodiment.
In the following, the semiconductor device of the present invention will be described and illustrated in detail with reference to fig. 4J, and it should be noted that, in order to avoid repetition, only the same components and structures as those in the first embodiment are described briefly, and the detailed explanation and description thereof will be given with reference to the description in the first embodiment.
Specifically, as shown in fig. 4J, the semiconductor device of the present invention includes a substrate 401, wherein the substrate 401 includes a front surface and a back surface opposite to the front surface.
Further, an epitaxial layer 403 is formed on the substrate 401, and a gate dielectric layer 404 is formed on the epitaxial layer 403.
Further, the surface layer of the epitaxial layer 403 is formed with JFET regions 408 disposed at intervals, the surface layers of the epitaxial layer 403 on both sides of the JFET region 408 are formed with first conductivity type well regions 411, and the surface layers of the first conductivity type well regions 411 are formed with second conductivity type source regions 413.
Further, a dielectric material layer 410 is formed on the gate dielectric layer 404 corresponding to the region of the JFET region 408, a sidewall 407 is formed on the gate dielectric layer 404 corresponding to the region between the JFET region 408 and the first conductivity type well region 411, and an isolation layer 412 is formed on the sidewall of the sidewall 407.
In one example, a buffer layer 402 is further formed between the substrate 401 and the epitaxial layer 403, where the buffer layer 402 can enable better concentration matching between the epitaxial layer 403 and the substrate 401, which is beneficial for accurately controlling the doping concentration of the epitaxial layer 403 during the growth process.
In one example, the semiconductor device is a junction field effect transistor device.
According to the semiconductor device, the semiconductor device is prepared by adopting the method of the embodiment, and the first ion implantation for forming the JFET region, the second ion implantation for forming the first conductive type well region and the third ion implantation for forming the second conductive type source region are connected in series through a self-alignment process, so that compared with the mode of adopting a photomask as a blocking layer for selective implantation, the semiconductor device can effectively reduce overlay precision deviation caused by secondary photoetching, and further ensure the stability of parameters; compared with a Blank ion implantation mode, the low-energy implantation mode can be selected, meanwhile, the channel cannot be influenced, and therefore the resistance of the JFET region can be reduced.
The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (9)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming an epitaxial layer on the substrate;
forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
performing first ion implantation to form a first conductive type well region in the epitaxial layer;
forming a side wall on the side wall of the pseudo gate structure, and performing second ion implantation to form a second conductivity type source region in the first conductivity type well region;
forming a dielectric material layer covering the gate dielectric layer;
removing the pseudo gate structure;
and forming an isolation layer on the side wall of the side wall, and performing third ion implantation to form a JFET region in the epitaxial layer.
2. The method of manufacturing of claim 1, wherein the gate dielectric layer comprises an oxide layer, the dummy gate structure comprises a bottom-up dummy gate material layer comprising a nitride layer and a gate hard mask layer comprising an oxide layer.
3. The method of claim 1, wherein forming a sidewall of the dummy gate structure comprises:
Depositing a sidewall material on the gate dielectric layer and the dummy gate structure;
and etching back the side wall material, wherein the side wall material remained on the side wall of the pseudo grid electrode structure is the side wall.
4. The method of manufacturing of claim 2, wherein forming a layer of dielectric material overlying the gate dielectric layer, removing the dummy gate structure, comprises:
depositing a dielectric material on the gate dielectric layer, the side wall and the dummy gate structure;
carrying out chemical mechanical polishing on the dielectric material until the pseudo gate material layer is exposed, wherein the dielectric material left on the gate dielectric layer is the dielectric material layer;
and removing the pseudo gate material layer.
5. The method of claim 2 or 4, wherein the dummy gate material layer is removed by wet etching with a high selectivity.
6. The method of claim 1, wherein forming an isolation layer on the sidewall of the sidewall comprises:
depositing isolation layer materials on the dielectric material layer, the side wall of the side wall and the grid dielectric layer;
and removing the isolation layer materials on the dielectric material layer and the gate dielectric layer, and reserving the isolation layer materials on the side wall of the side wall so as to form the isolation layer on the side wall of the side wall.
7. A method of manufacturing a semiconductor device, comprising:
providing a substrate, and forming an epitaxial layer on the substrate;
forming a gate dielectric layer on the epitaxial layer, and forming dummy gate structures arranged at intervals on the gate dielectric layer;
forming a side wall on the side wall of the pseudo gate structure, and performing first ion implantation to form a JFET region in the epitaxial layer;
forming a dielectric material layer covering the gate dielectric layer;
removing the pseudo gate structure;
performing a second ion implantation to form a first conductivity type well region in the epitaxial layer;
and forming an isolation layer on the side wall of the first side wall, and performing third ion implantation to form a second conduction type source region in the first conduction type well region.
8. A semiconductor device characterized by being produced by the production method of the semiconductor device according to any one of claims 1 to 7.
9. The semiconductor device of claim 8, wherein the semiconductor device comprises a junction field effect transistor device.
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