CN116611375A - Software and hardware collaborative simulation platform and software and hardware testing method - Google Patents
Software and hardware collaborative simulation platform and software and hardware testing method Download PDFInfo
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Abstract
The invention provides a software and hardware collaborative simulation platform and a software and hardware testing method, wherein the software and hardware collaborative simulation platform comprises: the system comprises a virtual machine and at least one simulation platform, wherein the virtual machine is connected with the simulation platform through a bus and is used for virtualizing the simulation platform into a standard graphic processor or a general-purpose computing device. The virtual machine in the invention can virtualize the simulation platform as standard graphic processor equipment, so that the simulation platform can be directly connected with a software driver and a test environment, and software can simulate to test on real hardware. In addition, the method and the device do not need to generate and store the vector file vector with the corresponding format according to different test environments, so that decoupling with the vector file vector is realized, the data dump procedure of the vector file vector is reduced, and the problem in the data dump procedure is avoided, so that the positioning precision of a system in case of running errors is disturbed.
Description
Technical Field
The invention relates to the technical field of software testing, in particular to a software and hardware collaborative simulation platform and a software and hardware testing method.
Background
A System On Chip (SOC) includes not only a large number of hardware modules, but also a large number of software, such as an operating System, drivers, communication protocols, and various applications, and the like, and its design complexity is much higher than that of a conventional integrated circuit Chip. Therefore, when simulating the SOC, not only the system hardware part but also the software part, that is, the software-hardware co-simulation, needs to be performed.
At present, most software stores commands (command), register sequences (MMIO sequences), data files, instruction files and the like issued to hardware in the running process according to a given format to obtain vector files (hereinafter referred to as vector files), then runs the vector files by using a C simulator (Cmodel) written in c++, and analyzes according to the given format to simulate the running of a software and hardware system. However, many problems are likely to occur during storage of the vector file, which increases the difficulty of error localization when the system is in error.
Disclosure of Invention
The invention provides a software and hardware collaborative simulation platform and a software and hardware testing method, which are used for solving the defect of high positioning difficulty when a simulation software and hardware system runs in error in the prior art.
The invention provides a software and hardware collaborative simulation platform, which comprises:
the system comprises a virtual machine and at least one simulation platform, wherein the virtual machine is connected with the simulation platform through a bus and is used for virtualizing the simulation platform as a standard graphic processor or a general-purpose computing device.
According to the software and hardware collaborative simulation platform provided by the invention, the virtual machine is installed on the computer, and the computer is used for starting simulation software corresponding to the virtual machine and loading an operating system image file and full stack software.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform comprises a protocol forwarding module;
the protocol forwarding module is used for simulating the data packet flow of the hardware equipment based on the network protocol of the hardware equipment and forwarding the data packet flow.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform further comprises a software module, and the software module is connected with the protocol forwarding module;
the software module is used for simulating a peripheral interface of hardware and forwarding the data packet stream.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform further comprises an evaluation module, a communication module and an analysis module, wherein the evaluation module, the communication module and the analysis module are all connected with the software module;
the evaluation module is used for evaluating the software and hardware collaborative work system, the communication module is used for simulating communication among a plurality of users, and the analysis module is used for carrying out data analysis on the software and hardware collaborative work system.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform further comprises a logic module, wherein the logic module is connected with the protocol forwarding module and is used for distributing tasks corresponding to all data in the data packet stream based on load balancing data.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform further comprises a first module and a second module, wherein the first module and the second module are respectively connected with the logic module;
the first module is used for simulating mapping of hardware equipment, and the second module is used for sending the load balancing data to the logic module.
According to the software and hardware collaborative simulation platform provided by the invention, the virtual machine comprises open source virtualization software Qemu.
According to the software and hardware collaborative simulation platform provided by the invention, the simulation platform comprises a system-on-chip simulation platform.
The invention also provides a software and hardware testing method, which comprises the following steps:
determining a test script;
and running the test script on the software and hardware co-simulation platform to obtain running data, and determining a test result based on the running data.
The invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the software and hardware testing method according to any one of the above when executing the program.
The present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a software and hardware testing method as described in any of the above.
The invention also provides a computer program product comprising a computer program which when executed by a processor implements a software and hardware testing method as described in any one of the above.
According to the software and hardware co-simulation platform and the software and hardware testing method, the virtual machine can virtualize the simulation platform into standard graphic processor equipment, so that the simulation platform can be directly connected with a software driving and testing environment, and software can simulate to test on real hardware. In addition, the invention does not need to generate and store the vector file with the corresponding format according to different test environments, thereby not only realizing decoupling with the vector file, but also reducing the data dump procedure of the vector, and avoiding problems in the data dump procedure so as to interfere with the positioning precision when the system is in error operation.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a software and hardware collaborative simulation platform provided by the invention;
FIG. 2 is a schematic diagram of a software and hardware co-simulation platform according to the present invention;
FIG. 3 is a schematic flow chart of a software and hardware testing method provided by the invention;
fig. 4 is a schematic structural diagram of an electronic device provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A complete SOC design has software and tool chains in addition to the chip code that it mates with. The role of software in SOC systems is also increasingly important with the increase in system complexity. The traditional integrated circuit design method is that after the function segmentation of the software and the hardware is completed, the software and the hardware team head to develop the respective components. Although the development steps of the software and the hardware are synchronously performed, the real combined test of the software and the hardware cannot be performed until the chip sample is returned, and if the chip has a bug, the hardware modification cost is high, the time is more consuming, and the performance of the chip is affected by the software modification. Therefore, in early stage of hardware development, software and hardware collaborative simulation test needs to be performed in advance.
At present, most of software stores commands (command), register sequences (MMIO sequences), data files, instruction files and the like issued to hardware in the running process according to a given format to obtain vector files, then uses Cmodel to run the vector files, and analyzes the vector files according to the given format to simulate the running of a software and hardware system. However, many problems are likely to occur during storage of the vector file, which increases the difficulty of error localization when the system is in error. In addition, the method is only applicable to simulating SPC (Stream Processor Cluster) services, but not other services (such as CP, DMA, etc.).
In this regard, the invention provides a software and hardware collaborative simulation platform. FIG. 1 is a schematic structural diagram of a software and hardware co-simulation platform provided by the present invention, as shown in FIG. 1, the software and hardware co-simulation platform includes:
the system comprises a virtual machine 110 and at least one simulation platform 120, wherein the virtual machine 110 is connected with the simulation platform 120 through a bus, and the virtual machine 110 is used for virtualizing the simulation platform 120 as a standard graphic processor or a general-purpose computing device.
Here, the virtual machine 110 is a technology of emulating a software or hardware environment of another computer system on a computer, and it can create a plurality of virtual logical machines (guests) on a physical machine (host). Virtual machine 110 may include, among other things, open source virtualization software (Qemu). The simulation platform 120 refers to a platform for simulating a hardware device system, and can be obtained through Cmodel construction.
The virtual machine 110 is used to virtualize the emulation platform 120 as a standard graphics processor or general purpose computing device, so that the emulation platform 120 can directly interface with software drivers and test environments, and software can emulate tests on real hardware. Alternatively, the standard image processor may be a PCIe GPU (PCI Express Graphics Processing Unit) and the general purpose computing device may be a general purpose computing chip GP-GPU (general-purpose-Graphics Processing Unit) for use in the field of artificial intelligence.
In addition, if the virtual machine 110 is connected to the multiple simulation platforms 120 through the bus, the multiple simulation platforms 120 may be used to simulate hardware equipment systems under multiple different service scenarios, that is, the embodiment of the present invention may implement software and hardware testing by simulating multiple different service scenarios (such as SPC service, CP service, DMA service, SOC service, etc.), so as to overcome the defect that in the prior art, only the SPC service scenario can be simulated for software and hardware testing. The bus may be a high-speed serial bus (PCI Express, PCIe) to provide higher data transfer speeds and greater bandwidth, among other things.
In addition, in the embodiment of the invention, the vector file with the corresponding format is not required to be generated and stored according to different test environments, so that decoupling with the vector file is realized, the data dump process of the vector file is reduced, and the problem in the dump process is avoided, thereby interfering with the positioning precision when the system is in error operation. In addition, the simulation platform 120 is used for simulating a hardware device system, so that the simulation platform 120 and the corresponding hardware device system can be replaced with each other, and debugging is convenient.
The software and hardware collaborative simulation platform provided by the embodiment of the invention can perform software and hardware testing in advance in the early stage of hardware development so as to release the system risk in advance, and avoid the problems that the software modification influences the chip performance due to higher hardware modification cost and more time consumption caused by the bug found in the process of performing the software and hardware joint test after the chip sample is reworked.
Based on the above embodiment, as shown in fig. 2, the virtual machine 110 is installed on the computer 130, and the computer 130 is used to start the emulation software corresponding to the virtual machine, and load the operating system image file and the full stack software.
Specifically, the virtual machine 110 may be Qemu, which is a hosted virtual machine that emulates a CPU through dynamic binary translation, and provides a set of device models that enable the device model to run a variety of unmodified clients OS (Operating System), and may be used with KVM (Kernel-based Virtual Machine) to run the virtual machine at near-local speeds (i.e., speeds where its running speed is understood to be near that of a real computer).
The virtual machine 110 is installed on a computer 130 (such as host), and the computer 130 is used to start emulation software corresponding to the virtual machine, and load an operating system image file and full stack software. Then, CModel can be registered in Qemu in the form of PCIE equipment, the virtual operating system can identify hardware PCIE equipment, and in this case, software cannot perceive whether the bottom layer is hardware or CModel, so that software and hardware system simulation test can be performed in a relatively real development environment based on the software and hardware collaborative simulation platform provided by the embodiment of the invention.
Based on any of the above embodiments, the emulation platform 120 includes a protocol forwarding module 121;
the protocol forwarding module 121 is configured to emulate a packet flow of a hardware device and forward the packet flow based on a network protocol of the hardware device. The protocol forwarding module 121 may be configured based on HA (Hardware Abstraction), and in the software-hardware co-simulation platform, it can provide a hardware abstraction layer to decouple a specific hardware platform from software.
Based on any of the above embodiments, the emulation platform 120 further includes a software module 122, where the software module 122 is connected to the protocol forwarding module 121, so that the software module 122 can receive the packet flow forwarded by the protocol forwarding module 121.
In addition, the software module 122 is used to emulate a hardware peripheral interface and forward the packet stream. The software module 122 may be configured based on HBF (High Bandwidth Fabric), and the HBF is a hardware forwarding technology implemented by using a dedicated chip, and may directly forward the data packet using hardware, without requiring software processing. Compared with a software forwarding mode, the HBF can achieve faster forwarding speed and higher stability. The HBF is a software module running on a host computer that when interacting with the host computer is capable of emulating an interface of a hardware peripheral device, sending instructions and receiving data, and transferring data to the emulated hardware. The HBF may act as an intermediate layer providing a communication interface between software and hardware so that various parts of the system may be emulated and communication with the software may be performed on behalf of external devices.
Based on any of the above embodiments, the simulation platform 120 further includes an evaluation module 122a, a communication module 122b, and an analysis module 122c, where the evaluation module 122a, the communication module 122b, and the analysis module 122c are all connected to the software module 122;
the evaluation module 122a is used for evaluating the software and hardware collaborative system, the communication module 122b is used for simulating communication among a plurality of users, and the analysis module 122c is used for carrying out data analysis on the software and hardware collaborative system.
The evaluation module 122a may be configured based on CP (Command Processor), where CP is a hardware-level system, and is used for monitoring, managing, and controlling scheduling of tasks in a chip. In the software and hardware collaborative simulation platform, the CP can evaluate the performance indexes such as the multipath interference resistance and the time delay of the system.
The communication module 122b may be constructed based on SDMA (Software-Defined Memory Access), which is a Software-defined memory access technology that may enable efficient, scalable and secure packet processing. SDMA divides an internal memory in network equipment into a plurality of logic areas by using a memory mapping technology, and then realizes dynamic allocation and scheduling of the memory by control software to optimize linear memory access, thereby improving the processing speed and efficiency of data packets. In the software and hardware collaborative simulation platform, SDMA can be used for simulating communication among a plurality of users, so that the system is more stable and efficient, and performance indexes such as throughput, time delay, fault tolerance and the like of the system can be evaluated.
The analysis module 122c may be constructed based on SPC (Stream Processor Cluster). In the software and hardware collaborative simulation platform, the production process of the system can be simulated and evaluated, statistical analysis is carried out according to real-time data, problems are found, and relevant control measures are formulated. The production benefits of each solution can be analyzed by simulating different production flows, thereby finding the optimal flow and solution. Different fault conditions can be simulated, the cause of the problem of the system is analyzed, and measures are taken in time to eliminate the problem. The production data can be counted, analyzed and visually displayed, so that management staff can better know the production condition, and a more scientific and reasonable production plan and decision can be made.
Based on any of the above embodiments, the simulation platform 120 further includes a logic module 123, where the logic module 123 is connected to the protocol forwarding module 121, and the logic module 123 is configured to allocate tasks corresponding to each data in the data packet stream based on the load balancing data.
The logic module 123 may be configured based on LBF (Low Bandwidth Fabric), and the LBF may communicate with the host computer through the HA. In the software and hardware co-simulation platform, the LBF receives control information from the HBF and returns the result to the HBF. LBF can be used to simulate a load balancing scenario in software and hardware co-simulation. In co-simulation, software and hardware can simulate various load scenarios, and the LBF can realize proper allocation and processing of tasks according to the load scenarios.
In addition, through the cooperation of the HBF and the LBF, the software and hardware collaborative simulation platform can simulate the whole system, ensure that functions are correct in an actual system, avoid unnecessary actual tests, reduce the research and development period of products and finally improve the quality and reliability of the products.
Based on any of the above embodiments, the simulation platform 120 further includes a first module 123a and a second module 123b, where the first module 123a and the second module 123b are connected to the logic module 123, respectively;
the first module 123a is used to simulate the mapping of hardware devices and the second module 123b is used to send load balancing data to the logic module 123.
The first module 123a may be constructed based on MMIO (Memory Mapped Input/Output). In the software and hardware co-simulation platform, MMIO can be used for simulating mapping of hardware equipment in a virtualized environment, so that access of a virtual machine to entity hardware is realized. With MMIO, software may simulate sending I/O requests, and hardware may simulate reading and responding to I/O requests.
The second module 123b may be configured based on dorbell, where in the software and hardware collaborative simulation platform, dorbell may simulate sending and responding of an I/O request, software may send a request to hardware through dorbell, and hardware may notify the processing result of the software request through dorbell.
Based on any of the embodiments described above, virtual machine 110 includes open source virtualization software Qemu.
Specifically, qemu is an open-source virtual machine system, which can support various hardware platforms and operating systems. Qemu can run on multiple hosts and can provide a number of advanced features, including dynamic binary translation to speed up the performance of virtual machines, and the ability to integrate with existing systems. Qemu supports a variety of client operating systems, including Linux, android, windows, iOS and like operating systems.
In addition, qemu can also be used with KVM to provide hardware accelerated virtualization and improve performance. The KVM is an open-source Linux kernel module, which can support virtualized hardware and provide efficient virtualized functions.
Based on any of the embodiments described above, the simulation platform 120 comprises a system-on-chip simulation platform.
Specifically, the system-on-chip simulation platform refers to a simulation platform for simulating an SOC, which is a processor system integrating various hardware resources, computer instructions, data memories, and the like onto a single chip, including a processor core, a memory, an input/output interface, a bus system on chip, various circuit components, and the like. The design process of the SOC includes two aspects, software design and hardware design. The hardware design mainly comprises a logic circuit design, an on-chip bus design, a power management design, packaging, testing and the like of a chip, and the software design comprises an operating system design, a driver design, application programming and the like.
Based on any one of the above embodiments, the present invention further provides a software and hardware testing method, as shown in fig. 3, where the method includes:
step 310, determining a test script;
step 320, running a test script on the software and hardware co-simulation platform according to any of the above embodiments to obtain operation data, and determining a test result based on the operation data.
Software and hardware testing refers to testing software and hardware components in a computer system to ensure that they are functioning properly and meet expected performance requirements. The software test mainly comprises the test of software components such as application programs, operating systems, drivers and the like, and the verification of whether the functions of the software components are normal, whether the performances of the software components reach the standards, whether the safety loopholes exist or not and the like. The hardware test mainly comprises the test of hardware components such as a processor, a memory, a display card, a main board and the like, and is used for verifying whether the hardware components can normally operate, have good stability, have defects and the like. Software and hardware testing generally needs to be tested for different test cases, namely, corresponding test scripts need to be determined according to the different test cases.
Here, a test script is an instruction or code for automatically running a test procedure, verifying the function and performance of a software and hardware system. The test script may be obtained based on the following method:
(1) and the coverage rate and the test quality of the test cases can be combined, and a test script can be written to realize automatic test. (2) The test scripts may be obtained from a third party test Framework, which may include Jenkins, robot frames, and the like. (3) And obtaining the test script with higher reliability from the open source community.
After the test script is acquired, the test script is run on the software and hardware collaborative simulation platform according to any embodiment of the present invention, so as to obtain running data, and a test result is determined based on the running data. Wherein the operational data includes test output data, error log data, statistical report data, and the like. The test result is used for representing whether the software and hardware test is successful or not, if yes, the software and hardware are not required to be modified, and if not, the software and hardware are modified based on the test result.
Fig. 4 is a schematic structural diagram of an electronic device according to the present invention, as shown in fig. 4, the electronic device may include: processor 410, memory 420, communication interface (Communications Interface) 430, and communication bus 440, wherein processor 410, memory 420, and communication interface 430 communicate with each other via communication bus 440. The processor 410 may invoke logic instructions in the memory 420 to perform a software and hardware testing method comprising: determining a test script; and running the test script on the software and hardware co-simulation platform to obtain running data, and determining a test result based on the running data.
Further, the logic instructions in the memory 420 described above may be implemented in the form of software functional units and may be stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, enable the computer to perform the method of testing hardware and software provided by the above methods, the method comprising: determining a test script; and running the test script on the software and hardware co-simulation platform to obtain running data, and determining a test result based on the running data.
In yet another aspect, the present invention further provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform the software and hardware testing methods provided above, the method comprising: determining a test script; and running the test script on the software and hardware co-simulation platform to obtain running data, and determining a test result based on the running data.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. The software and hardware collaborative simulation platform is characterized by comprising:
the system comprises a virtual machine and at least one simulation platform, wherein the virtual machine is connected with the simulation platform through a bus and is used for virtualizing the simulation platform as a standard graphic processor or a general-purpose computing device.
2. The software and hardware co-simulation platform according to claim 1, wherein the virtual machine is installed on a computer, and the computer is configured to start simulation software corresponding to the virtual machine, and load an operating system image file and full stack software.
3. The software and hardware co-simulation platform according to claim 2, wherein the simulation platform comprises a protocol forwarding module;
the protocol forwarding module is used for simulating the data packet flow of the hardware equipment based on the network protocol of the hardware equipment and forwarding the data packet flow.
4. A software and hardware co-simulation platform according to claim 3, wherein the simulation platform further comprises a software module, the software module being connected to the protocol forwarding module;
the software module is used for simulating a peripheral interface of hardware and forwarding the data packet stream.
5. The software and hardware co-simulation platform according to claim 4, further comprising an evaluation module, a communication module, and an analysis module, wherein the evaluation module, the communication module, and the analysis module are all connected to the software module;
the evaluation module is used for evaluating the software and hardware collaborative work system, the communication module is used for simulating communication among a plurality of users, and the analysis module is used for carrying out data analysis on the software and hardware collaborative work system.
6. The software and hardware co-simulation platform according to claim 3, further comprising a logic module, wherein the logic module is connected to the protocol forwarding module, and the logic module is configured to allocate tasks corresponding to each data in the packet stream based on load balancing data.
7. The software and hardware co-simulation platform according to claim 6, further comprising a first module and a second module, wherein the first module and the second module are respectively connected with the logic module;
the first module is used for simulating mapping of hardware equipment, and the second module is used for sending the load balancing data to the logic module.
8. The software-hardware co-simulation platform of any of claims 1 to 7, wherein the virtual machine comprises open source virtualization software Qemu.
9. The software and hardware co-simulation platform of any of claims 1 to 7, wherein the simulation platform comprises a system-on-chip simulation platform.
10. A software and hardware testing method is characterized by comprising the following steps:
determining a test script;
running the test script on the software and hardware co-simulation platform according to any one of claims 1 to 9 to obtain running data, and determining a test result based on the running data.
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| CN117113908A (en) * | 2023-10-17 | 2023-11-24 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
| CN117113908B (en) * | 2023-10-17 | 2024-02-02 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
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