CN117113908B - Verification method, verification device, electronic equipment and readable storage medium - Google Patents
Verification method, verification device, electronic equipment and readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- G06F30/36—Circuit design at the analogue level
- G06F30/373—Design optimisation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the invention provides a verification method, a verification device, electronic equipment and a readable storage medium, and relates to the technical field of computers, wherein the verification method comprises the following steps: downloading a software design into a processing system of a programmable logic chip, and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip; synchronously operating the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design; under the condition that the first operation data and the second operation data are not matched, carrying out hardware snapshot on the programmable logic chip so as to save state information of the programmable logic chip; and importing the state information into simulation software to simulate so as to debug the hardware design. The embodiment of the invention improves the verification efficiency and ensures the simulation freedom degree and the debugging efficiency.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a verification method, a verification device, an electronic device, and a readable storage medium.
Background
In the related art, for verification of High-Level Synthesis (HLS) design, a software simulation verification manner is generally adopted, and compared with hardware simulation methods such as FPGA prototype verification and FPGA simulation, hardware-based simulation generally runs at a speed of tens or hundreds of megahertz, software simulation is often slower and takes tens or hundreds of kilohertz as a unit, and the simulation speed is further reduced by a debugging option such as waveform dump or debugging information display, so that the overall verification efficiency is lower.
Disclosure of Invention
The embodiment of the invention provides a verification method, a verification device, electronic equipment and a readable storage medium, which can solve the problem of low verification efficiency of hardware design in related technologies.
In order to solve the above problems, an embodiment of the present invention discloses a verification method, which includes:
downloading a software design into a processing system of a programmable logic chip, and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip;
synchronously operating the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design;
Under the condition that the first operation data and the second operation data are not matched, carrying out hardware snapshot on the programmable logic chip so as to save state information of the programmable logic chip;
and importing the state information into simulation software to simulate so as to debug the hardware design.
In another aspect, an embodiment of the present invention discloses a verification apparatus, including:
the preprocessing module is used for downloading a software design into a processing system of the programmable logic chip and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip;
the monitoring module is used for synchronously operating the hardware design and the software design in the programmable logic chip and monitoring first operation data of the hardware design and second operation data of the software design;
the first snapshot module is used for carrying out hardware snapshot on the programmable logic chip under the condition that the first operation data and the second operation data are not matched so as to save the state information of the programmable logic chip;
and the transmission module is used for importing the state information into simulation software to simulate so as to debug the hardware design.
In still another aspect, the embodiment of the invention also discloses an electronic device, which comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions that cause the processor to perform the verification method described above.
The embodiment of the invention also discloses a readable storage medium, which enables the electronic device to execute the verification method when the instructions in the readable storage medium are executed by the processor of the electronic device.
The embodiment of the invention has the following advantages:
the embodiment of the invention provides a verification method, wherein a hardware design is loaded on an FPGA chip to run, and verification efficiency is improved by utilizing FPGA acceleration; and under the condition that the first operation data of the hardware design is not matched with the second operation data of the software design, errors can be quickly and accurately positioned through the hardware snapshot, state information stored by the snapshot is imported into simulation software, the simulation software is utilized to debug the hardware design in a finer granularity, and the degree of freedom and the debugging efficiency of simulation are ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of steps of an embodiment of a verification method of the present invention;
FIG. 2 is a schematic diagram of the architecture of a verification framework of the present invention;
FIG. 3 is a block diagram of a verification device of the present invention;
fig. 4 is a block diagram of an electronic device for authentication according to an example of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.
Method embodiment
The embodiment of the invention provides a verification method, which can combine FPGA acceleration with software simulation, and can improve the verification efficiency while guaranteeing the degree of freedom and the debugging efficiency.
In order to facilitate an understanding of the embodiments provided by the present invention, the following description is made:
1. High-Level Synthesis (HLS): high-level synthesis is a hardware design approach that allows developers to describe hardware functions and behavior in high-level languages (such as C, C ++ or SystemC) and then convert these high-level language descriptions to RTL (Register Transfer Level) descriptions of hardware circuits through high-level synthesis tools. The method eliminates the process of manually writing hardware description languages (such as Verilog and VHDL) in the traditional hardware design, so that the hardware design process is simpler and more efficient, the development speed of the hardware design is accelerated, the hardware design threshold is reduced, and more software developers can concentrate on the functional design. However, HLS also has its limitations, for example, in some complex hardware design scenarios, manually writing RTL code may still be more efficient than automatically synthesized circuits.
Different companies and research institutions have developed a wide variety of HLS tools, some of the currently mainstream HLS tools include:
vitis HLS (Xilinx): the Vitis HLS is an HLS tool developed by Xilinx, which is a component in Xilinx Vivado Design Suite. The main goal of the Vitis HLS is to allow hardware designers to describe hardware functionality using high-level programming languages such as C/c++ and OpenCL, which are then automatically converted into optimized RTL (Register Transfer Level) code for efficient hardware acceleration on Xilinx FPGA and SoC platforms.
Intel HLS Compiler (Intel FPGA): intel HLS Compiler is an HLS tool provided by Intel FPGA (precursor Altera), supports high-level synthesis using the C/C++ language, and is capable of generating optimized RTL code for Intel FPGA devices.
Legup HLS: legUp HLS is a open source HLS tool that supports the conversion of C code into hardware circuitry on an FPGA.
2. IP (IP Core): the IP core is a pre-designed and verified hardware functional unit and can be reused in different hardware systems. It is a reusable hardware module, similar to a code library in software development. On-chip IP may include a variety of different functions, ranging from simple logic gates and registers to complex processors, communication interfaces, graphics processing units, and so forth.
3. RTL Circuit RTL (Register-Transfer Level) circuits are a common Level of hardware description. RTL circuits describe the behavior and structure of digital circuits and use a register transfer level of abstraction. RTL circuit descriptions are typically written using Hardware Description Language (HDL), such as VHDL (VHSIC Hardware Description Language), verilog HDL, systemVerilog HDL. The designer may use the RTL level description to define and implement the desired digital circuit functions and then use the synthesis tool to convert the RTL level description to a physical implementation in the FPGA. In the field of FPGA, chip design and verification, RTL level description is very important for design, verification and debugging. It provides a level of abstraction that enables designers to describe circuit behavior at a higher level of abstraction and to use appropriate tools for simulation, verification and synthesis, ultimately generating bit stream (bitstream) files that can be configured into FPGA chips to implement specific digital circuit functions.
4. And (3) FPGA: FPGA (Field-Programmable Gate Array, field programmable gate array) is a reconfigurable integrated circuit chip with a wide range of applications. Unlike conventional fixed function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured to accommodate different applications and functions according to the needs of the user. An FPGA consists of a large number of programmable logic blocks (logic blocks) and programmable interconnect resources (interconnect resources). Programmable logic blocks are typically composed of Look-Up Tables (LUTs), registers, and other logic elements that can perform various logic functions. The programmable interconnect resources are used to connect the logic blocks to form the desired circuit structure. Using FPGAs, design engineers can describe the required circuit functions using hardware description language and convert them into bit streams (bitstreams) compatible with the FPGA chip by programming tools. The bit stream contains information to program and configure the internal logic and interconnect resources of the FPGA. One of the main advantages of FPGA is its programmability and flexibility. It allows design engineers to implement custom functions and algorithms at the hardware level without the need for traditional custom integrated circuit design and manufacturing processes. This makes FPGAs very useful in prototype development and fast design iterations.
5. Dynamic partial reconfiguration (Dynamic Partial Reconfiguration, DPR) of an FPGA refers to the ability to reconfigure portions of the circuitry while the FPGA is running. In conventional FPGA designs, it is often necessary to reprogram and reload the entire circuit into the FPGA to change its function. Whereas DPR techniques allow for reconfiguration of only part of the circuitry while the FPGA is running, without affecting the other circuitry that is running. The main advantage of dynamic partial reconfiguration is its flexibility and improved resource utilization. By using DPR, multiple functional modules can be implemented in the FPGA, each of which can be reconfigured independently as needed without reloading the entire design. The flexibility enables the FPGA to adapt to various application requirements, reduces reprogramming and reloading time, and accelerates the design iteration speed.
6. FIFO is an abbreviation of "First In, first Out", chinese called "First In First Out", which is a common way of managing a queue data structure. In the FIFO, the element that was first queued will be fetched first and the element that was last queued will be fetched last as if the person who was queued in front of the team were first to leave the team. Such a data structure may be used to simulate various actual scenarios, such as queuing, processing requests, etc. FIFO queues are often used to manage shared resources, processing tasks, cache management, and the like.
Referring to fig. 1, there is shown a flow chart of steps of an embodiment of a verification method of the present invention, which may include the steps of:
step 101, downloading a software design into a processing system of a programmable logic chip, and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip.
Step 102, synchronously operating the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design.
And step 103, under the condition that the first operation data and the second operation data are not matched, performing hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
And 104, importing the state information into simulation software to simulate so as to debug the hardware design.
It should be noted that the programmable logic chip, that is, the FPGA chip (or the FPGA system-on-chip) includes not only the programmable gate array circuit but also one or more on-chip processors. Wherein the programmable gate array circuit is commonly referred to as programmable logic (Programmable Logic, PL); the on-chip processor is typically an ARM processor, known as a processing system (Processing System, PS). In the embodiment of the invention, the hardware design is burnt on the PL end of the FPGA chip, and the software design is operated on the PS end of the FPGA chip. The hardware design in the invention mainly refers to the HLS design, the software design mainly refers to the C/C++ design corresponding to the HLS design, and the software design is used for realizing the same functions as the hardware design.
In the embodiment of the invention, the hardware design to be verified is firstly burnt to the PL end of the FPGA chip, the software design is downloaded to the PS end of the FPGA chip, and the hardware design and the software design are synchronously operated on the FPGA chip. For example, if a specific functional verification is to be performed on the hardware design, the corresponding benchmark test program may be downloaded into an external memory device of the FPGA, such as a double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR). Then, the FPGA chip is operated, and the benchmark test program is synchronously executed by the hardware design and the software design. The benchmark test procedure includes a series of procedures for testing the performance or correctness of the design under test. In the actual verification process, different benchmark test programs can be generated according to different verification requirements.
If the first operational data of the hardware design and the second operational data of the software design do not match, a hardware design error may be determined. In this case, a hardware snapshot may be performed on the entire FPGA chip to save state information of the FPGA chip. And finally, importing the stored state information into simulation software to simulate, thereby debugging the to-be-tested design. The state information of the FPGA may include state information of a fly-drag, an on-chip memory, a DSP, an external device, and the like. The external device in the embodiment of the invention refers to a device which is mounted on an FPGA chip and does not belong to a PL end or a PS end, such as external storage devices of DDR and the like.
Referring to fig. 2, an architecture diagram of a verification framework provided by an embodiment of the present invention is shown. As shown in fig. 2, the verification framework includes an FPGA chip and simulation software, which is loaded in a personal computer (Personal Computer, PC). The PL end of the FPGA chip is provided with a hardware design and verification module, and the verification module is used for collecting operation data of the hardware design and the software design and comparing the two groups of data so as to judge whether the hardware design is in error or not. The software design is run at the PS end of the FPGA chip. The external device in fig. 2 refers to a device that is mounted on an FPGA chip and that is neither a PL nor PS terminal, such as an external memory device like a DDR.
Traditionally, FPGA prototyping methods only check if the module output matches the expected result. However, if any errors are found, the visibility of the internal signals and intermediate results is critical to debugging. Modification of the analyzed signals using FPGA vendor's debug tools (e.g., signalTap and ILA) requires recompilation, while storing more data introduces more overhead. In the embodiment of the invention, extra codes can be added in the C/C++ model of the original HLS matrix multiplication to sample internal signals of hardware design and software design, so that the internal signals can be directly compared later. Specifically, the embodiment of the invention respectively configures a buffer area for the hardware design and the software design, and in the running process, the hardware design writes running data of the hardware design, including intermediate results and final output results, into the hardware buffer area; the software design writes its operating data into the software buffer.
The verification module can read first operation data of the hardware design from the hardware buffer area, read second operation data of the software design from the software buffer area, compare the read first operation data with the second operation data, determine that the hardware design has errors under the condition that the two groups of data are not matched, interrupt the operation of the hardware design and the software design, carry out hardware snapshot on the FPGA chip, and save the state information of the FPGA chip. The verification module interacts with the PC end, the stored state information is imported into simulation software, and the simulation software is used for debugging and repairing the hardware design.
According to the embodiment of the invention, the hardware design and the software design are mapped to the same FPGA chip to run, and the simulation speed is obviously improved by utilizing the acceleration of FPGA hardware; in addition, the embodiment of the invention can import the state information of the FPGA chip into simulation software for simulation under the condition of hardware design errors, and ensures the degree of freedom and the debugging efficiency of the simulation through software simulation.
Optionally, the programmable logic chip is further equipped with an external device, and the programmable logic area further includes a verification module, where the verification module is used to verify the hardware design; the hardware design interacts with the external device and/or the verification module during operation via an on-chip bus.
In the embodiment of the invention, the system level verification of the hardware design can be realized on the FPGA chip, namely, the hardware design can interact with other modules on the FPGA chip, such as a verification module, external equipment, such as DDR and the like, and generate operation data in the operation process, and whether the hardware design has errors or not is determined by comparing the operation data of the hardware design and the software design.
Optionally, the programmable logic chip further includes a data memory, where the data memory is configured to store input data corresponding to the hardware design, and the hardware design reads the input data from the data memory in the operation process and processes the operation data.
The embodiment of the invention can realize unit level verification of the hardware design on the FPGA chip, namely, only the correctness of the hardware design is verified, and the interaction process of the hardware design and other modules, such as a verification module, external equipment and the like, is not concerned.
Optionally, before performing a hardware snapshot on the programmable logic chip to save state information of the programmable logic chip in a case that the first operation data and the second operation data do not match, the method further includes:
Writing first operation data of the hardware design into a hardware buffer area under the condition that result signals of the hardware design in the same iterative operation are all generated; the first operational data includes all of the resulting signals in the iterative operation.
At the PL end, the intermediate result of each iterative operation of the hardware design may be sampled. Because the internal result signals may not be generated in the same clock cycle in the hardware generated by HLS, the result signals in the same iteration operation in the hardware design may be written into the hardware buffer after being synchronized, that is, all the result signals in the iteration operation are written into the hardware buffer synchronously when the result signals in the same iteration operation in the hardware design are all generated.
By way of example, the HLS hardware design for implementing merge ordering, the signals it outputs may include address signals and data signals. The output time of the address signal and the data signal are different, so that the address signal and the data signal can be synchronized and written into the hardware buffer in the form of 'address + data'.
At the PS end, no additional synchronization is needed, as intermediate calculation results of the software design have been identified and executed sequentially within the same iteration.
In an alternative embodiment of the invention, the method further comprises:
step S11, determining sampling conditions of a first signal in the hardware design; the first signal is any signal in the hardware design;
and step S12, under the condition that the first signal meets the sampling condition, interrupting the operation of the hardware design, and performing hardware snapshot on the hardware design to save the state information of the hardware design.
In the embodiment of the invention, the first signal of interest in the hardware design can be sampled, and the correctness of the HLS design is verified. The first signal may be any signal generated during the operation of the hardware design. In the verification process, sampling conditions of the first signal can be preset, and under the condition that the sampling conditions are met, the operation of the hardware design is interrupted, and the hardware design is subjected to hardware snapshot.
The PL end of the FPGA chip further includes an interrupt module, and in the verification process, a sampling condition of the first signal may be set in the interrupt module, where the interrupt module sends an interrupt signal to the hardware design when it is determined that the sampling condition is met, and the hardware design pauses operation after receiving the interrupt signal. After the hardware design is safely paused, the interrupt module only performs hardware snapshot on the design module (comprising the hardware design and the functional units corresponding to the hardware design), and the state information of the design module is saved. For example, a sampling condition "signal a= = x = x||signal C > x" may be set for signals signal a, signal B, and signal C, and hardware design may be interrupted and state information of a design block may be snapshot-saved when the sampling condition is satisfied.
Furthermore, the state information of the hardware design can be imported into simulation software for simulation, so that unit-level verification of the hardware design is realized, namely, the correctness of the hardware design is verified, and the interaction process of the hardware design and other modules, such as a verification module, external equipment and the like, is not concerned.
In an alternative embodiment of the invention, the method further comprises:
step S21, determining breakpoint logic of a second signal in the hardware design; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used for indicating the target interval corresponding to the second signal;
and S22, under the condition that the current value of the second signal does not accord with the breakpoint logic, interrupting the operation of the hardware design and the software design, and carrying out hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
It will be appreciated that the values of some intermediate signals are correct within a certain range, which cannot be directly compared with the signal values in the PS-side software design. In embodiments of the present invention, breakpoint logic decisions may be added to these signals. Specifically, if the current value of the second signal is an arbitrary value within the target interval, no processing is performed, and the hardware design is operated. If the current value of the second signal does not belong to any value in the target interval, that is, the current value of the signal does not conform to the breakpoint logic, in this case, the operation of the hardware design can be interrupted, and the state information of the FPGA chip can be saved through the hardware snapshot.
Furthermore, the stored state information can be imported into simulation software for simulation, so that analysis and debugging with finer granularity can be performed on the second signal.
In an optional embodiment of the present invention, the programmable logic area of the programmable logic chip further includes a verification module, where the verification module is configured to compare the first operation data with the second operation data; and under the condition that the first operation data and the second operation data are not matched, performing hardware snapshot on the programmable logic chip to save state information of the programmable logic chip, wherein the method comprises the following steps:
step S31, respectively performing compression processing on the first operation data and the second operation data to obtain first compression data and second compression data when the data amount of the first operation data and/or the second operation data is greater than or equal to a preset threshold value;
step S32, the first compressed data and the second compressed data are sent to the verification module, and the first compressed data and the second compressed data are compared through the verification module;
and step S33, performing hardware snapshot on the programmable logic chip under the condition that the first compressed data and the second compressed data are not matched so as to save the state information of the programmable logic chip.
If the hardware design and the software design generate a large amount of operation data in the operation process, and the communication bandwidth of the on-chip bus is limited, a long time is required for transmitting the data, and verification efficiency is affected. Therefore, in the embodiment of the present invention, if the data size of the first operation data of the hardware design is greater than or equal to the preset threshold value, and/or the data size of the first operation data of the software design is greater than or equal to the preset threshold value, the first operation data of the hardware design and the second operation data of the software design may be compressed by using the compression algorithm, and then the compressed first compressed data and second compressed data are sent to the verification module, so as to reduce delay and resource overhead caused by data transmission.
As an example, corresponding buffers may be allocated in the FPGA chip for hardware and software designs for recording operational data. Typically, both the hardware buffer for recording the operational data of the hardware design and the software buffer for recording the operational data of the software design are provided at the PL, typically in the verification module. The hardware design and the software design can respectively compress the operation data by utilizing a compression algorithm under the condition of larger data volume, and then write the compressed data into the corresponding buffer area. The compression algorithm may include, but is not limited to, XOR-folding, checksum and Cyclic Redundancy Check (CRC) algorithms, among others. Selecting an appropriate compression granularity may balance compression rate and accuracy to quickly detect potential problems. In practical applications, the compression algorithm may be selected based on the granularity of compression as well as the accuracy of compression.
In summary, the embodiment of the invention provides a verification method, wherein the hardware design is loaded on an FPGA chip to run, and the verification efficiency is improved by utilizing the acceleration of the FPGA; and under the condition that the first operation data of the hardware design is not matched with the second operation data of the software design, errors can be quickly and accurately positioned through the hardware snapshot, state information stored by the snapshot is imported into simulation software, the simulation software is utilized to debug the hardware design in a finer granularity, and the degree of freedom and the debugging efficiency of simulation are ensured.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
Device embodiment
Referring to fig. 3, there is shown a block diagram of a verification device of the present invention, which may specifically include:
The preprocessing module 301 is configured to download a software design into a processing system of a programmable logic chip, and burn a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip;
a monitoring module 302, configured to run the hardware design and the software design synchronously in the programmable logic chip, and monitor first running data of the hardware design and second running data of the software design;
a first snapshot module 303, configured to perform a hardware snapshot on the programmable logic chip to save state information of the programmable logic chip when the first operation data and the second operation data are not matched;
and the transmission module 304 is used for importing the state information into simulation software to simulate so as to debug the hardware design.
Optionally, the programmable logic chip is further equipped with an external device, and the programmable logic area further includes a verification module, where the verification module is used to verify the hardware design; the hardware design interacts with the external device and/or the verification module during operation via an on-chip bus.
Optionally, the programmable logic chip further includes a data memory, where the data memory is configured to store input data corresponding to the hardware design, and the hardware design reads the input data from the data memory in the operation process and processes the operation data.
Optionally, the apparatus further comprises:
the data writing module is used for writing the first operation data of the hardware design into a hardware buffer area under the condition that the result signals of the hardware design in the same iterative operation are all generated; the first operational data includes all of the resulting signals in the iterative operation.
Optionally, the apparatus further comprises:
the first determining module is used for determining the sampling condition of the first signal in the hardware design; the first signal is any signal in the hardware design;
and the second snapshot module is used for interrupting the operation of the hardware design and carrying out hardware snapshot on the hardware design under the condition that the first signal meets the sampling condition so as to save the state information of the hardware design.
Optionally, the apparatus further comprises:
a second determining module, configured to determine breakpoint logic of a second signal in the hardware design; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used for indicating the target interval corresponding to the second signal;
And the third snapshot module is used for interrupting the operation of the hardware design and the software design under the condition that the current value of the second signal does not accord with the breakpoint logic, and carrying out hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
Optionally, the programmable logic area of the programmable logic chip further comprises a verification module, and the verification module is used for comparing the first operation data with the second operation data; the first snapshot module includes:
the compression sub-module is used for respectively carrying out compression processing on the first operation data and the second operation data to obtain first compression data and second compression data under the condition that the data volume of the first operation data and/or the second operation data is larger than or equal to a preset threshold value;
the transmitting sub-module is used for transmitting the first compressed data and the second compressed data to the verification module, and comparing the first compressed data with the second compressed data through the verification module;
and the snapshot submodule is used for carrying out hardware snapshot on the programmable logic chip under the condition that the first compressed data and the second compressed data are not matched so as to save the state information of the programmable logic chip.
In summary, the embodiment of the invention provides a verification device, which loads a hardware design to an FPGA chip to run, and improves the verification efficiency by utilizing the FPGA; and under the condition that the first operation data of the hardware design is not matched with the second operation data of the software design, errors can be quickly and accurately positioned through the hardware snapshot, state information stored by the snapshot is imported into simulation software, the simulation software is utilized to debug the hardware design in a finer granularity, and the degree of freedom and the debugging efficiency of simulation are ensured.
For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The specific manner in which the various modules perform the operations in relation to the processor of the above-described embodiments have been described in detail in relation to the embodiments of the method and will not be described in detail herein.
Referring to fig. 4, a block diagram of an electronic device for authentication according to an embodiment of the present invention is provided. As shown in fig. 4, the electronic device includes: the device comprises a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface complete communication with each other through the communication bus; the memory is configured to store executable instructions that cause the processor to perform the authentication method of the foregoing embodiment.
The processor may be a CPU (Central Processing Unit ), general purpose processor, DSP (Digital Signal Processor ), ASIC (Application Specific Integrated Circuit, application specific integrated circuit), FPGA (Field Programmble Gate Array, field programmable gate array) or other editable device, transistor logic device, hardware components, or any combination thereof. The processor may also be a combination that performs the function of a computation, e.g., a combination comprising one or more microprocessors, a combination of a DSP and a microprocessor, etc.
The communication bus may include a path to transfer information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect, peripheral component interconnect standard) bus or an EISA (Extended Industry Standard Architecture ) bus, or the like. The communication bus may be classified into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.
The memory may be a ROM (Read Only memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access memory) or other type of dynamic storage device that can store information and instructions, an EEPROM (Electrically Erasable Programmable Read Only, electrically erasable programmable Read Only memory), a CD-ROM (Compact Disa Read Only, compact disc Read Only), a magnetic tape, a floppy disk, an optical data storage device, and the like.
Embodiments of the present invention also provide a non-transitory computer-readable storage medium that, when executed by a processor of an electronic device (server or terminal), enables the processor to perform the authentication method shown in fig. 1.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The foregoing has described in detail a verification method, apparatus, electronic device and readable storage medium according to the present invention, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (13)
1. A method of authentication, the method comprising:
downloading a software design into a processing system of a programmable logic chip, and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip;
synchronously operating the hardware design and the software design in the programmable logic chip, and monitoring first operation data of the hardware design and second operation data of the software design;
under the condition that the first operation data and the second operation data are not matched, carrying out hardware snapshot on the programmable logic chip so as to save state information of the programmable logic chip;
importing the state information into simulation software for simulation so as to debug the hardware design;
the programmable logic chip is further provided with external equipment, and the programmable logic area further comprises a verification module which is used for verifying the hardware design; the hardware design interacts with the external device and/or the verification module during operation via an on-chip bus.
2. The method of claim 1, wherein the programmable logic chip further comprises a data memory, the data memory is configured to store input data corresponding to the hardware design, and the hardware design reads the input data from the data memory and processes the operation data during operation.
3. The method of claim 1, wherein in the event that the first operational data and the second operational data do not match, prior to performing a hardware snapshot of the programmable logic chip to save state information of the programmable logic chip, the method further comprises:
writing first operation data of the hardware design into a hardware buffer area under the condition that result signals of the hardware design in the same iterative operation are all generated; the first operational data includes all of the resulting signals in the iterative operation.
4. The method according to claim 1, wherein the method further comprises:
determining a sampling condition of a first signal in the hardware design; the first signal is any signal in the hardware design;
and under the condition that the first signal meets the sampling condition, interrupting the operation of the hardware design, and performing hardware snapshot on the hardware design to save the state information of the hardware design.
5. The method according to claim 1, wherein the method further comprises:
determining breakpoint logic of a second signal in the hardware design; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used for indicating the target interval corresponding to the second signal;
And under the condition that the current value of the second signal does not accord with the breakpoint logic, interrupting the operation of the hardware design and the software design, and carrying out hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
6. The method of claim 1, further comprising a verification module in a programmable logic area of the programmable logic chip, the verification module configured to compare the first operational data and the second operational data; and under the condition that the first operation data and the second operation data are not matched, performing hardware snapshot on the programmable logic chip to save state information of the programmable logic chip, wherein the method comprises the following steps:
under the condition that the data volume of the first operation data and/or the second operation data is greater than or equal to a preset threshold value, respectively compressing the first operation data and the second operation data to obtain first compressed data and second compressed data;
the first compressed data and the second compressed data are sent to the verification module, and the first compressed data and the second compressed data are compared through the verification module;
And under the condition that the first compressed data and the second compressed data are not matched, performing hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
7. A verification device, the device comprising:
the preprocessing module is used for downloading a software design into a processing system of the programmable logic chip and burning a hardware design corresponding to the software design into a programmable logic area of the programmable logic chip;
the monitoring module is used for synchronously operating the hardware design and the software design in the programmable logic chip and monitoring first operation data of the hardware design and second operation data of the software design;
the first snapshot module is used for carrying out hardware snapshot on the programmable logic chip under the condition that the first operation data and the second operation data are not matched so as to save the state information of the programmable logic chip;
the transmission module is used for importing the state information into simulation software to simulate so as to debug the hardware design;
the programmable logic chip is further provided with external equipment, and the programmable logic area further comprises a verification module which is used for verifying the hardware design; the hardware design interacts with the external device and/or the verification module during operation via an on-chip bus.
8. The apparatus of claim 7, wherein the programmable logic chip further comprises a data memory, the data memory for storing input data corresponding to the hardware design, the hardware design reading input data from the data memory during operation and processing the operation data.
9. The apparatus of claim 7, wherein the apparatus further comprises:
the data writing module is used for writing the first operation data of the hardware design into a hardware buffer area under the condition that the result signals of the hardware design in the same iterative operation are all generated; the first operational data includes all of the resulting signals in the iterative operation.
10. The apparatus of claim 7, wherein the apparatus further comprises:
the first determining module is used for determining the sampling condition of the first signal in the hardware design; the first signal is any signal in the hardware design;
and the second snapshot module is used for interrupting the operation of the hardware design and carrying out hardware snapshot on the hardware design under the condition that the first signal meets the sampling condition so as to save the state information of the hardware design.
11. The apparatus of claim 7, wherein the apparatus further comprises:
a second determining module, configured to determine breakpoint logic of a second signal in the hardware design; the correct value of the second signal is any value in a target interval, and the breakpoint logic is used for indicating the target interval corresponding to the second signal;
and the third snapshot module is used for interrupting the operation of the hardware design and the software design under the condition that the current value of the second signal does not accord with the breakpoint logic, and carrying out hardware snapshot on the programmable logic chip so as to save the state information of the programmable logic chip.
12. An electronic device, comprising a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is configured to store executable instructions that cause the processor to perform the authentication method of any one of claims 1 to 6.
13. A readable storage medium, characterized in that instructions in the readable storage medium, when executed by a processor of an electronic device, enable the processor to perform the authentication method of any one of claims 1 to 6.
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| CN103914580A (en) * | 2012-12-31 | 2014-07-09 | 复旦大学 | Method for FPGA (field programmable gate array) circuit bit stream simulation |
| CN109543212A (en) * | 2018-10-10 | 2019-03-29 | 深圳市紫光同创电子有限公司 | Function test method, device and the computer storage medium of programmable logic device |
| CN116611375A (en) * | 2023-05-26 | 2023-08-18 | 上海壁仞智能科技有限公司 | Software and hardware collaborative simulation platform and software and hardware testing method |
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| US9513334B2 (en) * | 2013-03-15 | 2016-12-06 | Microsemi SoC Corporation | System on a chip FPGA spatial debugging using single snapshot |
| US9217774B2 (en) * | 2013-11-01 | 2015-12-22 | International Business Machines Corporation | Cycle-accurate replay and debugging of running FPGA systems |
| GB201522216D0 (en) * | 2015-12-16 | 2016-01-27 | Lambda Logic Ltd | System and method for the design of digital hardware |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103914580A (en) * | 2012-12-31 | 2014-07-09 | 复旦大学 | Method for FPGA (field programmable gate array) circuit bit stream simulation |
| CN109543212A (en) * | 2018-10-10 | 2019-03-29 | 深圳市紫光同创电子有限公司 | Function test method, device and the computer storage medium of programmable logic device |
| CN116611375A (en) * | 2023-05-26 | 2023-08-18 | 上海壁仞智能科技有限公司 | Software and hardware collaborative simulation platform and software and hardware testing method |
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