CN116599538A - LDPC decoder and decoding method based on ANMS algorithm - Google Patents
LDPC decoder and decoding method based on ANMS algorithm Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H—ELECTRICITY
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention provides an LDPC decoder and decoding method based on an ANMS algorithm, wherein the decoder comprises: the system comprises a configuration information module 201, a check node updating module 202, a variable node updating module 203, a decoding judgment module 204 and a control module 205, wherein the decoding judgment module 204 adopts different self-adaptive normalization factor calculation formulas aiming at a data path M1 and a data path M2, and the control module 205 controls data to iterate according to two branch circuits. The LDPC decoder which can realize the ANMS algorithm based on two inhibition factor formulas in a set of hardware system is realized, idle resources in the decoder are effectively utilized, and the decoding performance of the decoder is improved.
Description
Technical Field
The invention relates to the technical field of decoding, in particular to an LDPC decoder and a decoding method based on an ANMS algorithm.
Background
Among the numerous channel coding schemes, a Low-Density Parity-Check (LDPC) code is a linear error correction code having a performance approaching shannon's limit, and is widely used in optical fiber communication and various services due to its excellent error correction performance and high data transmission efficiency, and continues to play an important role in 5G communication systems.
At present, an iterative decoding method is mainly adopted for LDPC code decoding. According to the form of the data to be decoded, the decoding algorithm is mainly divided into a hard decision decoding algorithm and a soft decision algorithm. Wherein, the performance of the BP (Belief Propagation) decoding algorithm in the soft decision algorithm is close to the shannon limit. When the BP algorithm is realized by hardware, the hardware efficiency is low due to too high calculation complexity, and the hardware cost is high, so that the check node updating calculation is generally approximated to obtain the Min-Sum algorithm. Although the Min-Sum algorithm reduces the computational complexity, it overestimates the magnitude of the information that the check node passes to the variable nodes relative to the BP algorithm, inevitably reducing decoding performance, and in addition, the Min-Sum check node update formula results in the magnitude of the information outside the check node being generally greater than that in the BP algorithm. The NMS (Normalized Min-Sum) algorithm introduces a normalization factor alpha (0 < alpha < 1) to improve the check node update formula in the Min-Sum algorithm, and reduces the amplitude of information outside the check node in the Min-Sum algorithm so as to improve the algorithm performance. According to the BP decoding algorithm, in the decision step of iterative decoding, for the check constraint of decision failure, the external information of the corresponding check nodes needs to be suppressed, while the NMS algorithm does not suppress the nodes. The ANMS (Adaptive Normalized Min-Sum) algorithm introduces check node suppression factors on the basis of the NMS algorithm to reduce the influence of unreliable check node external information on the subsequent decoding process.
However, there is no better theoretical method for the choice of normalization factor in the ANMS algorithm. Although many documents propose adaptive formulas for different normalization factors, only a single formula calculation is utilized in the respective system.
For this reason, it is necessary to design a decoder with high decoding performance, which can decode with different normalization factors.
Disclosure of Invention
The invention provides an LDPC decoder based on an ANMS algorithm, which aims to design an LDPC decoder capable of realizing the ANMS algorithm based on two inhibition factor formulas in a set of hardware system, effectively utilizes idle resources in the decoder and improves the decoding performance of the decoder.
In a first aspect, the present invention provides an LDPC decoder based on an ANMS algorithm, including: the configuration information module 201 is configured to receive a codeword to be decoded, and transmit the codeword to be decoded to the control module 205 and the variable node update module 203; the code word to be decoded represents configuration information of different code lengths and code rates;
the check node updating module 202 is configured to obtain codeword data output by the configuration information module 201 or the variable node updating module 203 from the control module 205, perform check node updating calculation on the codeword data, thereby obtaining codeword information after check node updating, and input the information after check node updating into the control module 205;
the variable node updating module 203 is configured to obtain codeword data output by the configuration information module 201 or the check node updating module 202 from the control module 205, perform variable node updating calculation on the codeword data, thereby obtaining codeword information updated by the variable node, and input the updated information of the variable node into the control module 205;
the decoding decision module 204 is configured to obtain the codeword information updated by the check node and the codeword information updated by the variable node from the control module 205, determine whether the codeword to be decoded is correct according to the codeword information updated, and send a signal indicating whether the decoding is correct to the control module;
the control module 205 is configured to receive and determine whether the decoding sent by the decoding decision module 204 is correct, and if the signal indicates that the decoding is incorrect, perform iterative control: continuing to receive the codeword information updated by the check node and/or the codeword information updated by the variable node, and sending the codeword information updated by the variable node and/or the codeword information updated by the check node to the check node updating module 202 and/or the variable node updating module 203; and if the signal indicates that the decoding is correct, outputting a codeword which is successfully decoded.
Further, the control module 205 is further configured to determine whether the iteration number reaches the preset iteration maximum number when the signal indicates that the decoding is incorrect, determine that the decoding fails when the preset iteration maximum number is reached, end the iteration, and execute the iteration control when the preset iteration maximum number is not reached, and enter the next iteration.
Further, the control module 205 is further configured to perform iterative control based on the data path M1 and the data path M2, where a start node of the data path M1 is the check node update module 202, and a start node of the data path M2 is the variable node update module 203.
Further, the data transmission path of the data path M1 sequentially iterates according to the check node update module 202, the control module 205, and the variable node update module 203, and the data transmission path of the data path M2 sequentially iterates according to the variable node update module 203, the control module 205, and the check node update module 202.
Further, the check node update module 202 is further configured to perform check node update calculation on the data path M1 and the data path M2 using different adaptive normalization factors.
In a second aspect, the present invention further provides an LDPC decoding method based on an ANMS algorithm, including: s701: receiving a codeword to be decoded, wherein the codeword to be decoded represents configuration information of different code lengths and code rates; s702: performing variable node updating calculation and/or check node updating calculation on the code word to be decoded to obtain code word information updated by the variable node and/or code word information updated by the check node; s703: judging whether the codeword to be decoded is correct or not according to the codeword information updated by the variable node and the codeword information updated by the check node, and if the codeword to be decoded is incorrect, executing the iteration in S702; and if the code word to be decoded is correct, outputting the code word which is successfully decoded.
In a third aspect, the present invention also provides an electronic device, including a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any one of the ANMS algorithm-based LDPC decoding methods described above when the program is executed.
In a fourth aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of an LDPC decoding method based on an ANMS algorithm as described in any of the above.
In a fifth aspect, the present invention also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of an ANMS algorithm-based LDPC decoding method as described in any one of the above.
According to the LDPC decoder based on the ANMS algorithm, the decoding judgment module 204 in the decoder adopts different self-adaptive normalization factor calculation formulas aiming at the data path M1 and the data path M2, and the control module 205 controls data to iterate simultaneously according to the two branches. The method and the device have the advantages that the decoding success rate is improved, meanwhile, idle resources in the decoder are effectively utilized, and the decoding performance and efficiency of the decoder are improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart depicting LDPC decoding based on the ANMS algorithm of the prior art;
fig. 2 is a functional configuration block diagram describing a decoder according to an embodiment of the present invention;
FIG. 3 is a state transition diagram depicting a control module state machine according to the present invention;
FIG. 4 is a schematic diagram depicting a control module according to the present invention;
fig. 5 is a diagram for describing a decoding scheduling manner of a decoding method according to an embodiment of the present invention;
FIG. 6 is a schematic diagram depicting a decoding decision module according to an embodiment of the invention;
fig. 7 is a flowchart describing a decoding method according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings. Embodiments of the invention and features of the embodiments may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
The names of messages or information interacted between the devices in the embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of such messages or information.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
Referring to fig. 2, fig. 2 is a functional schematic diagram of an LDPC decoder based on an ANMS algorithm according to the present invention. The decoder includes:
the configuration information module 201 is configured to receive a codeword to be decoded, and transmit the codeword to be decoded to the control module 205 and the variable node update module 203; the code word to be decoded represents configuration information of different code lengths and code rates;
the check node updating module 202 is configured to obtain codeword data output by the configuration information module 201 or the variable node updating module 203 from the control module 205, perform check node updating calculation on the codeword data (the check node updating calculation may refer to S102), thereby obtaining codeword information after the check node updating, and input the codeword information after the check node updating into the control module 205;
a variable node update module 203, configured to obtain codeword data output by the configuration information module 201 or the check node update module 202 from the control module 205, perform variable node update calculation on the codeword data (the variable node update calculation may refer to S103), thereby obtaining codeword information after variable node update, and input the codeword information after variable node update into the control module 205;
the decoding decision module 204 is configured to obtain the codeword information updated by the check node and the codeword information updated by the variable node from the control module 205, determine whether the codeword to be decoded is correct according to the codeword information updated, and send a signal indicating whether the decoding is correct to the control module;
the control module 205 receives the signal indicating whether the decoding sent by the decoding decision module 204 is correct, and if the signal indicates that the decoding is incorrect, performs iterative control: continuing to receive the codeword information updated by the check node and/or the codeword information updated by the variable node, and sending the codeword information updated by the variable node and/or the codeword information updated by the check node to the check node updating module 202 and/or the variable node updating module 203; and if the signal indicates that the decoding is correct, outputting a codeword which is successfully decoded.
The data to be decoded is configuration information such as different code lengths, code rates and the like, and the configuration information module 201 caches and transfers the configuration information;
the check node update module 202 is configured to perform check node update calculation on input data or data in iteration.
The variable node update module 203 is configured to perform variable node update calculation on input data or data in iteration.
The decoding decision module 204 (or called a check module) is configured to receive the node updated information from the check node update module 202 and the variable node update module 203, determine whether the decoded codeword is correct according to the received node updated information, and send a signal whether the decoding is correct to the control module; outputting a decoding success signal when the decoded code word is correct, outputting the decoded code word, judging whether the iteration number reaches the preset iteration maximum number when the decoded code word is wrong, determining that the decoding fails when the preset iteration number reaches a preset value, and entering the next iteration when the preset iteration number does not reach the preset value.
Optionally, the control module is configured to perform control such that when one path of decoded codeword is correct, a decoding success signal is output, and a decoded codeword is output, two paths of decoding iterations are terminated, when the decoded codeword is incorrect, it is determined whether the number of iterations reaches a preset maximum number of iterations, when the preset number of iterations reaches a preset value, a decoding failure signal is output, and when the preset maximum number of iterations is not reached, the next iteration is entered. If the data path M1 is successfully decoded, outputting the decoding result of the data path M1, and terminating the iterative process of the data paths M1 and M2.
The control module 205 receives the data transferred from the check node update module 202 (or called check node) and the data transferred from the variable node update module 203 (or called variable node) at the same time, and may transfer the input data of the variable node and the input data of the check node at the same time. Specifically, after the input information enters the input buffer module, the input information enters the check node update module 202 to obtain the check node updated data, while the buffered information enters the variable node update module 203 to obtain the variable node updated data. And then, when the updated data of the variable nodes enter the check updating nodes, the updated data of the check nodes enter the variable updating nodes.
In some embodiments, a state machine is arranged in the control module, and the state machine controls the branch controller to simultaneously receive data transmitted by the check node and data transmitted by the variable node, and can simultaneously transmit input data of the variable node and input data of the check node, and when one path of decoding is successful, two paths of iteration are controlled to be terminated, and the success of decoding is determined.
The control module divides the data iteration process into two paths, namely data paths M1 and M2, through the branch controller. The data path M1 and the data path M2 enter iteration at the same time, the difference is that the initial nodes are different, the initial node of the data path M1 is a check node, and the initial node of the data path M2 is a variable node. The data path M1 iterates in the order of check node-control module-variable node-control module-check node- …, and the data path M2 iterates in the order of variable node-control module-check node-control module-variable node- ….
The check node update module 202 is further configured to perform check node update calculation on the data path M1 and the data path M2 by using different adaptive normalization factors. The adaptive normalization factor can be obtained through two different formulas, and different adaptive normalization factors are used for processing the data path M1 and the data path M2 through the transmitted adaptive normalization factor switching signals.
In an application scenario, in the process of updating the check node by the check node, the adaptive normalization factor is obtained through two different formulas, and the data path M1 and the data path M2 are processed by using different adaptive normalization factors through the transmitted adaptive normalization factor switching signals. When the self-adaptive normalization factor switching signal is pulled up, the current data path M1 check node update is indicated, and the self-adaptive normalization factor alpha 1 is selected to perform self-adaptive normalization processing; when the self-adaptive normalization factor switching signal is pulled down, the current data path M2 check node update is indicated, and the self-adaptive normalization factor alpha 2 is selected to perform self-adaptive normalization processing.
Unlike the LDPC decoder of the prior art, the decoding decision module 204 in the LDPC decoder of the present invention adopts different adaptive normalization factor calculation formulas for the data path M1 and the data path M2, and the control module 205 controls the data to iterate according to the two branches.
The LDPC decoder control module structure of an embodiment of the present invention will be described in detail with reference to fig. 3 and 4.
Wherein, the state transition diagram of the state machine is shown in fig. 3. When in the idle state, the state machine detects that the initial information frame header signal is pulled up and then enters the initialization state. After the initial information is stored, the initial information frame tail signal is pulled up, and the state machine jumps to the state that the data path M1 uses the variable node updating module 203 (or called M1 variable) and the data path M uses the 2 check node updating module 202 (or called M2 check). Thereafter, the state machine starts counting from 0 to T, where T is the greater of the check node update time and the time required for the variable node update, and the state machine jumps to the state where data path M1 uses check node update module 202 (or M1 check), and data path M2 uses variable node update module 203 (or M2 variable). After that, the state machine starts counting from 0 to T, and then the state machine starts judging to determine whether to end decoding or skip the state of the data path M1 using the variable node update module 203 and the data path M2 using the check node update module 202.
The control module structure is schematically shown in fig. 4. The state machine 401 controls the bypass controller 402 to generate strobe signals of the selector 404, the selector 405, the selector 406, and the selector 407.
Specifically, when the current state is the initialization state, the selector 404 and the selector 405 are controlled to gate the initial information, the selector 406 is controlled to output the data output from the storage unit 408, and the selector 407 is controlled to output the data output from the storage unit 409; when the current state is the M1 variable M2 verification state, the selector 404 is controlled to gate the variable node output, the selector 405 is controlled to gate the verification node output, the selector 406 is controlled to output the data output by the storage unit 409, and the selector 407 is controlled to output the data output by the storage unit 408; when the current state is the M1 check M2 variable state, the selector 404 is controlled to gate the check node output, the selector 405 is controlled to gate the variable node output, the selector 406 is controlled to output the data output by the storage unit 408, and the selector 407 is controlled to output the data output by the storage unit 409.
The state machine 401 controls the address generator to generate the read-write addresses of the multiplexing storage unit 408 and the multiplexing storage unit 409, and performs row-column conversion to meet the requirements of updating the variable nodes column by column and checking the updating of the nodes column by column.
The decoding process of the LDPC decoder according to the present invention will be described in detail with reference to the decoding scheduling manner of fig. 5. Unlike the prior art decoder, the LDPC decoder 200 according to the embodiment of the present invention performs two-way decoding at the same time, and the decoding process of the LDPC decoder provided by the present invention mainly describes that the control module 205 in the LDPC decoder 200 controls the data flow of the two ways of data ways M1 and M2, where the check node suppression factor calculation formula of the data way M1 is α1, and the check node suppression factor calculation formula of the data way M2 is α2.
As shown in fig. 5, firstly, a codeword to be decoded is received, and then the codeword is calculated according to a data path M1 and a data path M2, wherein the suppression factors of check nodes of the data path M1 and the data path M2 are calculated according to different suppression factor adaptive formulas, so that a suppression factor calculation formula which is faster in decoding success is automatically selected under different data conditions to be decoded.
Specifically, when the input is X1 and the maximum decoding frequency is l, M iterations are needed for successful decoding through the check node suppression factor α1, n iterations are needed for successful decoding through the check node suppression factor α2, wherein M < l and n < l, if M < n, the decoding result of the data path M1 is output, and otherwise, the decoding result of the data path M2 is output; when the input is X2 and the maximum decoding frequency is l, M2 iterations are needed for successful decoding through the check node inhibition factor alpha 1, and the data path M1 decoding result is output when the check node inhibition factor alpha 2 cannot be successfully decoded in the l iterations. When the input is X3 and the maximum decoding frequency is l, the check node inhibition factor alpha 1 cannot be successfully decoded in l iterations, and n3 iterations are needed for successful decoding through the check node inhibition factor alpha 2, and then a decoding result of the data path M2 is output. When the input is X4 and the maximum decoding frequency is l, the check node inhibition factor alpha 1 cannot be successfully decoded in l iterations, and the check node inhibition factor alpha 2 cannot be successfully decoded in l iterations, so that the output decoding fails.
And initializing the LDPC decoder after receiving the code word to be decoded. The control module performs control so that the code words to be decoded respectively perform variable node update calculation according to the data path M1 input variable node update module shown in fig. 5, and the data path M2 input check node update module shown in fig. 5 performs check node update calculation.
After the variable node updating module of the data path M1 completes updating calculation, the updated information is transmitted to the check node updating module, and meanwhile, after the check node updating module of the data path M2 completes updating calculation, the updated information is transmitted to the variable node updating module. After the check node updating module of the data path M1 completes the updating calculation, the updated information is transmitted to the variable node updating module, and meanwhile, after the variable node updating module of the data path M2 completes the updating calculation, the updated information is transmitted to the check node updating module.
Thus, the code word is decoded according to two paths in the LDPC decoder, and the two paths adopt different adaptive formulas of the suppression factors (the adaptive formulas of the suppression factors can be existing), and the decoding result depends on the path with fewer iteration times caused by different suppression factors. Therefore, the decoding success rate is improved, the idle resources in the decoder are effectively utilized, and the decoding performance of the decoder is improved.
The structure of the decoding decision module 204 will be described with reference to the single check node processing unit structure of fig. 6.
And after receiving the data to be processed, the single check node processing unit firstly performs absolute value operation so as to find out the minimum value except the minimum value. And then, carrying out self-adaptive normalization processing, and outputting an original code or a complementary code according to the result of symbol exclusive OR. Where a single check node processing unit refers to the component 202 in fig. 2, is the output of the single check node processing unit.
The check node update module 202 of the present invention is characterized in that the adaptive normalization factor is obtained by two different formulas, and different adaptive normalization factors are used for processing the data path M1 and the data path M2 by the transmitted adaptive normalization factor switching signal. When the self-adaptive normalization factor switching signal is pulled up, the current data path M1 check node update is indicated, and the self-adaptive normalization factor alpha 1 is selected to perform self-adaptive normalization processing; when the self-adaptive normalization factor switching signal is pulled down, the current data path M2 check node update is indicated, and the self-adaptive normalization factor alpha 2 is selected to perform self-adaptive normalization processing.
A decoding method according to an embodiment of the present invention will be described below with reference to fig. 7. Fig. 7 is a flowchart describing a decoding method according to an embodiment of the present invention.
Before explaining the present invention, the LDPC decoding method is briefly described, and the LDPC decoding method adopts a common adaptive normalization minimum sum algorithm.
A common adaptive normalized min-sum algorithm, fig. 1 is a flowchart of LDPC decoding based on the ANMS algorithm, and includes the following steps:
s101, receiving information from a channel, and initializing: the current iteration number l=0, the maximum iteration number H, according to the received information y= (y) from the channel 1 ,y 2 ,y 3 ,…,y n ) Initializing all variable node information;
L (l) (v ij )＝L (yi) ,i＝1,2,3,…,n；
s102, updating check nodes, wherein the check node updating formula is as follows:
wherein the method comprises the steps ofIs an adaptive normalization factor;
s103, updating variable nodes, wherein the variable nodes update formula:
L (l) (v ij )＝L(y i )+∑L (l) (c j′i )；
s104, calculating posterior probability of variable nodes:
L (l) (q i )＝L(y i )+∑L (l) (c ji )
and decoding judgment: if L (l) (q i ) > 0 thenOtherwise, go (L)>Judging
If yes, decoding is correct, otherwise decoding is wrong;
s105, when the decoding is correct, determining that the decoding is successful, and outputting a code word;
s106, judging whether the maximum iteration times are reached when the decoding is incorrect;
s107, when the maximum iteration times are not reached, repeating the steps 102-105 if the check equation is not satisfied;
s108, reaching the maximum iteration times, determining decoding failure, and ending the iteration.
The above formula symbols have the meanings shown in table 1.
TABLE 1
The sequence of S102 and S103 can be exchanged. From the above decoding steps, it is determined that the check node update is completedThe ANMS algorithm adopts a variable normalization factor, and has greater flexibility in the implementation process compared with the NMS algorithm. Normalization in ANMS algorithmThe selection of factors is not a better theoretical method at present. However, the existing application has higher selection requirement on the normalization factor, so that data can be divided into two paths, and the normalization factors obtained by different normalization factor calculation formulas are used for updating check nodes.
In addition, in the LDPC decoding method of the prior art, since decoding is performed by using an information transfer manner, only one of the variable node update module or the check node update module is in an update operation and the other module is in an idle state at the same time, and such decoding method results in low system resource utilization. Therefore, the check node updating module and the variable node updating module can be multiplexed in a time sharing way, the check node updating module is used by the data branch circuit M1, the variable node updating module is used by the data branch circuit M2 or the variable node updating module is used by the data branch circuit M1, and the check node updating module is used by the data branch circuit M2 at the same time. Therefore, on the premise of not increasing check nodes and variable nodes, one iteration branch is increased.
The present invention has been made in view of these problems of the prior art, and with reference to fig. 7:
the decoding method according to the embodiment of the present invention is applied to the LDPC decoder 200 described above, and includes:
s701: and receiving a codeword to be decoded, wherein the codeword to be decoded represents configuration information of different code lengths and code rates. The codeword to be decoded may be 8064 16bit values.
S702: performing variable node updating calculation and/or check node updating calculation on the code word to be decoded to obtain code word information updated by the variable node and/or code word information updated by the check node; after initializing the codeword to be decoded, variable node update calculation and/or check node update calculation may be performed.
S703: judging whether the codeword to be decoded is correct or not according to the codeword information updated by the variable node and the codeword information updated by the check node, and if the codeword to be decoded is incorrect, executing the iteration in S702; and if the code word to be decoded is correct, outputting the code word which is successfully decoded. As an example, firstAnd (4) performing decoding judgment on the codeword information updated by the root variable node and the codeword information updated by the check node (the decoding judgment method can refer to S104), and judging whether the codeword to be decoded is correct or not according to the judgment result. The condition for judging whether the code word to be decoded is correct is thatWherein Xn represents the result of decoding judgment of the codeword information updated by the variable node or the codeword information updated by the check node, H T The transpose matrix representing the check matrix (the transpose matrix is a constant and can be set as needed).
Wherein S701 further includes receiving the codeword to be decoded and initializing the codeword to be decoded.
Wherein S702 further includes: and respectively carrying out two paths of calculation on the initialized code words to be decoded: the data path M1 performs variable node update calculation on the initialized code word to be decoded so as to obtain code word information updated by the variable node, then performs check node update calculation on the code word information updated by the variable node so as to obtain code word information updated by the check node, and then performs variable node update calculation on the code word information updated by the check node again so as to cycle; and the data path M2 performs check node updating calculation on the initialized code word to be decoded so as to obtain code word information updated by the check node, then performs variable node updating calculation on the code word information updated by the check node so as to obtain code word information updated by the variable node, and then performs check node updating calculation on the code word information updated by the variable node again so as to circulate.
Wherein S703 further includes: judging whether the codeword to be decoded is correct according to the codeword information updated by the variable node and the codeword information updated by the check node, if the codeword to be decoded is incorrect, judging whether the iteration number reaches the preset iteration maximum number, if the iteration number does not reach the preset iteration maximum number, executing the iteration in S702, if the iteration number reaches the preset iteration maximum number, decoding fails, and ending the iteration. The preset maximum number of iterations is generally determined according to MATLAB modeling simulation, and a more appropriate value is selected between the speed and the decoding performance as the preset maximum number of iterations. The larger the preset decoding times are, the better the performance is, and the slower the speed is; the smaller the preset number of decoding times, the worse the performance and the faster the speed. The preset maximum number of iterations is typically 10 to 20.
Wherein S702 further includes: and performing check node updating calculation on the data path M1 and the data path M2 by using different self-adaptive normalization factors.
It will be appreciated that what is described in this method corresponds to the various blocks in the ANMS algorithm-based LDPC decoder described with reference to fig. 2. Thus, the operations, features and beneficial effects described above for the decoder are equally applicable to the ANMS algorithm-based LDPC decoding method, and are not described in detail herein.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. An ANMS algorithm-based LDPC decoder, comprising:
the configuration information module 201 is configured to receive a codeword to be decoded, and transmit the codeword to be decoded to the control module 205 and the variable node update module 203; the code word to be decoded represents configuration information of different code lengths and code rates;
the check node updating module 202 is configured to obtain codeword data output by the configuration information module 201 or the variable node updating module 203 from the control module 205, perform check node updating calculation on the codeword data, thereby obtaining codeword information after check node updating, and input the information after check node updating into the control module 205;
the variable node updating module 203 is configured to obtain codeword data output by the configuration information module 201 or the check node updating module 202 from the control module 205, perform variable node updating calculation on the codeword data, thereby obtaining codeword information updated by the variable node, and input the updated information of the variable node into the control module 205;
the decoding decision module 204 is configured to obtain the codeword information updated by the check node and the codeword information updated by the variable node from the control module 205, determine whether the codeword to be decoded is correct according to the codeword information updated, and send a signal indicating whether the decoding is correct to the control module;
the control module 205 is configured to receive and determine whether the decoding sent by the decoding decision module 204 is correct, and if the signal indicates that the decoding is incorrect, perform iterative control: continuing to receive the codeword information updated by the check node and/or the codeword information updated by the variable node, and sending the codeword information updated by the variable node and/or the codeword information updated by the check node to the check node updating module 202 and/or the variable node updating module 203; and if the signal indicates that the decoding is correct, outputting a codeword which is successfully decoded.
2. The ANMS algorithm-based LDPC decoder of claim 1, wherein the control module 205 is further configured to, when the signal indicates that decoding is incorrect, determine whether the number of iterations reaches a preset maximum number of iterations, determine that decoding fails when the preset maximum number of iterations is reached, end an iteration, and perform iteration control when the preset maximum number of iterations is not reached, and enter a next iteration.
3. The ANMS-algorithm-based LDPC decoder according to claim 1, wherein the control module 205 is further configured to perform iterative control based on the data path M1 and the data path M2, the start node of the data path M1 is the check node update module 202, and the start node of the data path M2 is the variable node update module 203.
4. The ANMS algorithm-based LDPC decoder of claim 3, wherein the data transmission path of the data path M1 sequentially iterates according to the check node update module 202, the control module 205, and the variable node update module 203, and the data transmission path of the data path M2 sequentially iterates according to the variable node update module 203, the control module 205, and the check node update module 202.
5. The ANMS-algorithm-based LDPC decoder of claim 4, wherein the check node update module 202 is further configured to perform check node update calculations on the data path M1 and the data path M2 using different adaptive normalization factors.
6. An ANMS algorithm-based LDPC decoding method, the method operating on an ANMS algorithm-based LDPC decoder of any of claims 1-5, the decoding method comprising:
s701: receiving a codeword to be decoded, wherein the codeword to be decoded represents configuration information of different code lengths and code rates;
s702: performing variable node updating calculation and/or check node updating calculation on the code word to be decoded to obtain code word information updated by the variable node and/or code word information updated by the check node;
s703: judging whether the codeword to be decoded is correct or not according to the codeword information updated by the variable node and the codeword information updated by the check node, and if the codeword to be decoded is incorrect, executing the iteration in S702; and if the code word to be decoded is correct, outputting the code word which is successfully decoded.
7. The ANMS-algorithm-based LDPC method of claim 6, wherein S702 further comprises:
and respectively carrying out two paths of calculation on the initialized code words to be decoded: the data path M1 performs variable node update calculation on the initialized code word to be decoded so as to obtain code word information updated by the variable node, then performs check node update calculation on the code word information updated by the variable node so as to obtain code word information updated by the check node, and then performs variable node update calculation on the code word information updated by the check node again so as to cycle; and the data path M2 performs check node updating calculation on the initialized code word to be decoded so as to obtain code word information updated by the check node, then performs variable node updating calculation on the code word information updated by the check node so as to obtain code word information updated by the variable node, and then performs check node updating calculation on the code word information updated by the variable node again so as to circulate.
8. The ANMS-algorithm-based LDPC method of claim 6, wherein S703 further comprises: judging whether the codeword to be decoded is correct according to the codeword information updated by the variable node and the codeword information updated by the check node, if the codeword to be decoded is incorrect, judging whether the iteration number reaches the preset iteration maximum number, if the iteration number does not reach the preset iteration maximum number, executing the iteration in S702, if the iteration number reaches the preset iteration maximum number, decoding fails, and ending the iteration.
9. The ANMS-algorithm-based LDPC method of claim 7, wherein S702 further comprises: and performing check node updating calculation on the data path M1 and the data path M2 by using different self-adaptive normalization factors.
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