CN111464190B - Method and device for exchanging, checking and decoding LDPC code and CRC - Google Patents

Method and device for exchanging, checking and decoding LDPC code and CRC Download PDF

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CN111464190B
CN111464190B CN202010410388.8A CN202010410388A CN111464190B CN 111464190 B CN111464190 B CN 111464190B CN 202010410388 A CN202010410388 A CN 202010410388A CN 111464190 B CN111464190 B CN 111464190B
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CN111464190A (en
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陈容
陈岚
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Institute of Microelectronics of CAS
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

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Abstract

The present disclosure provides an exchange check decoding method and device combining LDPC code and CRC, the method includes: step 1, judging whether to use CRC in the iterative process of iterative decoding by using LDPC codes
Figure DDA0002491627550000011
Step 2, if
Figure DDA0002491627550000012
The CRC detection is passed, and then whether the H matrix check is performed is judged
Figure DDA0002491627550000013
Step 3, if
Figure DDA0002491627550000014
The decoding is completed. The decoding system and the decoding method can reduce the calculation complexity of the decoder and improve the decoding efficiency on the premise of not changing the reliability of the decoding system.

Description

Method and device for exchanging, checking and decoding LDPC code and CRC
Technical Field
The present disclosure relates to the field of communications, and in particular, to an exchange check decoding method and apparatus combining an LDPC code and a CRC.
Background
Low-density parity-check (LDPC) codes are a kind of error correction codes with strong error correction capability, and were first proposed by Galleger at MIT in the 60's of the 20 th century. The LDPC code has the advantages of simple description, low decoding complexity, parallel realization, flexible use, low error floor and the like, and is widely applied to practical systems. Among the decoding algorithms of LDPC codes, the most widely studied and applied is the Belief Propagation Algorithm (BPA) decoding Algorithm and its improved Algorithm. This class of algorithms corrects errors that may occur in information bits by iteratively passing confidence messages between variable nodes and check nodes.
In order to improve transmission reliability and determine the correctness of the data at the receiving end, in addition to using channel coding techniques, check bits are usually added at the end of the transmitted data. Cyclic Redundancy Check (CRC) is widely used in communication systems because of its strong error code detection capability and excellent anti-interference performance. In recent years, with the development of channel coding, especially the application of Turbo code and LDPC code based on iterative decoding, CRC is added to channel decoding to participate in the iterative process.
The CRC is combined with the channel coding, which can reduce the error floor of decoding, improve the reliability of the system, and can be used as an error detection mechanism in a retransmission scheme. And the method can be used as a condition for terminating iteration in advance and improve the decoding efficiency when being added into the decoding iteration of the Turbo code and the LDPC code. Therefore, in the new generation of wireless communication systems, the use of iterative decoding and CRC concatenation is a necessary trend.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides an LDPC code and CRC combined exchange check decoding method and apparatus to at least partially solve the above-mentioned technical problems.
(II) technical scheme
According to one aspect of the present disclosure, there is provided an exchange check decoding method combining an LDPC code and a CRC, including:
step 1, in the iterative process of LDPC code iterative decoding, whether to judge through CRC
Figure BDA0002491627530000021
Step 2, if
Figure BDA0002491627530000022
The CRC detection is passed, and then whether the H matrix check is performed is judged
Figure BDA0002491627530000023
Step 3, if
Figure BDA0002491627530000024
The decoding is completed.
In some embodiments of the present disclosure, further comprising:
step 4, if
Figure BDA0002491627530000025
If the CRC fails, judging whether the maximum iteration number is reached;
and 5, if the maximum iteration times is reached, finishing decoding and retransmitting.
In some embodiments of the present disclosure, step 4 is followed by:
and 6, if the maximum iteration times are not reached, returning to the step 1 to adopt the LDPC code to perform iterative decoding again.
In some embodiments of the present disclosure, further comprising:
step 7, obtaining the result through H matrix check judgment
Figure BDA0002491627530000026
If so, go to step 4 to determine whether the maximum number of iterations has been reached.
In some embodiments of the present disclosure, step 1 further comprises:
step 0, initializing LDPC code iterative decoding, calculating initial probability likelihood ratio message L (P) transmitted to variable node by channel i ) Then, for each variable node i and the check node j ∈ C (i) adjacent to the variable node i, setting the initial value of the variable node message
L (0) (q ij )=L(P i )
Wherein, L (q) ij ) Representing variable node messages, namely external probability likelihood ratio messages transmitted to the variable nodes by the check nodes; c (i) represents the set of check nodes connected to variable node i.
In some embodiments of the present disclosure, the step 1 comprises:
substep 11, for all check nodes j and variable nodes i e R (j) adjacent to the check nodes j, calculating check node information during the first iteration, namely external probability likelihood ratio information transmitted to the check nodes by the variable nodes
Figure BDA0002491627530000027
Wherein, L (q) ij ) Representing variable node messages; l (r) ji ) Representing check node messages; r (j) represents a set of variable nodes connected to check node i;
a substep 12 of calculating variable node messages for the first iteration for all variable nodes i and check nodes j ∈ C (i) adjacent to the variable nodes i
Figure BDA0002491627530000031
Wherein C (i) represents a set of check nodes connected to variable node i;
substep 13 of calculating decision quantity information for all variable nodes
Figure BDA0002491627530000032
Wherein, L (q) i ) Representing all the messages collected by the variable node i;
substep 14, calculating the structure according to the variable nodes, making a decision, if L (l) (q i ) If greater than 0, then
Figure BDA0002491627530000033
If L is (l) (q i ) When the ratio is less than or equal to 0, then
Figure BDA0002491627530000034
Substep 15, obtaining the front k bit decision information
Figure BDA0002491627530000035
Multiplying by parallel computing matrix M of CRC, and judgingWhether or not to break
Figure BDA0002491627530000036
According to an aspect of the present disclosure, there is also provided an exchange check decoding apparatus combining an LDPC code and a CRC, including:
the CRC detection module is used for judging whether CRC detection is passed or not in the iterative process of LDPC code iterative decoding;
and the H matrix checking module is used for carrying out H matrix checking after the CRC detection of the CRC detection module.
In some embodiments of the present disclosure, further comprising:
the maximum iteration time detection module is used for judging whether the maximum iteration time is reached or not when the CRC of the CRC detection module or the H matrix check of the H matrix check module fails; if the maximum iteration times are reached, decoding is finished and retransmission is carried out; if the maximum iteration times are not reached, the iterative decoding of the LDPC code is carried out again.
(III) advantageous effects
It can be seen from the above technical solutions that the method and apparatus for LDPC code and CRC combined exchange check decoding disclosed in the present disclosure have at least one or a part of the following beneficial effects:
(1) According to the LDPC code decoding method and device, CRC is added in the LDPC code decoding process, on the premise that the reliability of a decoding system is not changed, the calculation complexity of a decoder can be reduced, and the decoding efficiency can be improved.
(2) According to the method, CRC detection is placed before matrix check of the LDPC code, check sequence is exchanged, and the calculation complexity of a decoder is reduced.
(3) According to the method and the device, the iterative decoding of the LDPC code is subjected to feedback control through CRC detection, and the decoding efficiency is improved.
Drawings
Fig. 1 is a logic diagram of an LDPC code and CRC combined exchange check decoding method according to an embodiment of the present disclosure.
Fig. 2 is a flow chart of an example LDPC code and CRC combined cross check decoding method according to the present disclosure.
Fig. 3 is a schematic diagram of the LDPC code word after CRC is added.
Detailed Description
The present disclosure provides an exchange check decoding method and device combining LDPC code and CRC, the method includes: in the iterative decoding process, CRC detection is placed before matrix check, if the CRC detection passes, the matrix check is continued, and if the CRC passes, decoding is successful and output; if the CRC detection is not passed or the matrix check is not passed, the iteration is continued until the check is passed or the maximum iteration times is reached, the decoding is finished and the retransmission is carried out. The decoding system and the decoding method can reduce the calculation complexity of the decoder and improve the decoding efficiency on the premise of not changing the reliability of the decoding system.
To make the objects, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail below with reference to specific embodiments and the accompanying drawings.
Certain embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
The CRC and the channel coding are used in cascade, which may improve the reliability of the system, but in the iterative decoding, as a part of the feedback loop, the delay of the decoding may be increased, which may affect the throughput of the decoder. In the decoding process of the LDPC code, a matrix check is provided to detect whether decoding is successful, and if the matrix check is directly replaced by CRC detection, the reliability of a decoding system is influenced by the omission condition of CRC.
In a first exemplary embodiment of the present disclosure, an exchange check decoding method combining an LDPC code and a CRC is provided, and by exchanging the order of CRC and matrix check, the computational complexity of a decoder may be effectively reduced and the decoding efficiency may be improved without changing the reliability of a decoding system. Fig. 1 is a logic diagram of an LDPC code and CRC combined exchange check decoding method according to an embodiment of the present disclosure. Fig. 2 is a flow chart of an example LDPC code and CRC combined cross check decoding method according to the present disclosure. As shown in fig. 1 and fig. 2, the method for decoding an LDPC code and CRC in an exchange check manner includes:
step 0, initializing LDPC code iterative decoding, calculating initial probability likelihood ratio information L (P) transmitted to variable node by channel i ) Then, setting an initial message transmitted from the variable node to the check node for each variable node i and the check node j ∈ C (i) adjacent to the variable node i
L (0) (q ij )=L(P i )
Wherein, L (q) ij ) An external probability likelihood ratio message representing the variable node i passing to the check node j; c (i) represents the set of check nodes connected to variable node i.
Step 1, in the iterative process of LDPC code iterative decoding, whether to judge through CRC
Figure BDA0002491627530000051
In the embodiment of the present disclosure, the LDPC code iterative decoding adopts a Minimum Sum Algorithm (MSA), and the specific step 1 includes:
substep 11, for all check nodes j and variable nodes i ∈ R (j) adjacent to the check nodes j, calculating check node information during the first iteration
Figure BDA0002491627530000052
Wherein, L (q) ij ) Representing variable node messages, namely external probability likelihood ratio messages transmitted to the variable nodes by the check nodes; l (r) ji ) Representing check node messages, namely external probability likelihood ratio messages transmitted to the check nodes by the variable nodes; r (j) represents a set of variable nodes connected to check node i;
substep 12, for all variable nodes i and check nodes j belonged to C (i), calculating variable node information in the first iteration
Figure BDA0002491627530000053
Wherein C (i) represents a set of check nodes connected to variable node i;
substep 13, calculating decision quantity information for all variable nodes
Figure BDA0002491627530000054
Wherein, L (q) i ) All the messages collected by the variable node i are represented;
substep 14, according to the variable node calculation structure, making decision, if L (l) (q i ) If greater than 0, then
Figure BDA0002491627530000055
If L is (l) (q i ) When the ratio is less than or equal to 0, then
Figure BDA0002491627530000056
A substep 15 of obtaining the first k bit decision information
Figure BDA0002491627530000057
Multiplying the CRC parallel calculation matrix M to judge whether to carry out multiplication or not
Figure BDA0002491627530000058
Step 2, if
Figure BDA0002491627530000059
The CRC detection is passed, and then whether the H matrix check is performed is judged
Figure BDA0002491627530000061
Specifically, the first k bit decision information obtained in the substep 15
Figure BDA0002491627530000062
Multiplying the H matrix to judge whether the check relation of the H matrix is met, namely judging whether the check relation of the H matrix is met
Figure BDA0002491627530000063
Step 3, if
Figure BDA0002491627530000064
Then decoding is completed;
step 4, if in step 2
Figure BDA0002491627530000065
If the CRC fails, judging whether the maximum iteration number is reached;
step 5, if the maximum iteration times is reached, decoding is finished and retransmission is carried out;
and 6, if the maximum iteration times are not reached, returning to the step 1 to adopt the LDPC code to perform iterative decoding again.
In a first exemplary embodiment of the present disclosure, there is also provided an LDPC code and CRC combined exchange check decoding apparatus, including
And the CRC detection module is used for judging whether the LDPC code passes CRC detection in the iterative process of the LDPC code iterative decoding.
And the H matrix checking module is used for carrying out H matrix checking after the CRC detection of the CRC detection module passes.
A maximum iteration number detection module for judging whether the maximum iteration number is reached or not when the CRC detection (or the H matrix check of the H matrix check module) used for the CRC detection module fails; if the maximum iteration times are reached, decoding is finished and retransmission is carried out; if the maximum iteration times are not reached, the LDPC code iterative decoding is carried out again.
Fig. 3 is a schematic diagram of the LDPC code word after CRC is added. As shown in fig. 3, n is the total length after encoding, k is the information bit length (including r CRC check bits), and m = n-k is the added encoded redundancy bits.
In a second exemplary embodiment of the present disclosure, an exchange check decoding method of combining an LDPC code with a CRC is provided. Compared with the LDPC code and CRC combined exchange check decoding method of the first embodiment, the LDPC code and CRC combined exchange check decoding method of this embodiment further includes, after step 2, when step 2 fails to pass the H matrix check:
step 7, obtaining the result through H matrix check judgment
Figure BDA0002491627530000066
If so, entering step 4 to judge whether the maximum iteration times is reached;
step 5, if the maximum iteration times is reached, decoding is finished and retransmission is carried out;
and 6, if the maximum iteration times are not reached, returning to the step 1 to adopt the LDPC code to perform iterative decoding again.
For the purpose of brief description, any technical features of the first embodiment that can be applied to the same are described herein, and the same description is not repeated.
CRC is generally implemented by a Linear Feedback Shift Register (LFSR), and with the development of technology, data storage and transmission speeds have been greatly increased, and a conventional serial algorithm has not been able to meet the requirements, and a parallel algorithm with a faster speed must be used. The matrix-based parallel algorithm is widely adopted due to high execution speed and less occupied hardware resources. The main principle is to deduce a matrix M of parallel computation through a serial algorithm, and then obtain a CRC result through matrix multiplication. If it is
Figure BDA0002491627530000071
The CRC passes and the check succeeds, otherwise it does not pass.
For an LDPC code of (n, k), n is the total length after encoding, k is the information bit length (including r CRC check bits), and m = n-k is the added encoded redundancy bits. The check matrix of the LDPC code is defined as a sparse matrix H m×n Each iteration of the message, the codeword decided in sub-step 14 is
Figure BDA0002491627530000072
CRC uses parallel computation, whose computation matrix can be denoted as M k×r
Calculated by one time of H matrix check
Figure BDA0002491627530000073
The computational complexity is: mn multiplications and m (n-1) additions;
calculated through one CRC detection
Figure BDA0002491627530000074
The computational complexity is: rk times multiplication and r (k-1) addition.
Since r < m and k < n are usually the case, the complexity of one CRC calculation is less than that of one H matrix check calculation.
Assuming that the average number of iterations of decoding is I a Then, if CRC is concatenated after LDPC code iteration, I is needed a sub-H matrix check and 1 CRC check, for a total of (mnI) a + rk) multiplications and (m (n-1) I a + r (k-1)) times of addition.
The CRC detection is placed before the H matrix check, only one time of H matrix check and I is needed a Secondary CRC detection, total required (rkI) a + mn) multiplications and (r (k-1) I a + m (n-1)) times of addition operation.
Compared with the common cascade decoding method, the switching check decoding method provided by the invention can reduce the calculation complexity, and simultaneously comprises H matrix check and CRC detection in the decoding process, thereby ensuring the high reliability of the decoding system. And CRC detection is used as a part of iterative decoding, feedback control is carried out on decoding, and decoding efficiency is improved.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should clearly recognize that the LDPC code and CRC combined exchange check decoding method of the present disclosure.
In summary, the present disclosure provides an exchange check decoding method combining LDPC codes and CRC, which can reduce the computational complexity of a decoder and improve the decoding efficiency without changing the reliability of a decoding system.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element relative to another or relative to a method of manufacture, and is used merely to allow a given element having a certain name to be clearly distinguished from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose systems may also be used with the teachings herein. The required structure for constructing such a system is apparent from the description above. Moreover, this disclosure is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the disclosure as described herein, and any descriptions above of specific languages are provided for disclosure of enablement and best mode of the present disclosure.
The disclosure may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. Various component embodiments of the disclosure may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some or all of the components in the relevant apparatus according to embodiments of the present disclosure. The present disclosure may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present disclosure may be stored on a computer-readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (7)

1. An exchange check decoding method combining LDPC codes and CRC comprises the following steps:
step 1, in the iterative process of LDPC code iterative decoding, whether to judge through CRC
Figure FDA0003883636130000011
Step 2, if
Figure FDA0003883636130000012
The CRC detection is passed, and then whether the H matrix check is performed is judged
Figure FDA0003883636130000013
Step 3, if
Figure FDA0003883636130000014
Then decoding is completed;
wherein the step 1 comprises:
substep 11, for all check nodes j and variable nodes i e R (j) adjacent to the check nodes j, calculating check node information during the first iteration, namely external probability likelihood ratio information transmitted to the check nodes by the variable nodes
Figure FDA0003883636130000015
Wherein, L (q) ij ) Representing variable node messages; l (r) ji ) Representing check node messages; r (j) represents a set of variable nodes connected to the check node i;
a substep 12 of calculating variable node messages for the first iteration for all variable nodes i and check nodes j ∈ C (i) adjacent to the variable nodes i
Figure FDA0003883636130000016
Wherein C (i) represents a set of check nodes connected to variable node i;
substep 13, calculating decision quantity information for all variable nodes
Figure FDA0003883636130000017
Wherein, L (q) i ) Representing all the messages collected by the variable node i;
substep 14, according to the variable node calculation structure, making decision, if L (l) (q i ) If greater than 0, then
Figure FDA0003883636130000018
If L is (l) (q i ) When the ratio is less than or equal to 0, then
Figure FDA0003883636130000019
Substep 15, obtaining the front k bit decision information
Figure FDA00038836361300000110
Multiplying the CRC parallel calculation matrix M to judge whether to carry out multiplication or not
Figure FDA00038836361300000111
2. The LDPC code and CRC combined exchange check decoding method according to claim 1, further comprising:
step 4, if
Figure FDA00038836361300000112
If the CRC fails, judging whether the maximum iteration number is reached;
and 5, if the maximum iteration times is reached, finishing decoding and retransmitting.
3. The method for LDPC code and CRC combined exchange check decoding according to claim 2, wherein step 4 is followed by further comprising:
and 6, if the maximum iteration times are not reached, returning to the step 1 to adopt the LDPC code to perform iterative decoding again.
4. The LDPC code and CRC combined exchange check decoding method according to claim 2, further comprising:
step 7, obtaining the result through H matrix check judgment
Figure FDA0003883636130000021
If so, go to step 4 to determine whether the maximum number of iterations has been reached.
5. The method for LDPC code and CRC combined exchange check decoding according to claim 1, wherein the step 1 further includes:
step 0, initializing LDPC code iterative decoding, calculating initial probability likelihood ratio message L (P) transmitted to variable node by channel i ) Then, for each variable node i and the check node j ∈ C (i) adjacent to the variable node i, setting the initial value of the variable node message
L (0) (q ij )=L(P i )
Wherein, L (q) ij ) Representing variable node messages, namely external probability likelihood ratio messages transmitted to the variable nodes by the check nodes; c (i) represents a set of check nodes connected to variable node i.
6. An exchange check decoding device combining LDPC codes and CRC comprises:
the CRC detection module is used for judging whether CRC detection is passed or not in the iterative process of LDPC code iterative decoding;
the H matrix check module is used for carrying out H matrix check after the CRC detection of the CRC detection module passes;
wherein the CRC detection module is configured to:
substep 11, for all check nodes j and variable nodes i e R (j) adjacent to the check nodes j, calculating check node information during the first iteration, namely external probability likelihood ratio information transmitted to the check nodes by the variable nodes
Figure FDA0003883636130000031
Wherein, L (q) ij ) Representing variable node messages; l (r) ji ) Representing check node messages; r (j) represents a set of variable nodes connected to check node i;
a substep 12 of calculating variable node messages for the first iteration for all variable nodes i and check nodes j ∈ C (i) adjacent to the variable nodes i
Figure FDA0003883636130000032
Wherein C (i) represents a set of check nodes connected to variable node i;
substep 13, calculating decision quantity information for all variable nodes
Figure FDA0003883636130000033
Wherein, L (q) i ) Representing all the messages collected by the variable node i;
substep 14, calculating the structure according to the variable nodes, making a decision, if L (l) (q i ) If greater than 0, then
Figure FDA0003883636130000034
If L is (l) (q i ) When the ratio is less than or equal to 0, then
Figure FDA0003883636130000035
Substep 15, obtaining the front k bit decision information
Figure FDA0003883636130000036
Multiplying the CRC parallel calculation matrix M to judge whether to carry out multiplication or not
Figure FDA0003883636130000037
7. The LDPC code and CRC combined exchange check decoding apparatus according to claim 6, further comprising:
the maximum iteration number detection module is used for judging whether the maximum iteration number is reached or not when the CRC detection of the CRC detection module or the H matrix check of the H matrix check module fails; if the maximum iteration times are reached, decoding is finished and retransmission is carried out; if the maximum iteration times are not reached, the iterative decoding of the LDPC code is carried out again.
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