CN116599343A - High-gain Sepic converter and control method thereof - Google Patents

High-gain Sepic converter and control method thereof Download PDF

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Publication number
CN116599343A
CN116599343A CN202310885650.8A CN202310885650A CN116599343A CN 116599343 A CN116599343 A CN 116599343A CN 202310885650 A CN202310885650 A CN 202310885650A CN 116599343 A CN116599343 A CN 116599343A
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diode
inductance
terminal
voltage
gain
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CN202310885650.8A
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CN116599343B (en
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乐卫平
林桂浩
唐亚海
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Shenzhen CSL Vacuum Science and Technology Co Ltd
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Shenzhen CSL Vacuum Science and Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

Abstract

The application discloses a high-gain Sepic converter and a control method thereof, wherein the converter comprises a power supply V g A switch tube S, a resistor R and a diode D 1 ‑D 6 Diode D r 、D o 、D s Inductance L 1 ‑L 4 Voltage doubling capacitor C r1 And C r2 Parasitic capacitance C s And output capacitance C o The method comprises the steps of carrying out a first treatment on the surface of the The application has the advantages that: (1) Parasitic capacitance C s Inductance L 3 And L 4 Constructing a resonant network to achieve ZVS of the switching tube S; when S is closed, capacitor C r2 Through diode D r Charging; when S is disconnected, is applied to the inductance L 3 And L 4 The voltage of the voltage-variable circuit is higher than that of a traditional Sepic circuit, so that high gain is realized and the voltage stress of a device is reduced; (2) Only one switching tube is needed, so that the cost is saved and the circuit is simplified; (3) Under different modes, the switching tube can realize five working modes, and the application scene is expanded; (4) The parallel design of the inductor can reduce the output current ripple in CCM mode.

Description

High-gain Sepic converter and control method thereof
Technical Field
The application mainly relates to the technical field of converters, in particular to a high-gain Sepic converter and a control method thereof.
Background
In the prior art, in the process of etching a chip, an etching machine needs the chip to have high-voltage positive charges to adsorb electrons, and after etching is finished, the chip needs to have high-voltage negative charges to repel electrons. In the implementation of high voltage direct current, there are a number of ways by which: (1) The alternating current is boosted by a transformer and then rectified to form high-voltage direct current; (2) Converting the low-voltage direct current into alternating current through an inverter, boosting the alternating current through a transformer, and rectifying to form high-voltage direct current; (3) boosting is achieved using DC-DC conversion in the power electronics. However, the boost converter of the prior art has the following disadvantages: (1) The method of boosting and rectifying the direct current inversion through the transformer is adopted, and more steps are easy to generate larger energy loss; (2) The alternating current is directly boosted and rectified, and the device can face serious stress problem under the high-voltage environment; (3) The output EMI of the converter is higher, the voltage gain is smaller, the duty ratio required for realizing higher gain is larger, the circuit structure is complex, and the cost is high.
Therefore, how to design a boost converter with large voltage gain, small stress, small output EMI, small energy loss, simple circuit structure and low cost is a technical problem to be solved.
Disclosure of Invention
In view of the above, it is necessary to provide a high-gain Sepic converter and a control method thereof, which address the problems of the prior art.
In a first aspect, an embodiment of the present application provides a high-gain Sepic converter, including a power supply V g A switch S, a resistor R and a first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Fifth diode D 5 Sixth diode D 6 Seventh diode D r Output diode D o Parasitic diode D s First inductor L 1 Second inductance L 2 Third inductance L 3 Fourth inductance L 4 First voltage-multiplying capacitor C r1 Second voltage-multiplying capacitor C r2 Parasitic capacitance C s And output capacitance C o ；
Wherein, the power supply V g Respectively with the positive terminal of the first inductor L 1 Is the first of (2)One end and a first diode D 1 Is electrically connected with the positive terminal of the power supply V g The negative terminal of (a) is respectively connected with the second terminal of the switch tube S and the parasitic diode D s Positive terminal of (C), parasitic capacitance s Second terminal of (2), voltage doubling capacitor C r2 Second terminal of (2), output capacitance C o Is electrically connected to the second terminal of resistor R;
second diode D 2 Respectively with the positive terminal of the first inductor L 1 Second terminal of (D) and third diode D 3 A second diode D electrically connected to the positive terminal of 2 Respectively with the negative terminal of the first diode D 1 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected to the first end of the first connector; first inductance L 1 Is connected with the first end of the first diode D 1 Is electrically connected with the positive electrode terminal of the battery; third diode D 3 And a second inductance L 2 Is electrically connected to the second end of the first circuit board;
fifth diode D 5 Respectively with the third inductor L 3 Second terminal of (D) and sixth diode D 6 A fifth diode D electrically connected to the positive terminal of (C) 5 Respectively with the negative terminal of the fourth diode D 4 And a fourth inductance L 4 Is electrically connected to the first end of the first connector;
first voltage-multiplying capacitor C r1 Respectively with the first end of the switch tube S and the parasitic diode D s Negative terminal of (C), parasitic capacitance s A first end, a seventh diode D r Positive terminal of (D) third diode D 3 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected with the second end of the first voltage-doubling capacitor C r1 Respectively with the second end of the fourth diode D 4 Positive terminal, third inductance L 3 Is connected to the first terminal of the output diode D o Is electrically connected with the positive electrode terminal of the battery;
second voltage-multiplying capacitor C r2 Respectively with the seventh diode D r The negative terminal, the fourth inductance L 4 Second terminal of (D) and sixth diode D 6 Is electrically connected with the negative electrode end of the battery; sixth diode D 6 The positive terminal of the third inductor is electrically connected with the first terminal of the third inductor;
output capacitor C o Respectively with the first end of the output diode D o Is electrically connected to the negative terminal of the resistor R;
the third end of the switch tube S is connected with the control circuit, and the first end and the second end of the resistor R form an output end.
In a second aspect, an embodiment of the present application provides a method for controlling a high-gain Sepic converter, including the following steps:
generating a control signal, and transmitting the control signal to a third end of the switching tube S;
and controlling the on-off of the switching tube S according to the control signal, so that the converter alternately works in a plurality of working modes in one working period.
Preferably, the plurality of working modes are five working modes, and the five working modes are a first working mode, a second working mode, a third working mode, a fourth working mode and a fifth working mode respectively.
Preferably, the first working mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 Seventh diode D r And output diode D o Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Respectively through diode D r And diode D o Voltage-doubling capacitor C r2 Charging; through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Is reduced linearly.
Preferably, the second working mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 And parasitic diode D s Conduction and parasitic capacitance C s Third inductance L 3 And a fourth inductance L 4 Resonance occurs.
Preferably, the third working mode is: the switch S is turned off, the parasitic diode D s First diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
Preferably, the fourth operation mode is: the switch S is turned on, the first diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
Preferably, the fifth working mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 To parasitic capacitance C s Charging up to parasitic capacitance C s Voltage of (2) and second voltage-multiplying capacitor C r2 Is equal to the voltage of the other.
Compared with the prior art, the high-gain Sepic converter has the following advantages: (1) Parasitic capacitance C s Inductance L 3 And inductance L 4 Forming a resonant network, implementing Zero Voltage Switching (ZVS) of the switching tube S, diode D r And a second voltage-multiplying capacitor C r2 Forming a voltage multiplication unit; when the switch is closed, the second voltage-multiplying capacitor C r2 Through a seventh diode D r Charging; when the switch is turned on, it is applied to the third inductor L 3 And a fourth inductance L 4 The voltage of the voltage-controlled circuit is higher than that of a traditional Sepic circuit, so that the voltage stress of a device is reduced while high gain is realized; (2) The high-output converter structure is realized by only using one switching tube and circuit element in the circuit, so that the cost is saved and the circuit structure is simplified; (3) SwitchFive different working modes can be realized under the on-off mode of the pipe S, so that various changes of the modes are realized, and the application scene of the converter is expanded; (4) First inductance L 1 And a second inductance L 2 The parallel design of the circuit enables the circuit to reduce the output current ripple in the CCM mode; (5) Compared with other high-gain converters, the high-gain converter has the advantages of simple circuit structure, simple control scheme, fewer power devices, high efficiency, low cost, small switching loss, low output EMI and the like.
Drawings
Exemplary embodiments of the present application may be more fully understood by reference to the following drawings. The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate the application and together with the embodiments of the application, and not constitute a limitation to the application. In the drawings, like reference numerals generally refer to like parts or steps.
FIG. 1 is a circuit diagram of a prior art Sepic chopper circuit;
FIG. 2 is a circuit diagram of a prior art soft-switch based Sepic converter;
fig. 3 is a circuit diagram of a high gain Sepic converter according to an exemplary embodiment of the present application;
fig. 4 is a control circuit diagram of a high-gain Sepic converter according to an exemplary embodiment of the present application;
FIG. 5 is a waveform diagram of a duty cycle of a high gain Sepic converter according to an exemplary embodiment of the present application;
fig. 6 is a circuit diagram of a first operation mode of a high-gain Sepic converter according to an exemplary embodiment of the present application;
FIG. 7 is a second operational mode circuit diagram of a high gain Sepic converter according to an exemplary embodiment of the present application;
FIG. 8 is a third operational mode circuit diagram of a high gain Sepic converter according to an exemplary embodiment of the present application;
FIG. 9 is a fourth operational mode circuit diagram of a high gain Sepic converter according to an exemplary embodiment of the present application;
FIG. 10 is a fifth operational mode circuit diagram of a high gain Sepic converter according to an exemplary embodiment of the present application;
fig. 11 is a flowchart of a control method of a high-gain Sepic converter according to another exemplary embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a prior art Sepic chopper circuit has a voltage gain derived from the following formula (1):
（1）；
wherein D is the duty cycle of the switching tube S, and the voltage gain M is only related to the duty cycle of the switching tube S. When D >0.5, the converter is in boost mode; when D <0.5, the converter is in buck mode.
Referring to fig. 2, a circuit diagram of a Sepic converter in the prior art is shown, where the converter includes three inductors, three capacitors, a diode, a parasitic capacitor, a switching tube, and a resistive load R, and the structure of the converter combines the advantages of the Sepic chopper circuit, so that the conversion efficiency of the converter is significantly improved, but the converter still has the problems of higher output EMI, smaller voltage gain, larger duty ratio required when higher gain is realized, complex circuit structure, and high cost.
Based on this, an embodiment of the present application provides a high-gain Sepic converter, which is described below with reference to the accompanying drawings.
Referring to FIG. 3, a high gain Sepic converter includes a power supply V g A switch S, a resistor R and a first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Fifth diode D 5 Sixth diode D 6 Seventh diode D r Output diode D o Parasitic diode D s First inductor L 1 Second inductance L 2 Third inductance L 3 Fourth inductance L 4 First voltage-multiplying capacitor C r1 Second voltage-multiplying capacitor C r2 Parasitic capacitance C s And output capacitance C o ；
Wherein, the power supply V g Respectively with the positive terminal of the first inductor L 1 Is connected to the first terminal of the first diode D 1 Is electrically connected with the positive terminal of the power supply V g The negative terminal of (a) is respectively connected with the second terminal of the switch tube S and the parasitic diode D s Positive terminal of (C), parasitic capacitance s A second terminal of (C), a second voltage-multiplying capacitor C r2 Second terminal of (2), output capacitance C o Is electrically connected to the second terminal of resistor R;
second diode D 2 Respectively with the positive terminal of the first inductor L 1 Second terminal of (D) and third diode D 3 A second diode D electrically connected to the positive terminal of 2 Respectively with the negative terminal of the first diode D 1 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected to the first end of the first connector; first inductance L 1 Is connected with the first end of the first diode D 1 Is electrically connected with the positive electrode terminal of the battery; third diode D 3 And a second inductance L 2 Is electrically connected to the second end of the first circuit board;
fifth diode D 5 Respectively with the third inductor L 3 Second terminal of (D) and sixth diode D 6 A fifth diode D electrically connected to the positive terminal of (C) 5 Respectively with the negative terminal of the fourth diode D 4 And a fourth inductance L 4 Is electrically connected to the first end of the first connector;
first voltage-multiplying capacitor C r1 Respectively with the first end of the switch tube S and the parasitic diode D s Negative terminal of (C), parasitic capacitance s A first end, a seventh diode D r Positive terminal of (D) third diode D 3 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected with the second end of the first voltage-doubling capacitor C r1 Respectively with the second end of the fourth diode D 4 Positive terminal, third inductance L 3 Is connected to the first terminal of the output diode D o Is electrically connected with the positive electrode terminal of the battery;
second voltage-multiplying capacitor C r2 Respectively with the seventh diode D r The negative terminal, the fourth inductance L 4 Second terminal of (D) and sixth diode D 6 Is electrically connected with the negative electrode end of the battery; sixth diode D 6 The positive terminal of the third inductor is electrically connected with the first terminal of the third inductor;
output capacitor C o Respectively with the first end and the second end of the outputPolar tube D o Is electrically connected to the negative terminal of the resistor R;
the third end of the switch tube S is connected with the control circuit, and the first end and the second end of the resistor R form an output end.
Wherein, the power supply V g Is a direct current power supply for supplying power to the first inductor L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy and apply it to the first voltage-multiplying capacitor C r1 And a second voltage-multiplying capacitor C r2 The switch tube S and the resistor R are then charged after supplying energy.
Preferably, the switching tube S is a MOS tube, a first end of the switching tube S is a drain, a second end of the switching tube S is a source, and a third end of the switching tube S is a gate; parasitic diode D s The high-speed diode is connected in parallel to the source electrode and the drain electrode of the switching tube S, is a common high-speed diode, and has the function of discharging reverse induced current generated by the inductive load when the load of the switching tube S is the inductive load, thereby playing a role of protecting the switching tube S.
Referring to fig. 4, the control circuit of the converter of this embodiment adopts PI control (PI control refers to a control deviation formed according to a given value and an actual output value, and forms a control quantity by linearly combining the proportion and integral of the deviation, so as to control a controlled object), and outputs a signal as PWM (pulse width modulation, which is an analog control manner, in which the bias of the base or the gate of a transistor is modulated according to the change of a corresponding load, so as to realize the change of the on time of the transistor or the MOS transistor, thereby realizing the change of the output of the switching regulator).
Specifically, the converter of the present embodiment controls the on and off of the switching tube S of the circuit so that the converter can alternately operate in five operating modes in one operating period, and referring to fig. 5, a waveform diagram of the converter in one operating period is shown, where at t 0 -t 1 In the time period, the converter is in a first working mode; at t 1 -t 2 In the time period, the converter is in a second working mode; at t 2 -t 3 In the time period, the converter is in a third working mode; at t 3 -t 4 During the time period, the converter is in a fourth operation mode; at t 4 -t 5 During the period, the converter is in a fifth mode of operation.
(1) At t 0 -t 1 In the time period, the converter is in the first working mode, as shown in fig. 6, the switching tube S is turned off, and the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 Seventh diode D r And output diode D o Conducting, their conducting currents being the same, and from t 0 Starting at the moment, the currents flowing through them decrease linearly, at which time the second voltage-multiplying capacitor C r2 Voltage acrossThe following relationship is satisfied:
（2）；
wherein, the liquid crystal display device comprises a liquid crystal display device,representing the output voltage +.>Representing a third inductance L 3 Is set in the above-described voltage range. At the same time, a first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Respectively through a first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 And output diode D o Store energy due to the first inductance L 1 And a second inductance L 2 The stored energy is greater than the third inductance L 3 And a fourth inductance L 4 Stored energy, so the first inductance L 1 And a second inductance L 2 Is smaller than the third inductance L 3 And a fourth inductance L 4 Is a ripple of (1); at this time, the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The voltage of (2) is represented by the following formulaThe illustration is:
（3）；
（4）；
wherein, the liquid crystal display device comprises a liquid crystal display device,、/>、/>and->Respectively represent the first inductances L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The voltage across it. When flowing through the sixth diode D 6 And output diode D o When the current drop of (2) is 0, the first operation mode is ended.
(2) At t 1 -t 2 In the time period, the converter is in the second working mode, as shown in fig. 7, at this time, the switching tube S is turned off, and the first diode D 1 Third diode D 3 Fourth diode D 4 Fifth diode D 5 Sixth diode D 6 And a seventh diode D r Conduction and parasitic capacitance C s Third inductance L 3 And a fourth inductance L 4 Resonance occurs, and referring to fig. 5, the resonance currentCan be regarded as half-sinusoid, the duration in this mode being resonance time +.>Half of the resonance time +.>The method comprises the following steps:
（5）；
when the resonance is ended, the second mode of operation is ended.
(3) At t 2 -t 3 In the period of time, the converter is in the third operation mode, as shown in fig. 8, in which the parasitic diode D of the switching tube S s First diode D 1 Second diode D 3 Fourth diode D 4 Sixth diode D 6 And output diode D o On, the voltage across the switching tube S is kept at 0, the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The voltage across the terminal is represented by the following formula:
（6）；
（7）；
in this mode of operation, the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Energy starts to be stored and the current flowing through them starts to increase linearly.
(4) At t 3 -t 4 In the time period, the converter is in the fourth operation mode, as shown in fig. 9, at this time, the driving signal of the switching tube S is not 0, the driving signal makes the switching tube S realize ZVS on, at this time, the first diode D in the circuit 1 Third diode D 3 And a seventh diode D r Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Is represented by the following formula:
（8）；
（9）；
in this mode of operation, the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The energy starts to be released and the current flowing through them continues to decrease linearly. When the drive signal is 0, the fourth operation mode ends.
(5) At t 3 -t 4 During the period, the converter is in the fourth operation mode, as shown in fig. 10, at which the switching tube S is turned off, the first diode D 1 Second diode D 3 Fourth diode D 4 Fifth diode D 5 Sixth diode D 6 And output diode D o On due to parasitic capacitance C s In parallel with the switching tube S, when the switching tube S is disconnected, the inductor starts to supply a parasitic capacitance C S Charging is performed when parasitic capacitance C s Voltage of (2) and second voltage-multiplying capacitor C r2 When the voltages of (a) are equal, the fifth operation mode ends.
Wherein, the liquid crystal display device comprises a liquid crystal display device,for the drive voltage of the switching tube, < >>As parasitic capacitance D S Voltage at two ends>To flow through parasitic capacitance D s Current of->、/>、/>And->Respectively is flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Is set in the above-described range).
In this embodiment, the second voltage-doubling capacitor C can be obtained according to the formulas (2) and (4) r2 Voltage acrossThe method comprises the following steps:
（10）；
meanwhile, according to the principle of volt-second balance, the voltages at two ends of the inductor should meet the following conditions in one period:
（11）；
referring to fig. 5, the voltage of the inductor is non-linearly transformed in the second operation mode, which may be considered as volt-second balance for simplicity of calculation, and thus, equation (11) may be expressed as:
（12）；
from this, the voltage gain of the high-gain Sepic converter of this embodiment can be calculated as:
（13）；
the constraint conditions are as follows:
（14）；
wherein T is the duration of one working period, and D is the duty cycle of the switching tube S in one working periodThe ratio of the two components is that,，/>，/>，/>，/>，/>，。
in this embodiment, when the duty ratio of the switching tube S is larger or smaller, the ZVS characteristic of the switching tube S may be lost; in particular, when the duty cycle is too small, the switching voltage will resonate to multiply during the second mode of operation; when the duty cycle is too large, the switching voltage cannot resonate to zero during the second mode of operation; therefore, for the accuracy and convenience of calculation, the duty ratio only represents the maximum duty ratio, the switching tube S is selected as a soft switch, and the switching voltage can resonate to zero again when the driving signal arrives, so that the switching voltage only has one complete resonance in the second working mode, in this case, the resonance period can be calculated without calculating the resonance amplitude, and the accuracy and the high efficiency of calculation can be ensured.
Compared with the prior art, the high-gain Sepic converter has the following advantages: (1) Parasitic capacitance C s Third inductance L 3 And a fourth inductance L 4 Forming a resonant network, realizing Zero Voltage Switching (ZVS) of the switching tube S; when the switch is closed, the second voltage-multiplying capacitor C r2 Through a seventh diode D r Charging, when the switch is opened, applied to the third inductance L 3 And a fourth inductance L 4 Is higher than that of the traditional Sepic circuit, in practiceThe voltage stress of the device is reduced while the gain is high; (2) The high-output converter structure is realized by only using one switching tube and circuit element in the circuit, so that the cost is saved and the circuit structure is simplified; (3) Five different working modes can be realized by the switching tube in the on-off mode, so that various changes of the modes are realized, and the application scene of the converter is expanded; (4) First inductance L 1 And a second inductance L 2 The parallel design of the circuit enables the circuit to reduce the output current ripple in the CCM mode; (5) Compared with other high-gain converters, the high-gain converter has the advantages of simple circuit structure, simple control scheme, fewer power devices, high efficiency, low cost, small switching loss, low output EMI and the like.
In other embodiments of the present application, a method for controlling a high-gain Sepic converter is provided, and is described below with reference to the accompanying drawings.
The methods provided in other implementations of the embodiments of the present application have the same advantageous effects as the high-gain Sepic converter provided in the foregoing embodiments of the present application, due to the same inventive concept.
Referring to fig. 11, a schematic diagram of a control method according to other embodiments of the application is shown. Since the method embodiments are substantially similar to the structural embodiments, the description is relatively simple, and reference is made to the description of the structural embodiments described above. The method embodiments described below are merely illustrative.
As shown in fig. 11, a control method of a high-gain Sepic converter may include the following steps:
s1101: generating a control signal, and transmitting the control signal to a third end of the switching tube S;
s1102: the on-off of the switching tube S is controlled according to the control signal, so that the converter alternately works in a plurality of working modes in one working period.
Specifically, the plurality of working modes are five working modes, namely a first working mode, a second working mode, a third working mode, a fourth working mode and a fifth working mode.
Specifically, the first working mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 Seventh diode D r And output diode D o Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Respectively through diode D r And diode D o For the second voltage-multiplying capacitor C r2 Charging; through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Is reduced linearly.
Specifically, the second working mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 And parasitic diode D s Conduction and parasitic capacitance C s Third inductance L 3 And a fourth inductance L 4 Resonance occurs.
Preferably, the third working mode is: the switch S is turned off, the parasitic diode D s First diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
Specifically, the fourth mode of operation is: the switch S is turned on, the first diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
Specifically, the fifth working mode is: the switching tube S is disconnectedFirst diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 To parasitic capacitance C s Charging up to parasitic capacitance C s Voltage of (2) and second voltage-multiplying capacitor C r2 Is equal to the voltage of the other.
It is noted that the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application, and are intended to be included within the scope of the appended claims and description.

Claims (10)

1. A high gain Sepic converter is characterized by comprising a power supply V g A switch S, a resistor R and a first diode D 1 Second diode D 2 Third diode D 3 Fourth diode D 4 Fifth diode D 5 Sixth diode D 6 Seventh diode D r Output diode D o Parasitic diode D s First inductor L 1 Second inductance L 2 Third inductance L 3 Fourth inductance L 4 First voltage-multiplying capacitor C r1 Second voltage-multiplying capacitor C r2 Parasitic capacitance C s And output capacitance C o ；
Wherein, the power supply V g Respectively with the positive terminal of the first inductor L 1 Is connected to the first terminal of the first diode D 1 Is electrically connected with the positive terminal of the power supply V g The negative terminal of (a) is respectively connected with the second terminal of the switch tube S and the parasitic diode D s Positive terminal of (C), parasitic capacitance s A second terminal of (C), a second voltage-multiplying capacitor C r2 Second terminal of (2), output capacitance C o Is electrically connected to the second terminal of resistor R;
second diode D 2 Respectively with the positive terminal of the first inductor L 1 Second terminal of (D) and third diode D 3 A second diode D electrically connected to the positive terminal of 2 Respectively with the negative terminal of the first diode D 1 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected to the first end of the first connector; first inductance L 1 Is connected with the first end of the first diode D 1 Is electrically connected with the positive electrode terminal of the battery; third diode D 3 And a second inductance L 2 Is electrically connected to the second end of the first circuit board;
fifth diode D 5 Respectively with the third inductor L 3 Second end and sixth diode of (2)Tube D 6 A fifth diode D electrically connected to the positive terminal of (C) 5 Respectively with the negative terminal of the fourth diode D 4 And a fourth inductance L 4 Is electrically connected to the first end of the first connector;
first voltage-multiplying capacitor C r1 Respectively with the first end of the switch tube S and the parasitic diode D s Negative terminal of (C), parasitic capacitance s A first end, a seventh diode D r Positive terminal of (D) third diode D 3 Is connected to the negative terminal of the inductor L and the second inductor L 2 Is electrically connected with the second end of the first voltage-doubling capacitor C r1 Respectively with the second end of the fourth diode D 4 Positive terminal, third inductance L 3 Is connected to the first terminal of the output diode D o Is electrically connected with the positive electrode terminal of the battery;
second voltage-multiplying capacitor C r2 Respectively with the seventh diode D r The negative terminal, the fourth inductance L 4 Second terminal of (D) and sixth diode D 6 Is electrically connected with the negative electrode end of the battery; sixth diode D 6 The positive terminal of the third inductor is electrically connected with the first terminal of the third inductor;
output capacitor C o Respectively with the first end of the output diode D o Is electrically connected to the negative terminal of the resistor R;
the third end of the switch tube S is connected with the control circuit, and the first end and the second end of the resistor R form an output end.
2. The high-gain Sepic converter of claim 1, wherein the switching tube S is a MOS transistor, a first end of the switching tube S is a drain, a second end of the switching tube S is a source, and a third end of the switching tube S is a gate.
3. The high gain Sepic converter of claim 1, wherein the control circuit is a PI control circuit.
4. A method of controlling a high gain Sepic converter according to any one of claims 1-3, comprising the steps of:
generating a control signal, and transmitting the control signal to a third end of the switching tube S;
and controlling the on-off of the switching tube S according to the control signal, so that the converter alternately works in a plurality of working modes in one working period.
5. The method for controlling a high-gain Sepic converter according to claim 4, wherein the plurality of operation modes are five operation modes, and the five operation modes are a first operation mode, a second operation mode, a third operation mode, a fourth operation mode and a fifth operation mode, respectively.
6. The method for controlling a high-gain Sepic converter according to claim 5, wherein the first operating mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 Seventh diode D r And output diode D o Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Respectively through diode D r And diode D o Voltage-doubling capacitor C r2 Charging; through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Is reduced linearly.
7. The method for controlling a high-gain Sepic converter according to claim 5, wherein the second operation mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 Sixth diode D 6 And parasitic diode D s Conduction and parasitic capacitance C s Third inductance L 3 And a fourth inductance L 4 Resonance occurs.
8. The method for controlling a high gain Sepic converter according to claim 5, whereinThe third working mode is as follows: the switch S is turned off, the parasitic diode D s First diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
9. The method for controlling a high-gain Sepic converter according to claim 5, wherein said fourth operation mode is: the switch S is turned on, the first diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 Store energy flowing through the first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 The current of (2) increases linearly.
10. The method for controlling a high-gain Sepic converter according to claim 5, wherein the fifth operating mode is: the switching tube S is disconnected, the first diode D 1 Third diode D 3 Fourth diode D 4 And a sixth diode D 6 Conduction, first inductance L 1 Second inductance L 2 Third inductance L 3 And a fourth inductance L 4 To parasitic capacitance C s Charging up to parasitic capacitance C s Voltage of (2) and second voltage-multiplying capacitor C r2 Is equal to the voltage of the other.
CN202310885650.8A 2023-07-19 2023-07-19 High-gain Sepic converter and control method thereof Active CN116599343B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110831291A (en) * 2019-11-22 2020-02-21 哈尔滨工业大学 Sepic soft switch-based LED driver and hybrid driving method thereof
CN111725993A (en) * 2020-06-17 2020-09-29 辽宁工程技术大学 High-efficiency Sepic soft switch converter and control method thereof
US20200412248A1 (en) * 2018-03-28 2020-12-31 Murata Manufacturing Co., Ltd. Voltage converter
CN114629349A (en) * 2021-09-02 2022-06-14 浙江大有实业有限公司杭州科技发展分公司 Improved high-frequency high step-up ratio SEPIC converter based on switching inductor
CN115065236A (en) * 2022-05-06 2022-09-16 江南大学 High-gain Sepic direct current converter based on three-level boosting unit
CN115864815A (en) * 2022-11-07 2023-03-28 三峡大学 Bridgeless Sepic PFC converter based on switch inductance and capacitance

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200412248A1 (en) * 2018-03-28 2020-12-31 Murata Manufacturing Co., Ltd. Voltage converter
CN110831291A (en) * 2019-11-22 2020-02-21 哈尔滨工业大学 Sepic soft switch-based LED driver and hybrid driving method thereof
CN111725993A (en) * 2020-06-17 2020-09-29 辽宁工程技术大学 High-efficiency Sepic soft switch converter and control method thereof
CN114629349A (en) * 2021-09-02 2022-06-14 浙江大有实业有限公司杭州科技发展分公司 Improved high-frequency high step-up ratio SEPIC converter based on switching inductor
CN115065236A (en) * 2022-05-06 2022-09-16 江南大学 High-gain Sepic direct current converter based on three-level boosting unit
CN115864815A (en) * 2022-11-07 2023-03-28 三峡大学 Bridgeless Sepic PFC converter based on switch inductance and capacitance

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