CN114421761B

CN114421761B - Three-level converter with flying capacitor and control method

Info

Publication number: CN114421761B
Application number: CN202210325549.2A
Authority: CN
Inventors: 陈鹏; 林磊明; 何安然; 孙帅; 于振峰
Original assignee: Sungrow Power Supply Co Ltd
Current assignee: Sungrow Power Supply Co Ltd
Priority date: 2022-03-30
Filing date: 2022-03-30
Publication date: 2022-07-12
Anticipated expiration: 2042-03-30
Also published as: CN114421761A

Abstract

The application provides a three-level converter with a flying capacitor and a control method, wherein a first switching tube and a second switching tube adopt switching tubes with different characteristics, and the different characteristics at least comprise switching frequency or device withstand voltage; sending a first driving signal to a first switch tube and sending a second driving signal to a second switch tube; in each preset time period, P pulses exist in the first driving signal, Q pulses exist in the second driving signal, P is an integer larger than or equal to 2, and Q is larger than P; the second driving signal has N pulses in a first pulse period of the first driving signal, the second driving signal has M pulses in a second pulse period of the first driving signal, N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M + N = Q; the inductor is charged and discharged for P + N + M times in each preset time period. Compared with the traditional two switching tubes with higher withstand voltage, the scheme reduces the power loss, reduces the power loss of the converter and improves the electric energy conversion efficiency.

Description

Three-level converter with flying capacitor and control method

Technical Field

The application relates to the technical field of power electronics, in particular to a three-level converter with a flying capacitor and a control method.

Background

Currently, a three-level DCDC converter with flying capacitor is shown in fig. 1, and the converter includes two main power transistors, a first switch transistor Q1 and a second switch transistor Q2, two diodes D1 and D2, a power inductor L and a flying capacitor CF. Typically, the flying capacitor CF has a voltage that is half of the bus voltage Vbus; generally, the capacitance values of the bus capacitors C1 and C2 are equal, and the voltage on C1 is equal to the voltage on C2. T1 and T2 adopt the conducting mode of 180 degrees of staggering, can realize the ripple current frequency multiplication of power inductance L in a duty cycle, thus reduce the inductance ripple. As shown in fig. 2 and fig. 3, Vg1 and Vg2 correspond to the driving signals of T1 and T2, respectively, Ts is the period of the driving signal, the periods of the two main power transistors are the same, and the duty ratios are the same. Fig. 2 is a schematic diagram of a driving signal with a duty ratio smaller than 0.5, and fig. 3 is a schematic diagram of a driving signal with a duty ratio larger than 0.5.

However, in the prior art, the first switching tube and the second switching tube are switching tubes with the same switching characteristics, for example, the switching frequency is the same, the withstand voltage is the same, and the switching tubes with higher withstand voltage are selected, so that the power loss of the two switching tubes is relatively large.

Disclosure of Invention

In order to solve the technical problem, the application provides a three-level converter with a flying capacitor and a control method, which can reduce the power loss of a switching tube and further reduce the power consumption of the whole converter.

In order to achieve the above purpose, the technical solutions provided in the embodiments of the present application are as follows:

the application provides a three level converter with flying capacitor includes: the flying capacitor comprises a first switching tube, a second switching tube, an inductor, a flying capacitor, a first diode, a second diode and a controller; the first switching tube and the second switching tube adopt switching tubes with different characteristics, wherein the different characteristics at least comprise switching frequency or device withstand voltage;

the first end of the inductor is connected with the first input end of the converter, and the second end of the inductor is connected with a first node; the first end of the first switching tube is connected with the first node, the second end of the first switching tube is connected with the second node, the first end of the second switching tube is connected with the second node, and the second end of the second switching tube is connected with the second input end of the converter; the anode and the cathode of the first diode are respectively connected with the first node and the third node, and the anode and the cathode of the second diode are respectively connected with the third node and the first output end of the converter; a first end of the flying capacitor is connected with the second node, and a second end of the flying capacitor is connected with the third node;

the controller is used for sending a first driving signal to the first switching tube and sending a second driving signal to the second switching tube; at each preset time period, P pulses exist in the first driving signal, Q pulses exist in the second driving signal, P is an integer greater than or equal to 2, and Q is greater than P; the second driving signal has N pulses in a first pulse period of the first driving signal, and the second driving signal has M pulses in a second pulse period of the first driving signal, wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M + N = Q; and the inductor is charged and discharged for P + N + M times in each preset time period.

Preferably, the Q pulses of the second driving signal correspond to low-level stages of the P pulses of the first driving signal.

Preferably, the Q pulses of the second driving signal correspond to high-level phases of the P pulses of the first driving signal.

Preferably, the frequencies of the P pulses are different, and the pulse widths of the P pulses are equal.

Preferably, the frequencies of the P pulses are the same, and the pulse widths of the P pulses are not equal.

Preferably, the frequencies of the P pulses are the same, and the pulse widths of the P pulses are equal.

Preferably, the frequencies of the P pulses are different, and the pulse widths of the P pulses are not equal.

Preferably, the pulse widths of the N pulses are not equal, and the pulse widths of the M pulses are equal;

or the like, or, alternatively,

the pulse widths of the N pulses are equal, and the pulse widths of the M pulses are not equal;

or the like, or, alternatively,

the pulse widths of the N pulses are equal, the pulse widths of the M pulses are equal, and the pulse widths of the N pulses are not equal to the pulse widths of the M pulses.

Preferably, the method further comprises the following steps: a third switching tube;

and a first end of the third switching tube is connected with the second node, and a second end of the third switching tube is connected with a first end of the flying capacitor.

Preferably, the method further comprises the following steps: a third diode and a fourth diode;

the anode of the third diode is connected with the middle point of the output voltage of the converter, and the cathode of the third diode is connected with the third node; the anode of the fourth diode is connected with the second node, and the cathode of the fourth diode is connected with the midpoint of the output voltage.

Preferably, the method further comprises the following steps: a fourth switching tube;

and the first end of the fourth switching tube is connected with the first end of the flying capacitor, and the second end of the fourth switching tube is connected with the negative output end of the converter.

Preferably, the three-level converter is a three-level BUCK circuit.

Preferably, the three-level converter is a three-level inverter.

The present application also provides a method of controlling a three-level converter with a flying capacitor, the converter comprising: the flying capacitor comprises a first switching tube, a second switching tube, an inductor, a flying capacitor, a first diode, a second diode and a controller; the first switching tube and the second switching tube adopt switching tubes with different characteristics, wherein the different characteristics at least comprise switching frequency or device withstand voltage;

the method comprises the following steps:

sending a first driving signal to the first switch tube, and sending a second driving signal to the second switch tube; at each preset time period, P pulses exist in the first driving signal, Q pulses exist in the second driving signal, P is an integer larger than or equal to 2, and Q is larger than P; the second driving signal has N pulses in a first pulse period of the first driving signal, and the second driving signal has M pulses in a second pulse period of the first driving signal, wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M + N = Q; and the inductor is charged and discharged for P + N + M times in each preset time period.

According to the technical scheme, the method has the following beneficial effects:

the two main power tubes in the converter provided by the application adopt switching tubes with different characteristics, for example, the switching frequency and the withstand voltage are different, one withstand voltage is high, and the other withstand voltage is low; the first switch tube corresponds to a first driving signal, and the second switch tube corresponds to a second driving signal; in each preset time period, the first driving signal has P pulses, the second driving signal has Q pulses, the second driving signal has N pulses in the first pulse period of the first driving signal, the second driving signal has M pulses in the second pulse period of the first driving signal, and the inductor is charged for P + N + M times in each preset time period.

Because two main power tubes in the converter that this application provided adopt the switch tube of different switching characteristics, one of them chooses for use withstand voltage lower switch tube another to choose for use withstand voltage higher switch tube, compare like this in the tradition two all choose for use withstand voltage higher switch tube, power loss can reduce, and then can reduce the power loss of whole converter to improve the electric energy conversion efficiency of converter.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following descriptions are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a three-level DCDC converter with flying capacitors provided in the prior art;

fig. 2 is a schematic diagram of driving signals of a first switch tube and a second switch tube corresponding to fig. 1 being staggered by 180 degrees;

FIG. 3 is a schematic diagram of driving signals of the first switch tube and the second switch tube of FIG. 1 being staggered by 180 degrees;

FIG. 4 is a schematic diagram of a three-level converter with a flying capacitor according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a driving signal of a three-level converter with a flying capacitor according to an embodiment of the present application;

FIG. 6 is a timing diagram of a three-level converter according to an embodiment of the present application;

FIG. 7 is another timing diagram of a three-level converter according to an embodiment of the present application;

FIG. 8a is a timing diagram of driving signals of a first switch and a second switch according to an embodiment of the present disclosure;

FIG. 8b is a timing diagram of driving pulses after inductor current optimization according to an embodiment of the present disclosure;

FIG. 8c is a timing diagram of driving signals of the first switch and the second switch according to an embodiment of the present application;

FIG. 9 is a timing diagram of another embodiment of a three-level converter;

FIG. 10 is a circuit diagram of a three-level converter with flying capacitors according to an embodiment of the present application;

FIG. 11 is a circuit diagram of a three-level converter with flying capacitors according to an embodiment of the present application;

FIG. 12 is a circuit diagram of a three-level converter with flying capacitors according to an embodiment of the present application;

FIG. 13 is a circuit diagram of a buck converter with a flying capacitor according to an embodiment of the present application;

fig. 14 is a circuit diagram of an inverter with flying capacitors provided in an embodiment of the present application;

fig. 15 is a flowchart of a control method of a three-level converter with a flying capacitor according to an embodiment of the present application.

Detailed Description

In order to help better understand the scheme provided in the embodiment of the present application, before the method provided in the embodiment of the present application is introduced, a scenario of an application of the scheme in the embodiment of the present application is introduced.

The application scenario of the three-level converter with the flying capacitor is not specifically limited in the application scenario, and for example, the three-level converter may be in the photovoltaic power generation field, the energy storage field, or other scenarios requiring electric energy conversion. The three-level converter with the flying capacitor can be a boost direct current (DCDC) converter or a buck DCDC converter.

In addition, the scheme provided by the embodiment of the application is not only suitable for the three-level DCDC converter, but also suitable for a three-level inverter circuit with a flying capacitor.

The three-level converter with flying capacitor provided by the embodiment of the present application will be described with reference to the accompanying drawings.

Converter embodiment

Referring to fig. 4, a schematic diagram of a three-level converter with a flying capacitor according to an embodiment of the present application is shown. For convenience of understanding, the embodiments of the present application will be described by taking a three-level DCDC converter as an example.

Referring to fig. 5, the figure is a schematic diagram of a driving signal of a DCDC converter with a flying capacitor according to an embodiment of the present application.

The embodiment provides a DCDC converter with flying capacitor, includes: a first switch tube Q1, a second switch tube Q2, an inductor L, a first diode D1, a second diode D2, a flying capacitor CF and a controller 100; the first switch tube Q1 and the second switch tube Q2 are main power tubes;

the first switch tube Q1 and the second switch tube Q2 are switch tubes with different characteristics, wherein the different characteristics at least comprise a switching frequency and a device withstand voltage;

the controller 100 is configured to send a driving signal to the gate of the first switching tube Q1 and the gate of the second switching tube Q2 to control the switching states of the first switching tube Q1 and the second switching tube Q2, for example, when the driving signal is at a high level, the switching tubes are turned on; when the driving signal is at low level, the switch tube is turned off.

The first end of the inductor L is connected with the first input end of the converter, and the second end of the inductor L is connected with the first node; a first end of a first switching tube Q1 is connected with a first node, a second end of the first switching tube Q1 is connected with a second node, a first end of a second switching tube Q2 is connected with the second node, and a second end of the second switching tube Q2 is connected with a second input end of the converter; the anode and the cathode of the first diode D1 are respectively connected with the first node and the third node, and the anode and the cathode of the second diode D2 are respectively connected with the third node and the first output end of the converter; the first end of the flying capacitor CF is connected to the second node, and the second end of the flying capacitor CF is connected to the third node.

The controller 100 is used for sending a first driving signal Vg1 to the first switching tube Q1 and sending a second driving signal Vg2 to the second switching tube Q2;

at each preset time period, the preset time period is denoted by T in fig. 5, and it should be understood that T is neither a period of the drive signal of T1 nor a period corresponding to the drive signal of T2. Vg1 represents a drive signal of Q1, and Vg2 represents a drive signal of Q2. At each preset time period, P pulses exist in the first drive signal Vg1, Q pulses exist in the second drive signal Vg2, P is an integer greater than or equal to 2, and Q is greater than P; n pulses exist in the second drive signal Vg2 in the first pulse period T1 of the first drive signal Vg1, M pulses exist in the second drive signal Vg2 in the second pulse period T2 of the first drive signal Vg1, N is an integer equal to or greater than 2, M is an integer equal to or greater than 1, and M + N = Q; the inductor is charged and discharged for P + N + M times in each preset time period.

As shown in fig. 5, taking P =2 and Q =3 as an example, where N =2 and M =1, the number of charging and discharging times of the inductor current is P + N + M =2+2+1=5 times in a preset time period T, so that the charging and discharging cycles of the inductor are increased, the ripple is reduced, and the size of the inductor is favorably reduced.

The three level converter with flying capacitor that this application embodiment provided, because in every preset time quantum, the cycle of the drive signal of first switch tube and second switch tube all increases, consequently, in every preset time quantum, the charge-discharge number of times of inductance increases to can effectively reduce the ripple current of inductance, because ripple current reduces, consequently, the inductance can take less inductance value, thereby effectively reduce the volume of inductance, further reduce the volume of whole three level converter.

The two main power tubes in the converter provided by the application adopt switching tubes with different characteristics, such as different switching frequencies and different voltage withstanding, wherein one voltage withstanding tube is high, and the other voltage withstanding tube is low; the first switch tube corresponds to a first driving signal, and the second switch tube corresponds to a second driving signal; in each preset time period, the first driving signal has P pulses, the second driving signal has Q pulses, the second driving signal has N pulses in the first pulse period of the first driving signal, the second driving signal has M pulses in the second pulse period of the first driving signal, and the inductor is charged for P + N + M times in each preset time period.

According to the technical scheme provided by the embodiment of the application, the switching frequencies of the two switching tubes are different, one switching frequency is higher, the other switching frequency is lower, specifically, the switching frequency of the first switching tube can be larger than that of the second switching tube, and the switching frequency of the first switching tube can also be smaller than that of the second switching tube. For the sake of comprehension and ease of description, the following embodiments are described by taking the example that the switching frequency of the first switching tube is low, and the switching frequency of the second switching tube is high. In an actual product, one of the switching tubes can be selected to have a higher switching frequency, and the other switching tube can be selected to have a lower switching frequency, that is, two switching tubes with different switching characteristics can be selected. Once the switch tube is selected, the driving signals cannot be converted back and forth in work, namely the first switch tube always corresponds to the first driving signal, and the second switch tube always corresponds to the second driving signal.

Several specific implementations of P pulses and Q pulses are described below with reference to the drawings.

If each preset time period is taken as one period T, P pulses exist for Vg1, and the frequency and pulse width of the P pulses are not limited in this embodiment, that is, the frequency of the P pulses may be equal or unequal, and the pulse widths of the P pulses may be equal or unequal.

For example, the following are included: the frequencies of the P pulses are different, and the pulse widths of the P pulses are equal. The frequency of the P pulses is the same, and the pulse widths of the P pulses are not equal. The frequencies of the P pulses are different, and the pulse widths of the P pulses are equal. The frequencies of the P pulses are different, and the pulse widths of the P pulses are not equal.

Referring to fig. 6, a timing diagram of a three-level converter according to an embodiment of the present application is shown.

In the timing chart shown in fig. 6, for Vg1, the frequency of P pulses is different and the pulse width is also different in one period T.

The pulse width and frequency of the N pulses of Vg2 shown in fig. 6 are not specifically limited in the present embodiment, nor are the pulse widths and frequencies of the M pulses specifically limited in the present embodiment,

the pulse widths of the N pulses are not equal, and the pulse widths of the M pulses are equal;

or the like, or a combination thereof,

the pulse widths of the N pulses are equal, and the pulse widths of the M pulses are not equal.

Or the like, or, alternatively,

One situation shown in fig. 6 is that the pulse widths of the N pulses of Vg2 are equal and the frequency is the same. The pulse width and frequency between the N pulses and the M pulses are not limited in the embodiments of the present application, for example, the pulse widths of the M pulses and the N pulses are the same.

Referring to fig. 7, another timing diagram of a three-level converter provided in the embodiment of the present application is shown.

Vg2 has N pulses (N is 2 or more) in the first pulse period T1 of Vg1, and Vg2 has M pulses (M is 1 or more) in the second pulse period T2 of Vg 1. The frequency and pulse width of the N pulses present in the first pulse period T1 and the M pulses present in the second pulse period T2 are not limited.

In fig. 7, the pulse widths of the N pulses are different, and the frequencies of the N pulses are also different. The frequency of the M pulses is the same, and the pulse width is the same.

It can be seen from fig. 5-7 that Q pulses of the second driving signal correspond to the low level stage of P pulses of the first driving signal, that is, Q pulses of the second driving signal exist only in the low level stage of P pulses of the first driving signal, and no pulse of the second driving signal exists in the high level stage of P pulses of the first driving signal.

The following describes a case where the three-level converter is a DCDC converter, and is a boost converter, there may be two cases of the boost ratio, one is smaller than 2, and the other is larger than 2, which are described below separately.

In each period of the first driving signal, when the N pulses of the second driving signal correspond to the low level stage of the first driving signal, or when the N pulses of the first driving signal correspond to the low level stage of the second driving signal, the voltage boost ratio of the three-level converter is less than 2.

In each period of the first driving signal, when the N pulses of the second driving signal correspond to the high level stage of the first driving signal, or when the N pulses of the first driving signal correspond to the high level stage of the second driving signal, the voltage boost ratio of the three-level converter is greater than 2.

The following describes a case where the three-level converter is a DCDC converter, and is a boost converter, where the boost ratio is less than 2, that is, the ratio of the output voltage to the input voltage is less than 2.

Referring to fig. 8a, the figure is a timing diagram of driving signals of the first switch tube and the second switch tube according to an embodiment of the present application.

In fig. 8a, PWM1 is the driving signal of the first switch tube, and PWM2 is the driving signal of the second switch tube.

As can be seen from fig. 8a, the boosting ratio of the three-level converter is less than 2 when N pulses of the second driving signal PWM2 correspond to the low-level phase of the first driving signal PWM1 in each period of the first driving signal PWM 1.

As can be seen from fig. 8a, in one period of the first driving signal PWM1, for example, the period is Ts, in Ts, there is one pulse in PWM1 and N pulses in PWM2, and in order to minimize the current ripple of the inductor, the N pulses of PWM2 are controlled to be in the low level stage of PWM1, so that the inductor voltage is ensured to be a vector combination of two voltages, and the ripple current of the inductor can be minimized. Since the inductor voltage is composed of two voltage vectors, the resultant voltage vector is optimal. If the inductor voltage is synthesized from more voltage vectors, the synthesized voltage is not optimal. For example, the ripple of the voltage vector-synthesized by three voltages is large compared to the voltage vector-synthesized by two voltages.

Various operating conditions of the three-level boost converter are analyzed in conjunction with fig. 8 a. Fig. 8a is a timing diagram of driving pulses when the inductor current is not optimized.

In FIG. 8a, Carrier 1 is the triangular wave for PWM1 generation and Carrier 2 is the triangular wave for PWM2 generation. Where T1 is the triangular wave period of carrier 1 and T2 is the triangular wave period of PWM 2. t1 is the high duration of one pulse of PWM1, and t2 is the high duration of one pulse of PWM 2. As can be seen from fig. 8a, N pulses of PWM2 exist in the low period of PWM 1. Take T1=1/2Ts as an example. the duty cycle for t1 is d1 and the duty cycle for t2 is d 2.

According to volt-second balance requirements of the flying capacitors, under the steady state condition:

1) when T1 is more than N.T2, the duty ratio of T1 is less than 1; the constraint conditions are as follows: d1max = n.t 2/T1;

2) when T1 is less than N.T2, the duty ratio of T2 is less than 1; the constraint conditions are as follows: d2max = T1/(n.t 2);

3) when T1= N.T2, the value ranges of the two groups of duty ratios are 0-1, and d1= d2 under a steady state condition, so that engineering realization and simplification are facilitated;

4) when d1= d2=1, the two switching tubes in the three-level converter act at the same frequency, and the duty ratio is equivalent to 0.5 in the conventional manner, that is, the maximum step-up ratio of the step-up circuit is 2.

It was described above that in order to reduce the ripple of the inductor current, the two voltage vectors are made to be the optimum case of synthesizing the inductor voltage, i.e., N pulses of PWM2 appear in the low level period of PWM 1. Describing another implementation where N pulses of PWM2 occur during the high period of PWM1, an optimal combination of voltages, i.e., two voltage vectors, can also be achieved.

The following analysis is done in conjunction with the inductor current optimized pulse timing.

Referring to fig. 8b, it is a timing diagram of the driving pulse after inductor current optimization provided in the embodiment of the present application.

As shown in fig. 8b, within Ts, 3 00 voltage vectors, one 10 voltage vector and 2 01 voltage vectors are included. According to the relation of the voltage vectors, in order to realize the synthesis of the optimal voltage, the action time of 3 00 voltage vectors is controlled to be equal; the ripple increment of the control 10 voltage vectors is equal to the ripple increment of the 2 01 voltage vectors.

The voltage of the flying capacitor specifically needs to be controlled by combining the flying capacitor and the duty ratio, that is, in engineering application, the voltage Vcf of the flying capacitor is related to the duty ratio d.

Vcf=f(d，N)×Vout。

From the above equations, it can be seen that Vcf and N, d are both related to the output voltage Vout of the converter.

Referring to fig. 8c, the graph is a timing diagram of driving signals of the first switch tube and the second switch tube according to the embodiment of the present application.

In each period of the first driving signal PWM1, when N pulses of the second driving signal PWM2 correspond to a high stage of the first driving signal PWM1, the boosting ratio of the three-level converter is greater than 2.

In the embodiment of the application, the N pulses of the second driving signal exist in the high level stage of the first driving signal, so that the inductive voltage can be ensured to be synthesized by two voltage vectors, the synthesized voltage quality is ensured to be higher, and the ripple on the inductive voltage is minimized. Similarly, the N pulses of the second driving signal exist in the low level stage of the first driving signal, so that the inductive voltage is ensured to be synthesized by two voltage vectors, and the synthesized voltage quality is ensured to be higher, thereby minimizing the ripple on the inductive voltage.

According to the volt-second balance requirement of the flying capacitor, under the steady state condition:

1) when T1 is more than N.T2, the duty ratio of d1 is always more than 0; the constraint conditions are as follows: d1min = 1-n.t 2/T1;

2) when T1 is less than N.T2, the duty ratio of d2 is greater than 0; the constraint conditions are as follows: d2min = 1-T1/(n.t 2);

4) when d1= d2=0, the two driving tubes in the three-level circuit act at the same frequency, and the duty ratio is equivalent to 0.5 of the conventional duty ratio, that is, the minimum Boost ratio of the Boost circuit is 2.

In the three-level converter provided by the embodiment of the application, the first switching tube may adopt a low-frequency switching device, the second switching tube may adopt a high-frequency switching device, and the two switching devices may select switching devices with different characteristics, for example, one switching device has a higher switching frequency and the other switching device has a lower switching frequency. In addition, the different characteristics may include different withstand voltages, that is, one switching tube has a high withstand voltage and the other switching tube has a low withstand voltage, in addition to different switching frequencies.

The duty ratio of the first switching tube and the duty ratio of the second switching tube are not specifically limited in the embodiments of the present application, and may be, for example, greater than 0.5, or less than 0.5.

The case where the duty ratio of the first drive signal Vg1 is greater than 0.5 will be described.

Referring to fig. 9, a timing diagram of a three-level converter according to an embodiment of the present application is shown.

As can be seen in fig. 9, the duty cycle of Vg1 is greater than 0.5 during one period T.

It should be understood that since there are multiple pulse periods of Vg1 in one period T, the duty cycle of Vg1 refers to the overall duty cycle in one period T, i.e., the ratio of the sum of the pulse widths of multiple pulses to T in T is greater than 0.5.

During specific work, the controller is used for controlling the switching states of the first switching tube and the second switching tube according to the conditions of input voltage, output voltage, inductive current, flying capacitor voltage and the like of the three-level converter, namely controlling the conduction or the disconnection of the first switching tube and the second switching tube, so that the charging current of the inductive current in each period T is equal to the discharging current; further, the charging current in each charging and discharging period of the inductor current may be equal to the discharging current.

The three-level converter provided by the embodiment of the application can also have other topological forms, and is described in detail in the following with reference to the attached drawings.

Referring to fig. 10, a circuit diagram of a three-level converter with a flying capacitor according to an embodiment of the present application is shown.

The difference between the three-level converter provided in this embodiment and fig. 4 is that the converter further includes: a third switching tube Q3;

a first terminal of the third switching tube Q3 is connected to the second node, and a second terminal of the third switching tube Q3 is connected to a first terminal of the flying capacitor CF.

The third switch tube Q3 is used to prevent the second switch tube Q2 and the second diode D2 from being over-voltage, and when the three-level converter is started, the third switch tube Q3 is turned off to prevent the input voltage Vin from forming a loop through the inductor L, D1, CF, Q3 and the second switch tube Q2, and to prevent the second switch tube Q2 from being over-voltage. When the three-level converter Vin is not powered and the output end of the three-level converter, namely BUS, is powered, current is prevented from flowing from the output end of the three-level converter to the input end, therefore, the third switching tube Q3 is disconnected, and D2, CF, Q1 and L are prevented from forming a path. Otherwise, the third switching tube Q3 is closed.

Referring to fig. 11, a circuit diagram of a three-level converter with a flying capacitor according to an embodiment of the present application is shown.

Further comprising: a fourth switching tube Q4;

the first end of the fourth switch tube Q4 is connected to the first end of the flying capacitor CF, and the second end of the fourth switch tube Q4 is connected to the negative output terminal of the converter, namely BUS-.

When the three-level converter is started, the fourth switching tube Q4 is closed, the CF can be charged, and when the voltage on the flying capacitor CF is charged to a preset voltage value, the Q4 is opened.

It will be appreciated that to reduce the impact of the charging current on the flying capacitor CF, the converter may further comprise a current limiting resistor in series with the fourth switch transistor Q4.

Referring to fig. 12, there is shown a circuit diagram of a three-level converter with flying capacitors according to an embodiment of the present application.

The three-level converter provided by the embodiment further comprises: a third diode D3 and a fourth diode D4;

the anode of the third diode D3 is connected to the middle point of the output voltage of the converter, and the cathode of the third diode D3 is connected to the third node; the anode of the fourth diode D4 is connected to the second node, and the cathode of the fourth diode D4 is connected to the midpoint of the output voltage.

The converter further includes, on the basis of the topology shown in fig. 1: a third diode D3 and a fourth diode D4.

An anode of the third diode D3 is connected to a midpoint of the output voltage of the three-level converter, that is, an anode of the third diode D3 is connected to a first end of the first capacitor C1, a first end of the first capacitor C1 is connected to a first end of the second capacitor C2, a second end of the first capacitor C1 is connected to the first output terminal, and a second end of the second capacitor C2 is connected to the second output terminal.

The cathode of the third diode D3 is connected to the third node C. The function of the D3 is to clamp the voltage drop experienced by the D4, and prevent the D4 from experiencing the entire dc bus voltage when the second switching transistor Q2 is turned on.

An anode of the fourth diode D4 is connected to the second node B, and a cathode of the fourth diode D4 is connected to the midpoint of the output voltage, i.e., a cathode of the fourth diode D4 is connected to the first terminal of the first capacitor C1.

The controller can also increase the charging and discharging frequency of the inductor L by applying asymmetric driving signals to the first switching tube Q1 and the second switching tube Q2, so as to reduce the ripple current of the inductor L.

In order to reduce the voltage stress on the second switching tube Q2 when the power supply is started, i.e. when the power supply is switched on, the circuit shown in fig. 12 has the following advantages with respect to the circuit shown in fig. 1:

in fig. 12, D3 and D4 are added to connect CF and C1 in parallel when the power is turned on, Vin is CF charged, and there is no time when the voltage of CF is 0, so Vin is not completely applied to the second switching tube Q2, thereby reducing the voltage stress applied to the second switching tube Q2 and protecting the second switching tube Q2.

The three-level converter described above takes a Boost circuit as an example, and the case where the three-level converter is a BUCK circuit is described below with reference to the drawings.

Referring to fig. 13, a circuit diagram of a buck converter with a flying capacitor according to an embodiment of the present application is shown.

In the converter provided by the embodiment, the three-level converter is a three-level BUCK circuit.

A first end of the first switch tube Q1 is connected to the positive input terminal of the converter, a second end of the first switch tube Q1 is connected to a first end of the second switch tube Q2, a second end of the second switch tube Q2 is connected to the cathode of the first diode, an anode of the first diode D1 is connected to the cathode of the second diode D2, and an anode of the second diode D2 is connected to the negative input terminal of the converter.

A first end of the flying capacitor CF is connected with a second end of the first switch tube Q1, and a second end of the flying capacitor CF is connected with an anode of a first diode D1;

a first terminal of the inductor L is connected to the cathode of the first diode D1 and a second terminal of the inductor L is connected to the output of the converter.

Since the converter shown in fig. 13 is a buck converter, the output voltage Vo is smaller than the input voltage Vin.

Referring to fig. 14, a circuit diagram of an inverter with a flying capacitor according to an embodiment of the present application is shown.

The converter provided by the embodiment can also be an inverter, namely a three-level inverter.

A three-level inverter with flying capacitors comprising: the flying capacitor comprises a first switching tube Q1, a second switching tube Q2, a third switching tube Q3, a fourth switching tube Q4, a flying capacitor CF and an inductor L.

The positive input end of the first end converter of the first switching tube Q1, the second end of the first switching tube Q1 is connected with the first end of the second switching tube Q2, the second end of the second switching tube Q2 is connected with the first end of the third switching tube Q3, the second end of the third switching tube Q3 is connected with the first end of the fourth switching tube Q4, and the second end of the fourth switching tube Q4 is connected with the negative input end of the converter.

The first terminal of the flying capacitor CF is connected to the first terminal of the second switching transistor Q2, and the second terminal of the flying capacitor CF is connected to the second terminal of the third switching transistor Q3.

The first end of the inductor L is connected to the second end of the second switching tube Q2, and the second end of the inductor L is connected to the output end of the converter.

Since the inverter functions to convert an input dc power into an ac power, the input voltage Vin is a dc voltage, and the output voltage Vo is an ac voltage.

Method embodiment

Based on the three-level converter with the flying capacitor provided by the above embodiments, the embodiments of the present application further provide a control method of the three-level converter with the flying capacitor, which is described in detail below with reference to the accompanying drawings.

Referring to fig. 15, there is provided a flow chart of a control method of a three-level converter with a flying capacitor according to the present application.

The present embodiment provides a method for controlling a three-level converter with a flying capacitor, where the converter includes: the flying capacitor comprises a first switching tube, a second switching tube, an inductor, a flying capacitor, a first diode, a second diode and a controller; the first switching tube and the second switching tube adopt switching tubes with different characteristics, wherein the different characteristics at least comprise switching frequency or device withstand voltage;

the method comprises the following steps:

s1501: sending a first driving signal to a first switching tube, wherein the first driving signal has P pulses in each preset time period;

s1502: sending a second driving signal to a second switching tube; at each preset time period, Q pulses exist in the second driving signal;

p is an integer greater than or equal to 2, and Q is greater than P; the second driving signal has N pulses in a first pulse period of the first driving signal, the second driving signal has M pulses in a second pulse period of the first driving signal, N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M + N = Q; the inductor is charged and discharged for P + N + M times in each preset time period.

The two main power tubes of the converter applied by the method provided by the application adopt switching tubes with different characteristics, for example, the switching frequency and the withstand voltage are different, one withstand voltage is high, and the other withstand voltage is low; the first switch tube corresponds to a first driving signal, and the second switch tube corresponds to a second driving signal; in each preset time period, the first driving signal has P pulses, the second driving signal has Q pulses, the second driving signal has N pulses in the first pulse period of the first driving signal, the second driving signal has M pulses in the second pulse period of the first driving signal, and the inductor is charged for P + N + M times in each preset time period.

Compared with the traditional method that two switch tubes with higher voltage resistance are adopted, the power loss can be reduced, the power loss of the whole converter can be reduced, and the electric energy conversion efficiency of the converter is improved.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing description of the disclosed embodiments will enable those skilled in the art to make or use the invention in various modifications to these embodiments, which will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A three-level converter with flying capacitors, comprising: the flying capacitor comprises a first switching tube, a second switching tube, an inductor, a flying capacitor, a first diode, a second diode and a controller; the first switching tube and the second switching tube adopt switching tubes with different characteristics, wherein the different characteristics at least comprise switching frequency or device withstand voltage;

the first end of the inductor is connected with the first input end of the converter, and the second end of the inductor is connected with a first node; the first end of the first switch tube is connected with the first node, the second end of the first switch tube is connected with the second node, the first end of the second switch tube is connected with the second node, and the second end of the second switch tube is connected with the second input end of the converter; the anode of the first diode is connected with the first node, the cathode of the first diode is connected with the third node, and the anode and the cathode of the second diode are respectively connected with the third node and the first output end of the converter; a first end of the flying capacitor is connected with the second node, and a second end of the flying capacitor is connected with the third node;

the controller is used for sending a first driving signal to the first switching tube and sending a second driving signal to the second switching tube; at each preset time period, P pulses exist in the first driving signal, Q pulses exist in the second driving signal, P is an integer larger than or equal to 2, and Q is larger than P; the second driving signal has N pulses in a first pulse period of the first driving signal, and the second driving signal has M pulses in a second pulse period of the first driving signal, wherein N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M + N = Q; and the inductor is charged and discharged for P + N + M times in each preset time period.

2. The converter according to claim 1, wherein Q pulses of the second drive signal correspond to low-level phases of P pulses of the first drive signal.

3. The converter of claim 1, wherein Q pulses of the second drive signal correspond to high phases of P pulses of the first drive signal.

4. The converter according to claim 1, wherein the frequencies of the P pulses are different, and the pulse widths of the P pulses are equal.

5. A converter according to any of claims 1-3, characterized in that the frequency of said P pulses is the same and the pulse widths of said P pulses are not equal.

6. A converter according to any of claims 1-3, characterized in that the frequency of said P pulses is the same and the pulse width of said P pulses is equal.

7. A converter according to any of claims 1-3, characterized in that the frequency of said P pulses is different, and the pulse widths of said P pulses are not equal.

8. A converter according to any of claims 1-3, wherein the pulse widths of said N pulses are not equal, and the pulse widths of said M pulses are equal;

or the like, or, alternatively,

9. The transducer of any one of claims 1-4, further comprising: a third switching tube;

10. The transducer of any one of claims 1-4, further comprising: a third diode and a fourth diode;

11. The transducer of any one of claims 1-4, further comprising: a fourth switching tube;

12. The converter of claim 1, wherein the three-level converter is a three-level BUCK circuit.

13. The converter of claim 1, wherein the three-level converter is a three-level inverter.

14. A method of controlling a three-level converter with flying capacitors, said converter comprising: the flying capacitor comprises a first switching tube, a second switching tube, an inductor, a flying capacitor, a first diode, a second diode and a controller; the first switching tube and the second switching tube adopt switching tubes with different characteristics, wherein the different characteristics at least comprise switching frequency or device withstand voltage;

the method comprises the following steps: