CN116598352A - Groove type MOSFET device and preparation method thereof - Google Patents

Groove type MOSFET device and preparation method thereof Download PDF

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Publication number
CN116598352A
CN116598352A CN202310363367.9A CN202310363367A CN116598352A CN 116598352 A CN116598352 A CN 116598352A CN 202310363367 A CN202310363367 A CN 202310363367A CN 116598352 A CN116598352 A CN 116598352A
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China
Prior art keywords
layer
trench
mosfet device
masking layer
source
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Pending
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CN202310363367.9A
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Chinese (zh)
Inventor
袁俊
郭飞
王宽
徐东
彭若诗
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Hubei Jiufengshan Laboratory
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Hubei Jiufengshan Laboratory
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Priority to CN202310363367.9A priority Critical patent/CN116598352A/en
Publication of CN116598352A publication Critical patent/CN116598352A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors

Abstract

The invention relates to the field of wide bandgap semiconductor devices, in particular to a trench MOSFET device and a preparation method thereof. The trench MOSFET device at least comprises a substrate, an epitaxial layer, a gate trench, a source trench and a drain electrode, wherein the epitaxial layer, the gate trench, the source trench and the drain electrode are arranged on the substrate, a p+ masking layer is arranged right below the gate trench and is positioned inside the epitaxial layer, a p+ connecting layer is further arranged inside the epitaxial layer, the p+ masking layer is grounded through the p+ connecting layer and the source electrode, and the p+ masking layer and the p+ connecting layer do not influence current circulation. According to the invention, the p+ masking layer is constructed below the grid electrode groove, and the grounding mode of the p+ masking layer is improved, so that the electric field at the groove angle can be effectively reduced, and when surge voltage occurs in the p+ masking layer, the depletion region can be expanded to two sides, the on-resistance is increased, and the surge current is inhibited.

Description

Groove type MOSFET device and preparation method thereof
Technical Field
The invention relates to the field of wide bandgap semiconductor devices, in particular to a trench MOSFET device and a preparation method thereof.
Background
Trench metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFETs) of wide bandgap semiconductor materials (silicon carbide/gallium nitride/gallium oxide/diamond/aluminum nitride, etc.) tend to suffer from several problems in practical fabrication and application: (1) The high electric field of the material drift region causes the electric field on the gate dielectric to be very high, and the problem is aggravated at the groove angle, so that the gate dielectric layer is rapidly broken down under high drain voltage, and the electrostatic effect and the voltage spike tolerance capability to severe environment are poor; (2) Because the wide bandgap semiconductor MOSFET is mainly applied to the field of high voltage, high frequency and large current, parasitic parameters in the circuit can cause peak burrs in the high frequency switching process, so that instantaneous overvoltage on the current path of the device is caused, meanwhile, the loss of the switch is increased, or large surge voltage is formed due to the change of a public power load and the like, and therefore the surge voltage resistance and overvoltage protection of the MOSFET are also very important. The existing MOSFET device does not have surge voltage self-inhibition capability and overvoltage protection capability, a complex buffer circuit, a surge voltage inhibition circuit and an overvoltage protection circuit are often required to be designed in practical application, the external matched inhibition and overvoltage protection circuit often has time delay, high-frequency peak voltage surge in the practical switching process is still born by the device, breakdown failure of a channel region of the device is sometimes caused, and gradual failure of a gate structure and an electrode ohmic contact region is sometimes caused, so that the reliability problem of the device is caused; (3) The limited ion implantation depth results in many targeted trench gate protection structures and anti-surge designs that are difficult to implement technically.
Therefore, it is of great importance to provide a MOSFET device with self-suppression capability against surge voltage, which has a gate dielectric at the trench corners that is not easily broken down.
Disclosure of Invention
Aiming at the technical problems existing in the prior art, the invention provides a novel trench MOSFET device, which is characterized in that a p+ masking layer is constructed under a gate trench, and the grounding mode of the device is improved, so that the electric field at the trench angle can be effectively reduced, and when surge voltage occurs, a depletion region can be expanded to two sides, the on-resistance is increased, and the surge current is inhibited.
The invention adopts the following technical scheme to realize the technical purposes:
the utility model provides a trench MOSFET device, includes the substrate and sets up epitaxial layer on the substrate at least, grid slot, source electrode slot and drain electrode, be provided with p+ masking layer just under the grid slot the p+ masking layer is located epitaxial layer is inside, epitaxial layer's inside still is provided with p+ tie layer, p+ masking layer passes through p+ tie layer and source ground, just p+ masking layer with p+ tie layer does not influence the circulation of electric current.
As a preferred embodiment, the p+ masking layer and the p+ connection layer are located at the same depth of the epitaxial layer, the p+ connection layer being in contact with the source p+ region of the source trench.
As a preferred embodiment, the shape of the p+ masking layer includes, but is not limited to, rectangular, diamond, circular, oval, and wave-shaped.
As a preferred embodiment, the p+ masking layers are connected by p+ connection layers, including but not limited to horizontal connection, oblique connection, cross connection, and m-shaped connection; and/or the source electrode grooves are alternately arranged or symmetrically arranged or are arranged at intervals by a plurality of p+ masking layers; and/or the grid electrode groove is in a whole section of long strip shape or a discontinuous long strip shape.
As a preferred embodiment, when the gate trench is in a discontinuous strip shape, the p+ mask layer is connected to the source electrode through the p+ ground layer at both sides of the gate trench.
As a preferred embodiment, the distance from the upper edge of the p+ masking layer to the bottom of the gate trench is d, where d > 0 or d=0 or d < 0; and/or the width of the gate trench is W1, and the p+ masking layer is W2, wherein W1 < W2 or w1=w2 or W1 > W2.
When d=0 and W1 is larger than or equal to W2, the p+ masking layer is in an ion implantation mode through a groove self-alignment process.
When d is more than 0, a p+ protection layer is arranged at the bottom of the grid electrode groove and is connected with the source electrode groove through a p+ grounding column.
As a preferred embodiment, d > 0 and the concentration of the N-epitaxial layer above the p+ masking layer is greater than the concentration of the N-epitaxial layer below the p+ masking layer.
The invention also provides a preparation method of the trench MOSFET device, which comprises the following steps:
growing a first N-epitaxial layer on a wide band gap semiconductor material substrate, and then preparing a p+ masking layer and a p+ connecting layer on the first N-epitaxial layer;
after the second N-epitaxial layer grows again, preparing a p-well region and a source N+ region;
etching to form a grid groove and a source groove, and forming a source p+ region;
gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, and source electrode deposition.
The invention also discloses the MOSFET device and the MOSFET device prepared by the method.
According to the invention, the p+ masking layer is constructed below the grid electrode groove, and the grounding mode of the p+ masking layer is improved, so that not only can the electric field at the groove angle be effectively reduced, but also the depletion region can be expanded to two sides when surge voltage occurs in the p+ masking layer, the on-resistance is increased, and the surge current is inhibited; and the P+ connection layer with optimized layout can enable the P+ masking layer to be better grounded, so that the Miller capacitance is reduced, the switching speed is improved, and the switching loss is reduced.
Drawings
Fig. 1 is a schematic perspective view of a MOSFET device with a cross section according to the present invention;
fig. 2 is a schematic structural diagram of another MOSFET device according to the present invention, in which fig. a is a schematic structural diagram of a cross-section, and fig. b is a schematic sectional view of a portion along a trench direction;
fig. 3 is a schematic diagram of the surge voltage resisting principle of the MOSFET device provided by the invention;
fig. 4 is a schematic diagram of various structures of a MOSFET device according to an embodiment of the present invention, where a is a schematic diagram of W1 < W2; b is a schematic structural diagram of w1=w2; c is a structural schematic diagram of W1 > W2;
fig. 5 is a schematic diagram of various structures of a MOSFET device according to an embodiment of the present invention, where a is a schematic diagram of d > 0; b is a schematic structural diagram with d=0; c is a structural schematic diagram with d less than 0;
FIG. 6 is a schematic diagram of another structure of a MOSFET device according to an embodiment of the present invention, wherein d > 0;
fig. 7 is a schematic structural diagram of a p+ mask layer in a MOSFET device according to an embodiment of the present invention, where a is rectangular, b is diamond-shaped, c is circular, d is oval, and e is a waveform;
fig. 8 is a schematic diagram of a source trench arrangement manner in a MOSFET device according to an embodiment of the present invention, where a is an alternating arrangement, b is a symmetrical arrangement, and c is an arrangement of a plurality of p+ masking layers spaced apart;
fig. 9 is a connection manner of a p+ connection layer in a MOSFET device according to an embodiment of the present invention, where a is a horizontal connection, b is an oblique connection, c is a cross connection, and d is a m-shaped connection;
fig. 10 is a schematic flow chart of preparing a MOSFET device according to an embodiment of the present invention, where a to h are corresponding steps S1 to S8, respectively.
In the figure: 1 substrate, 2 epitaxial layer, 3 grid electrode slot, 4 source electrode slot, 5 drain electrode, 6p+ ground layer, 7p+ masking layer, 8p+ connecting layer, 9 source electrode p+ region, 10p+ protective layer, 11P well region, 12 source electrode N+ region, and 13P+ ground column.
Detailed Description
The present invention will be described in further detail with reference to specific examples so as to more clearly understand the present invention by those skilled in the art.
Aiming at the problem that the high electric field of the existing wide band gap semiconductor material drift region causes the electric field on the gate dielectric layer to be very high, the problem is aggravated at the groove angle, so that the gate dielectric layer is broken down rapidly under high drain voltage, and the electric field at the groove angle can be effectively reduced by constructing a p+ masking layer below the groove and improving the grounding mode of the p+ masking layer; in addition, the existing MOSFET device does not have surge voltage self-inhibition capability and overvoltage protection capability, when surge voltage occurs in the p+ masking layer below the grid electrode groove, a depletion region can be expanded to two sides, on-resistance is increased, surge current is inhibited, and a specific principle can be seen in fig. 3.
Referring to fig. 1, the trench MOSFET device provided by the invention at least includes a substrate 1 and an epitaxial layer 2 disposed on the substrate 1, a gate trench 3, a source trench 4 and a drain electrode 5, a p+ masking layer 7 is disposed under the gate trench 3 and located inside the epitaxial layer 2, a p+ connection layer 8,p + masking layer 7 is further disposed inside the epitaxial layer 2, and is grounded through the p+ connection layer 8 and the source, and the arrangement of the p+ masking layer 7 and the p+ connection layer 8 does not affect the current flowing.
The upper part of the epitaxial layer 2 is sequentially provided with a p-well region 11 and a source N+ region 12, and the substrate 1 is an N+ substrate; the epitaxial layer 2 is an N-epitaxial layer; a gate dielectric layer is arranged on the inner wall of the gate groove, and gate polysilicon is arranged in the gate groove; the periphery of the source electrode groove is a source electrode p+ region 9; the drain electrode is located on the side of the substrate 1 remote from the epitaxial layer 2.
The arrangement of the p+ masking layer 7 not only can reduce the electric field at the groove angle, but also can expand the depletion region to two sides when surge voltage occurs, increase on-resistance and inhibit surge current.
The p+ connection layer 8 is disposed to connect the p+ masking layer and the source electrode, so that the p+ connection layer 8 and the p+ masking layer 7 may be disposed at the same depth in the epitaxial layer 2 or at different depths, in practice, for convenience in preparation and better connection, the p+ connection layer 8 and the p+ region 9 of the source trench 4 are disposed at the same depth in the epitaxial layer 2.
The gate trench 3 in the invention can be a whole section of long strip shape or a discontinuous long strip shape, when the trench is a discontinuous long strip shape, the structure is shown in fig. 2, at this time, the p+ masking layer can be formed by ion implantation through a trench self-alignment process, the p+ masking layer 7 can be directly connected with a source electrode (p-well region 11) through the p+ grounding layers 6 at two ends of the gate trench 3, and can also be connected with the source electrode through the p+ grounding layers 6 and the p+ connecting layer 8 (wherein the p+ grounding layers 6 are connected with the p-well region 11, and the p+ connecting layer 8 is connected with the source electrode trench) so as to realize grounding. Preferably, the voltage is simultaneously grounded through the p+ connection layer 6 and the p+ connection layer 8, and the surge voltage self-inhibition capability and the overvoltage protection capability are better.
In addition, if the distance d between the upper edge of the p+ masking layer 7 and the bottom of the trench is d, the width of the trench is W1, and the width of the p+ masking layer is W2, then any of the following relationships between W1 and W2 may be selected: w1 < W2, w1=w2, W1 > W2, wherein when W1 < W2, the structure is shown in fig. 4a, when w1=w2, the structure is shown in fig. 4b, and when W1 > W2, the structure is shown in fig. 4 c;
and the distance d between the upper edge of the p+ masking layer 7 and the bottom of the trench can be any one of the following: d > 0, d=0, d is less than 0, wherein
When d > 0, the concentration of the N-epi layer above the p+ masking layer (i.e., the second N-epi layer described below) may be increased appropriately as a current spreading layer to reduce the on-resistance of the device, the structure of which is shown in fig. 5 a;
when d=0, and W1 is equal to or greater than W2, the p+ masking layer can be formed by ion implantation through a trench self-alignment process, control is accurate, and secondary epitaxy can be avoided, and the structure is shown in fig. 5 b;
when d is less than 0, the p+ masking layer can wrap the corners of the groove, so as to protect the groove corners, and the structure is shown in fig. 5 c.
In this embodiment, when d > 0, a p+ protection layer 10 may be added at the bottom of the gate trench, and then connected to the underlying p+ masking layer 7 through a p+ grounding post 13, so as to achieve grounding, and the specific structure can be seen in fig. 6.
In this embodiment, the shape of the p+ masking layer 7 includes, but is not limited to, rectangular, diamond, circular, oval, and wave-shaped, and see fig. 7.
In addition, the p+ connection layer 8 and the p+ mask layer 7 may be connected in various manners, for example, the p+ connection layer 8 is overlapped on the upper surface of the p+ mask layer 7 or the p+ connection layer 8 is connected with the lower surface of the p+ mask layer.
The source trenches may be alternately arranged, symmetrically arranged, or a plurality of p+ masking layers may be spaced apart, as shown in fig. 8.
The p+ connection layer may also be formed by a variety of connection methods, such as horizontal connection, oblique connection, cross connection, m-connection, etc., as shown in fig. 9.
The P+ connecting layer with the optimized layout can enable the P+ masking layer to be better grounded, reduce miller capacitance, improve switching speed and reduce switching loss.
The invention also provides a preparation method of the trench MOSFET device, which comprises the following steps:
s1, in a wide bandgap semiconductor material (SiC/GaN/Ga 2 O 3 /AlN, etc.) a first N-epitaxial layer is grown on the substrate, see fig. 10a;
s2, forming a P+ masking layer and a P+ connecting layer by means of ion implantation, secondary epitaxy, growing P-type oxide and the like, wherein the P+ masking layer and the P+ connecting layer are shown in FIG. 10b;
s3, growing a second N-epitaxial layer on the first N-epitaxial layer, see FIG. 11c;
s4, forming a P well region 11 by means of ion implantation, secondary epitaxy, growing P-type oxide and the like, and forming a source N+ region 12 by means of ion implantation, as shown in FIG. 10d;
s5, forming a gate trench by dry etching, see FIG. 10e;
s6, forming a source electrode groove by dry etching, wherein the source electrode groove is shown in FIG. 10f;
s7, forming a source electrode P+ region by means of ion implantation, secondary epitaxy and P-type oxide growth, wherein the source electrode P+ region is shown in FIG. 10g;
s8, gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching and source electrode deposition are carried out, see FIG. 10h.
It should be noted that the above examples are only for further illustrating and describing the technical solution of the present invention, and are not intended to limit the technical solution of the present invention, and the method of the present invention is only a preferred embodiment and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. The utility model provides a trench MOSFET device, includes substrate (1) and epitaxial layer (2), gate slot (3), source slot (4) and drain electrode (5) of setting on substrate (1) at least, its characterized in that, be provided with p+ masking layer (7) just under gate slot (3) p+ masking layer is located epitaxial layer (2) are inside, epitaxial layer (2)'s inside still is provided with p+ tie layer (8), p+ masking layer (7) are through p+ tie layer (8) and source ground, p+ masking layer (7) with p+ tie layer (8) do not influence the circulation of electric current.
2. Trench MOSFET device according to claim 1, characterized in that the p+ masking layer (7) and the p+ connection layer (8) are located at the same depth of the epitaxial layer (2), the p+ connection layer (8) being in contact with the source p+ region (9) of the source trench (4).
3. A trench MOSFET device according to claim 1, characterized in that the shape of the p+ masking layer (7) includes, but is not limited to, rectangular, diamond, circular, oval, wave-shaped.
4. The trench MOSFET device according to claim 1, wherein the p+ masking layer (7) is connected by a p+ connection layer (8) including, but not limited to, horizontal connection, oblique connection, cross connection, m-connection; and/or
The source electrode grooves are alternately arranged or symmetrically arranged or are arranged at intervals by a plurality of p+ masking layers; and/or
The grid groove (3) is in a whole section of long strip shape or a discontinuous long strip shape; and/or
When the grid groove (3) is in a discontinuous strip shape, the p+ masking layer (7) is connected with the source electrode through the p+ grounding layers (6) at two sides of the grid groove (3).
5. The trench MOSFET device according to claim 1, wherein the p+ masking layer (7) upper edge is at a distance d from the gate trench bottom, where d > 0 or d = 0 or d < 0; and/or the width of the gate trench is W1, and the p+ masking layer is W2, wherein W1 < W2 or w1=w2 or W1 > W2.
6. The trench MOSFET device of claim 5, wherein when d = 0, W1 ≡w2, the p+ masking layer (7) is in the form of ion implantation by a trench self-aligned process.
7. The trench MOSFET device of claim 5, wherein when d > 0, a p+ protection layer (10) is provided at the bottom of the gate trench (3), the p+ protection layer (10) being connected to the source trench through a p+ ground post (13).
8. The trench MOSFET device of claim 5, wherein d > 0 and the concentration of the N-epitaxial layer above the p+ masking layer is greater than the concentration of the N-epitaxial layer below the p+ masking layer.
9. A method of fabricating a trench MOSFET device according to any one of claims 1 to 8, comprising the steps of:
growing a first N-epitaxial layer on a wide band gap semiconductor material substrate, and then preparing a p+ masking layer and a p+ connecting layer on the first N-epitaxial layer;
after the second N-epitaxial layer grows again, preparing a p-well region and a source N+ region;
etching to form a grid groove and a source groove, and forming a source p+ region;
gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, and source electrode deposition.
10. A MOSFET device according to any one of claims 1 to 8 and a MOSFET device prepared by the method of claim 9.
CN202310363367.9A 2023-04-06 2023-04-06 Groove type MOSFET device and preparation method thereof Pending CN116598352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310363367.9A CN116598352A (en) 2023-04-06 2023-04-06 Groove type MOSFET device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310363367.9A CN116598352A (en) 2023-04-06 2023-04-06 Groove type MOSFET device and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116598352A true CN116598352A (en) 2023-08-15

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