CN116597780A - Display panel and display device - Google Patents

Abstract

The application discloses a display panel and a display device. The output control module is connected in series between the first signal end and the main output end, and is used for transmitting signals of the first signal end to the main output end, the input end of the second main output module is connected with the second signal end, and is used for transmitting signals of the second signal end to the main output end, the picture refreshing frequency of the first display area of the display panel is the first refreshing frequency, the picture refreshing frequency of the second display area is the second refreshing frequency, the output control module in the shift register corresponding to the first display area is conducted, and the output control module in the shift register corresponding to the second display area is cut off in at least part of time periods. The embodiment of the application is beneficial to realizing the partition frequency division display of the display panel.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the continuous update of display technology, the refresh frequency of the display panel is frequently and newly high. For example, the refresh frequency may reach 165Hz, even breakthrough 240Hz. In addition, the reduction of power consumption of the display panel is also a pursuit goal in the art, so that low refresh frequency display is also continuously broken through, for example, the low refresh frequency can reach 1Hz.

In addition, in order to balance the picture display quality and the power consumption to a certain extent, the display panel can support the dynamic refresh frequency, for example, the display panel can support the refresh frequency of 1-120 hz. In the related art, only the entire display area of the display panel is supported to be simultaneously switched, for example, the entire display area is simultaneously switched from one refresh frequency to another refresh frequency. However, this does not satisfy the possibility that various display scenes exist in the entire display area of the display panel, for example, a part of the display area of the entire display area is displayed at a high refresh frequency and a part of the display area is displayed at a low refresh frequency.

How to display the division ratio of the display panel is a technical problem facing those skilled in the art.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, which are beneficial to realizing the partition frequency division display of the display panel.

In a first aspect, an embodiment of the present application provides a display panel, including a gate driving circuit, where the gate driving circuit includes a plurality of stages of shift registers cascaded with each other; the shift register includes: the output unit comprises a first main output module, a second main output module and an output control module; the output control module and the first main output module are connected in series between the first signal end and the main output end and are used for transmitting signals of the first signal end to the main output end, the control end of the first main output module is connected with the first node, the control end of the second main output module is connected with the second node, the input end of the second main output module is connected with the second signal end and is used for transmitting signals of the second signal end to the main output end, and the signals of the first signal end and the second signal end are transmitted to the main output end through the third node; the display area of the display panel comprises a first display area and a second display area, the picture refreshing frequency of the first display area is a first refreshing frequency, the picture refreshing frequency of the second display area is a second refreshing frequency, an output control module in a shift register corresponding to the first display area is conducted, an output control module in a shift register corresponding to the second display area is cut off in at least part of time period, the first refreshing frequency is larger than the second refreshing frequency, a first signal end is used for providing alternating on level and off level, and a second signal end is used for providing off level.

In a possible embodiment of the first aspect, the shift register further includes:

the input end of the first node control module is connected with the starting signal end, and the output end of the first node control module is connected with the first node;

the starting signal generation unit comprises a first auxiliary output module and a second auxiliary output module, wherein the control end of the first auxiliary output module is connected with a first node, the input end of the first auxiliary output module is connected with a first signal end, the control end of the second auxiliary output module is connected with a second node, the input end of the second auxiliary output module is connected with a second signal end, and the output end of the first auxiliary output module and the output end of the second auxiliary output module are connected with the auxiliary output end of the starting signal generation unit;

the auxiliary output end of the starting signal generating unit in the ith shift register is used as a starting signal end connected with the first node control module in the (i+1) th shift register.

In a possible embodiment of the first aspect, the first auxiliary output module and the first main output module each comprise a transistor controlled by a first node, and the second auxiliary output module and the second main output module each comprise a transistor controlled by a second node.

In a possible embodiment of the first aspect, the shift register further includes a first capacitor, one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the auxiliary output terminal.

In a possible embodiment of the first aspect, the shift register further includes a second capacitor, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to the second signal terminal.

In a possible embodiment of the first aspect, the output control module is connected between the first signal terminal and the input terminal of the first main output module;

or the output control module is connected between the output end of the first main output module and the third node;

alternatively, the output control module is connected between the third node and the main output.

In one possible embodiment of the first aspect, the main output terminal is connected to a pixel circuit of the display panel, the shift register includes a plurality of transistors, and the output control module includes a first transistor, where a channel width-to-length ratio of the first transistor is greater than or equal to a channel width-to-length ratio of other transistors of the shift register.

In a possible embodiment of the first aspect, the output control module comprises a first transistor, which is turned on or off under control of the control signal;

The first transistor is a P-type transistor, and the sum of the low level of the first signal end and the threshold voltage of the first transistor is larger than the conduction level of the control signal;

or the first transistor is an N-type transistor, and the sum of the high level of the first signal end and the threshold voltage of the first transistor is smaller than the conduction level of the control signal.

In a possible embodiment of the first aspect, the operation of the pixel circuit in the display panel includes a data writing sub-frame, in which the output control module is turned on;

the working process of the pixel circuit in the second display area further comprises a holding subframe, and the output control module is cut off in the holding subframe.

In a possible embodiment of the first aspect, the display area comprises an edge extending along a first direction, the first display area and the second display area being adjacent in a second direction, the first direction and the second direction intersecting;

the working scene of the display panel comprises a first scene and a second scene, wherein the minimum distance between the boundary line and the edge of the first display area and the second display area is d1 in the first scene, and the minimum distance between the boundary line and the edge of the first display area and the second display area is d2 in the second scene, and d1 is not equal to d2.

In a possible embodiment of the first aspect, the shift register further includes:

The second node control module is used for transmitting the signal received by the input end of the second node control module to a second node;

and the mutual control module is used for controlling the first node and the second node to each other.

Based on the same inventive concept, in a second aspect, an embodiment of the present application further provides a display device, including a display panel according to any one of the embodiments of the first aspect.

According to the display panel and the display device provided by the embodiments of the application, the output control module can control whether the conduction level of the first signal end can be transmitted to the main output end, that is, the output control module can control the conduction level output of the main output end. Because the output control module corresponding to the first display area with relatively higher refresh frequency is conducted, the conducted level of the first signal end can be output with relatively higher refresh frequency, and therefore the first display area can be displayed with relatively higher refresh frequency. The output control module corresponding to the second display area with relatively low refresh frequency is cut off in at least part of the period, so that the conduction level of the first signal end can be output with relatively low refresh frequency, and the second display area can be displayed with relatively low refresh frequency. Therefore, the embodiment of the application can realize the effects of partitioning the display panel and displaying at different refreshing frequencies.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar features, and in which the figures are not to scale.

Fig. 1 is a schematic top view of a display panel according to an embodiment of the present application;

fig. 2 is a schematic circuit diagram of a pixel circuit in a display panel according to an embodiment of the present application;

fig. 3 is a schematic circuit diagram of a shift register in a display panel according to an embodiment of the present application;

fig. 4 is a schematic circuit diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

fig. 6 is a schematic circuit diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

fig. 7 is a schematic circuit diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

fig. 8 is a schematic diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

FIG. 9 is a schematic diagram showing a frame refresh of a display panel according to an embodiment of the present application;

fig. 10 shows a schematic diagram of a partition structure of a display area of a display panel according to an embodiment of the present application;

FIG. 11 is a timing diagram showing two refresh rates of a display panel according to an embodiment of the present application;

fig. 12 is a timing diagram illustrating refresh rate switching of a display panel according to an embodiment of the present application;

fig. 13 is a schematic view showing another partition structure of a display area of a display panel according to an embodiment of the present application;

FIG. 14 shows a timing diagram of the circuit structure of FIG. 3;

FIG. 15 shows another timing diagram of the circuit structure shown in FIG. 3;

FIG. 16 shows a simulated timing diagram of the circuit structure of FIG. 3;

fig. 17 is a schematic diagram showing another circuit structure of a pixel circuit in a display panel according to an embodiment of the present application;

fig. 18 is a schematic diagram showing another circuit structure of a shift register in a display panel according to an embodiment of the present application;

FIG. 19 shows a timing diagram of the circuit structure of FIG. 18;

FIG. 20 shows another timing diagram of the circuit structure shown in FIG. 18;

fig. 21 is a schematic top view of a display device according to an embodiment of the application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to illustrate the application and are not configured to limit the application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

It will be understood that when an element is referred to as being "connected" or "electrically connected" to another element, it can be directly connected to the other element or one or more intervening elements may be present therebetween.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.

Embodiments of the present application provide a display panel and a display device, and embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

Embodiments of the present application provide a display panel, which may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel or other type of display panel.

As shown in fig. 1, the display panel 100 according to the embodiment of the application may include a gate driving circuit 10, and the gate driving circuit 10 may include a plurality of stages of shift registers VSR cascaded with each other. The display panel 100 may further include a pixel circuit 20 and a gate signal line 30, the gate signal line 30 connecting the shift register VSR and the pixel circuit 20. The signal output from the shift register VSR may control at least some of the transistors in the pixel circuit 20 to be turned on or off, and the pixel circuit 20 may be used to drive a light emitting element (not shown in fig. 1) to emit light for display.

The gate driving circuit 10 may be located in a non-display area NA of the display panel, and the pixel circuit 20 may be located in a display area AA of the display panel. The pixel circuits 20 may be arrayed in the first direction X and the second direction Y, and the plurality of shift registers VSR may be arranged in the second direction Y. The first direction X may be a row direction and the second direction Y may be a column direction.

The pixel circuit 20 may have a structure of 7T1C, 8T1C, 2T1C, 4T2C, or the like. As an example, the pixel circuit 20 may include transistors T1 to T7 and a storage capacitor Cst as shown in fig. 2, wherein in fig. 2, the transistors T1 to T7 are represented by P-type transistors, VDD represents a first power supply terminal, VSS represents a second power supply terminal, vref1 represents a first initialization signal, vref2 represents a second initialization signal, vdata represents a data signal, S1 and S2 represent scan signals, and EM represents a light emission control signal. For example, the gate driving circuit 10 may be used to output scan signals S1, S2.

The 7T1C structure of the pixel circuit shown in fig. 2 is only one example and is not intended to limit the present application.

As shown in fig. 3 to 5, the shift register may include an output unit 11, and the output unit 11 may include a first main output module 111, a second main output module 112, and an output control module 113.

The output control module 113 is connected in series with the first main output module 111 between the first signal terminal V1 and the main output terminal Gout. The output control module 113 and the first main output module 111 are configured to transmit the signal of the first signal terminal V1 to the main output terminal Gout.

The control terminal of the first main output module 111 is connected to a first node N1,

the control end of the second main output module 112 is connected to the second node N2, the input end of the second main output module 112 is connected to the second signal end V2, and the second main output module 112 is configured to transmit a signal of the second signal end V2 to the main output end Gout.

The signal of the first signal terminal V1 and the signal of the second signal terminal V2 are both transmitted to the main output terminal Gout through the third node N3.

The main output terminal Gout may be connected to the gates of at least some of the transistors in the pixel circuit 20 to control the turning on or off of at least some of the transistors in the pixel circuit.

The first signal terminal V1 may be used to alternately provide an on level and an off level, and the second signal terminal V2 may be used to provide an off level.

One of the on level and the off level is a low level, and the other is a high level. For example, for a P-type transistor, the on level is low and the off level is high. For another example, in the case of an N-type transistor, the on level is high and the off level is low.

If the signal output from the main output terminal Gout is used to control the P-type transistor in the pixel circuit, the off level provided by the second signal terminal V2 may be a high level, and the on level provided by the first signal terminal V1 may be a low level. In contrast, if the signal output from the main output terminal Gout is used to control the N-type transistor in the pixel circuit, the off level provided by the second signal terminal V2 may be a low level, and the on level provided by the first signal terminal V1 may be a high level.

In fig. 3 to 8, taking the signal output by the main output terminal Gout as an example for controlling the P-type transistor in the pixel circuit, the first signal terminal V1 may include the clock signal terminal SCK2, and the second signal terminal V2 may include the high-level signal terminal VGH. The clock signal terminal SCK2 is used to provide alternating high and low levels. The high level signal terminal VGH is for providing a high level. The high level may be a level of about +7v, and the low level may be a level of about-7V. Here, the first signal terminal V1 is denoted as the second clock signal terminal SCK2 for the convenience of distinguishing other clock signal terminals.

With continued reference to fig. 1, the display area AA of the display panel 100 may include a first display area AA1 and a second display area AA2. The picture refresh frequency of the first display area AA1 is the first refresh frequency F1, and the picture refresh frequency of the second display area AA2 is the second refresh frequency F2, F1 > F2.

The output control module 113 in the shift register VSR corresponding to the first display area AA1 may remain on, and the output control module 113 in the shift register VSR corresponding to the second display area AA2 may be turned off for at least a portion of the period.

The refresh frequency indicates the number of images that can be displayed per second by the display panel. For example, if a certain display area of the display panel is the first refresh frequency F1 and the first refresh frequency F1 is 120HZ, the number of images that can be displayed in the display area per second is 120. The other display area of the display panel is the second refresh frequency F2, and the second refresh frequency F2 is 1HZ, so that the number of times of images which can be displayed in each second of the display area is 1. The higher the refresh frequency of the display panel, the better the displayed image (picture) stability, i.e. the better the display quality. The lower the refresh frequency of the display panel, the lower the power consumption.

It can be understood that the shift register VSR corresponding to the first display area AA1 is: among the plurality of shift registers, a shift register capable of controlling a picture refresh frequency of the first display area AA 1. Similarly, the shift register VSR corresponding to the second display area AA2 is: among the plurality of shift registers, a shift register capable of controlling a picture refresh frequency of the second display area AA2.

According to the display panel provided by the embodiment of the application, the output control module 113 can control whether the low level of the first signal terminal V1 can be transmitted to the main output terminal Gout, that is, the output control module 113 can control the low level output of the main output terminal Gout. Because the output control module 113 corresponding to the first display area with relatively higher refresh frequency is turned on, the low level of the first signal terminal V1 can be output with relatively higher refresh frequency, so that the first display area can be displayed with relatively higher refresh frequency. The output control module 113 corresponding to the second display area with relatively low refresh frequency is turned off at least in part of the period, so that the low level of the first signal terminal V1 can be output with relatively low refresh frequency, and the second display area can be displayed with relatively low refresh frequency. Therefore, the embodiment of the application can realize the effects of partitioning the display panel and displaying at different refreshing frequencies.

The output control module 113 and the first main output unit 111 can control whether the low level of the first signal terminal V1 can be transmitted to the main output terminal Gout by the output control module 113 as long as they are connected in series between the first signal terminal V1 and the main output terminal Gout.

As an example, as shown in fig. 3, the output control module 113 may be connected between the first signal terminal V1 and the input terminal of the first main output module 111.

As another example, as shown in fig. 4, the output control module 113 may be connected between the output terminal of the first main output module 111 and the third node N3.

As yet another example, as shown in fig. 5, the output control module 113 may be connected between the third node N3 and the main output terminal Gout. In this case, in case that the output control module 113 is turned on, the main output terminal Gout may output the signal of the first signal terminal V1 or the signal of the second signal terminal V2; in the case where the output control module 113 is turned off, neither the signal of the first signal terminal V1 nor the signal of the output second signal terminal V2 can be transmitted to the main output terminal Gout, and the main output terminal Gout can maintain the signal received by the main output terminal Gout in the previous stage.

Switching from a high refresh rate to a low refresh rate can be achieved under the control of the output control module 113. In order to achieve switching from a low refresh frequency to a high refresh frequency, the shift register may further comprise a first node control module 12 and a start signal generation unit 13, as shown in fig. 3 to 5.

The first node control module 12 may be connected between the start signal terminal SIN and the first node N1. Under the condition that the first node control module 12 is turned on, the first node control module 12 may transmit the start signal provided by the start signal terminal SIN to the first node N1 to start the shift register to start working. As an example, the control terminal of the first node control module 12 may be connected to the first clock signal terminal SCK1.

The start signal generation unit 13 may include a first auxiliary output module 131 and a second auxiliary output module 132.

The control end of the first auxiliary output module 131 is connected with the first node N1, the input end of the first auxiliary output module 131 is connected with the first signal end V1, and the output end of the first auxiliary output module 131 is connected with the auxiliary output end Carry of the starting signal generating unit 13.

The control end of the second auxiliary output module 132 is connected to the second node N2, the input end of the second auxiliary output module 132 is connected to the second signal end V2, and the output end of the second auxiliary output module 132 is connected to the auxiliary output end Carry of the start signal generating unit 13.

As shown in fig. 1, the auxiliary output port of the start signal generating unit in the i-th stage shift register VSR may be used as the start signal port SIN connected to the first node control module in the i+1-th stage shift register VSR. That is, the signal output from the auxiliary output port Carry of the start signal generation unit in the i-th stage shift register VSR may be used as the start signal of the i+1-th stage shift register VSR.

In the embodiment of the present application, the difference between the start signal generating unit 13 and the output unit 11 is that the start signal generating unit 13 is no longer provided with the output control module 113 for controlling whether the signal of the first signal end V1 can be transmitted to the auxiliary output end Carry, so that the conduction level of the first signal end V1 can be transmitted to the auxiliary output end Carry when the first auxiliary output unit 131 is turned on, the auxiliary output end Carry of the start signal generating unit 13 can output a signal with a high refresh frequency, the signal with a high refresh frequency output by the auxiliary output end Carry of the start signal generating unit 13 of the ith shift register VSR is used as the start signal of the ith+1 shift register VSR, and therefore, when the output control module 113 of the ith shift register VSR is turned off, the main output end Gout of the ith shift register VSR can output a signal with a low refresh frequency, and the main output end Gout of the ith shift register VSR can output a signal with a high refresh frequency, thereby realizing the switching from the low refresh frequency to the high refresh frequency.

It is understood that the auxiliary output port of the start signal generating unit 13 in each stage of shift register VSR can output a signal with a high refresh frequency. For example, if the second refresh rate is switched to the first refresh rate, the auxiliary output port Carry of the start signal generating unit 13 in each stage of shift register VSR can output the signal of the first refresh rate.

As shown in fig. 1, the start signal terminal connected to the input terminal of the first node control module in the first stage shift register is a pad 41 of the display panel, and the pad 41 may be disposed in a non-display area of the display panel. The bonding pad 41 may be connected to a driving chip, and the driving chip may be used to provide an initial start signal and transmit the initial start signal to the first stage shift register through the bonding pad 41 and the connection line to start the first stage shift register to start operating.

The refresh frequency of the auxiliary output port output signal of the start signal generation unit 13 is equal to the refresh frequency of the start signal supplied from the terminal 41.

In some embodiments, as shown in any of fig. 3-5, the first auxiliary output module 131 and the first main output module 111 each include a transistor controlled by the first node N1. That is, the first auxiliary output module 131 and the first main output module 111 have the same structure. For example, the first main output module 111 includes a transistor M7, the first auxiliary output module 131 includes a transistor M11, the gate of the transistor M7 and the gate of the transistor M11 are both connected to the first node N1, and the first pole of the transistor M7 and the first pole of the transistor M11 are both connected to the first signal terminal V1. The second pole of the transistor M7 is electrically connected to the main output terminal Gout, and the second pole of the transistor M11 is connected to the auxiliary output terminal Carry.

The second auxiliary output module 132 and the second main output module 112 each include a transistor controlled by the second node N2. That is, the second auxiliary output module 132 and the second main output module 112 have the same structure. For example, the second main output module 112 includes a transistor M6, the second auxiliary output module 132 includes a transistor M10, the gate of the transistor M6 and the gate of the transistor M10 are both connected to the second node N2, and the first pole of the transistor M6 and the first pole of the transistor M10 are both connected to the second signal terminal V2. The second pole of the transistor M6 is electrically connected to the main output terminal Gout, and the second pole of the transistor M10 is connected to the auxiliary output terminal Carry.

In the embodiment of the application, each output module only comprises one transistor, so that the output control of the output end can be realized, and the output modules with the control end connected with the same node and the input end connected with the same signal end comprise transistors, thereby being beneficial to enabling the high level sizes output by different output ends to be basically consistent or the low level sizes output by different output ends to be basically consistent.

In some embodiments, as shown in fig. 3, the shift register may further include a first capacitor C1. One end of the first capacitor C1 is connected with the first node N1, and the other end of the first capacitor C is connected with the auxiliary output end Carry. The first capacitor C1 may help to stabilize the potential of the first node N1.

In some embodiments, as shown in fig. 3, the shift register may further include a second capacitor C2. One end of the second capacitor C2 is connected with the second node N2, and the other end of the second capacitor C is connected with the second signal end V2. The second capacitor C2 may help to stabilize the potential of the second node N1.

In some embodiments, as shown in fig. 3, the shift register may further include a second node control module 14 and a mutual control module 15.

The second node control module 14 may be configured to transmit the signal received at its input to the second node N2. For example, when the potential of the second node N2 is low, the second main output module 112 and the second auxiliary output module 132 can be turned on, and the input terminal of the second node control module 14 can be connected to the low level signal terminal VGL. The low level signal terminal VGL may provide a signal of about-7V.

The mutual control module 15 may be configured to control the first node N1 and the second node N2.

For example, the mutual control module 15 may include a pull-up sub-module composed of transistors M2, M3 and a pull-down sub-module composed of transistors M41, M42. The pull-up sub-module may be used to pull up the potential of the first node N1 under the control of the second node N2, and the pull-down sub-module may be used to pull down the potential of the second node N2 under the control of the first node N1.

The shift register may include a plurality of transistors, as an example, as shown in fig. 3, the first node control module 12 may include a transistor M1, the inter-control module 15 includes transistors M2, M3, M41, M42, the second node control module 14 includes a transistor M5, the second main output module 112 includes a transistor M6, the first main output module 111 includes a transistor M7, the output control module 113 includes a transistor M9, the second auxiliary output module 132 includes a transistor M10, and the first auxiliary output module 131 includes a transistor M11. The shift register may further include a transistor M8.

The gate of the transistor M1 serves as the control terminal of the first node control module 12, the first pole of the transistor M1 serves as the input terminal of the first node control module 12, and the second pole of the transistor M1 serves as the output terminal of the first node control module 12.

The gate of the transistor M2 is connected to the second clock signal terminal SCK2, the first pole of the transistor M2 is electrically connected to the first node N1, the second pole of the transistor M2 is connected to the first pole of the transistor M3, the gate of the transistor M3 is connected to the second node N2, and the second pole of the transistor M3 is connected to the high-level signal terminal VGH.

The gate of the transistor M41 is electrically connected to the first node N1, the first pole of the transistor M41 is connected to the first clock signal terminal SCK1, the second pole of the transistor M41 is connected to the first pole of the transistor M42, the gate of the transistor M42 is connected to the second clock signal terminal SCK2, and the second pole of the transistor M42 is connected to the second node N2.

The gate of the transistor M5 is used as the control terminal of the second node control module 14, the first pole of the transistor M5 is used as the input terminal of the second node control module 14, and the second pole of the transistor M5 is used as the output terminal of the second node control module 14.

The gate of the transistor M6 serves as the control terminal of the second main output module 112, the first pole of the transistor M6 serves as the input terminal of the second main output module 112, and the second pole of the transistor M6 serves as the output terminal of the second main output module 112.

The gate of the transistor M7 serves as the control terminal of the first main output module 111, the first pole of the transistor M7 serves as the input terminal of the first main output module 111, and the second pole of the transistor M7 serves as the output terminal of the first main output module 111.

The gate of the transistor M8 is connected to the low-level signal terminal VGL, the first pole of the transistor M8 is connected to the second pole of the transistor M1, the first pole of the transistor M41 and the first pole of the transistor M2, and the second pole of the transistor M8 is connected to the first node N1.

The gate of the transistor M9 is used as the control terminal of the output control module 113, the first pole of the transistor M9 is used as the input terminal of the output control module 113, and the second pole of the transistor M9 is used as the output terminal of the output control module 113.

The gate of the transistor M10 serves as the control terminal of the second auxiliary output module 132, the first pole of the transistor M10 serves as the input terminal of the second auxiliary output module 132, and the second pole of the transistor M10 serves as the output terminal of the second auxiliary output module 132.

The gate of the transistor M11 serves as the control terminal of the first auxiliary output module 131, the first pole of the transistor M11 serves as the input terminal of the first auxiliary output module 131, and the second pole of the transistor M11 serves as the output terminal of the first auxiliary output module 131.

It should be noted that, in the case where the shift register includes the transistor M42, the operation stability of the shift register is more facilitated. If the shift register is based on the whole size, the transistor M42 may not be provided, and the second diode of the transistor M41 may be connected to the second node N2.

For convenience of description, the transistor M9 included in the output control module 113 is referred to as a first transistor M9. The channel width to length ratio (W/L) of the first transistor M9 may be greater than or equal to the channel width to length ratio of any other transistor in the shift register.

Since the main output terminal Gout is connected to the pixel circuit of the display panel, the main output terminal Gout has a larger load (loading), and if the channel width length ratio of the first transistor M9 is larger, the driving capability of the signal output by the main output terminal Gout can be improved.

Illustratively, the channel width to length ratio of the transistors M6, M7 may be greater than the channel width to length ratios of the other transistors in the shift register, except for the first transistor M9 and the transistors M10, M11. The channel width-to-length ratio of the transistors M10, M11 may be larger than the channel width-to-length ratios of the other transistors in the shift register, except for the first transistor M9 and the transistors M6, M7.

In addition, the auxiliary output terminal Carry is not connected with the pixel circuit, and the signal output by the auxiliary output terminal Carry is only used as the starting signal of the next stage shift register, so that the load of the auxiliary output terminal Carry is smaller than that of the main output terminal Gout, and therefore, the channel width-to-length ratio of the transistors M6 and M7 can be larger than that of the transistors M10 and M11.

As an example, as shown in fig. 3 to 5, the first transistor M9 may be a P-type transistor, and the first transistor M9 is turned on or off under the control of the control signal SW. It is understood that, in the case where the first transistor M9 is a P-type transistor, the first transistor M9 is turned on when the control signal SW is at a low level, and the first transistor M9 is turned off when the control signal SW is at a high level.

Since there is a voltage loss (loss) in the process of transmitting the signal by the transistor, the sum of the low level of the first signal terminal V1 and the threshold voltage Vth of the first transistor M9 is greater than the on level of the control signal SW. For example, if the first transistor M9 is a P-type transistor, the low level of the first signal terminal V1 is vgl, the on level of SW is SW1, and SW1 < vgl +vth. This ensures that the first transistor M9 is turned on.

As another example, as shown in fig. 6 to 8, the first transistor M9 may be an N-type transistor, and the first transistor M9 is turned on or off under the control of the control signal SW. It is understood that, when the first transistor M9 is an N-type transistor, the first transistor M9 is turned on when the control signal SW is at a high level, and the first transistor M9 is turned off when the control signal SW is at a low level.

Similarly, due to the voltage loss (loss) during the signal transmission process of the transistor, the sum of the high level of the first signal terminal V1 and the threshold voltage Vth of the first transistor M9 is smaller than the on level of the control signal SW. For example, if the first transistor M9 is an N-type transistor, the high level of the first signal terminal V1 is vgh, the on level of SW is SW2, and SW2 > vgh +vth. This ensures that the first transistor M9 is turned on.

For example, the control terminals of the output control modules 113 in the multi-stage shift register may be connected to the same control signal terminal, and the same control signal terminal may output the control signals SW of different levels in a time-sharing manner. For example, the i-th to j-th shift registers correspond to the first refresh frequency F1, the j+1-th shift registers correspond to the second refresh frequency F2, F1 > F2, i < j, and j+1 < p, and the control signal SW output from the control signal terminal may be on level first and then off level.

In some embodiments, the operation of each pixel circuit in the display panel may include a data writing sub-frame (active frame). The operation of the pixel circuits in the second display area may further include maintaining a sub-Frame (Idle Frame). For example, the operation of the pixel circuits in the first display area may include only the data writing sub-frame, and the operation of the pixel circuits in the second display area may include the data writing sub-frame and the holding sub-frame. In the data writing sub-frame, a data signal (Vdata) can be written to the driving transistor gate of the pixel circuit. In the hold sub-frame, the data signal (Vdata) is no longer written to the drive transistor gate of the pixel circuit.

As shown in fig. 9, the data write sub-Frame (active Frame) and the hold sub-Frame (Idle Frame) are introduced at a refresh frequency of 60 Hz.

In the case of 60Hz, 60 frames are refreshed in 1 second time, each frame time=1 s/60=16.67 ms.

When the refresh frequency decreases, scan driving is performed by using a Skip frame method, for example, 60 times per second refresh is still maintained at 30Hz, but writing of a data signal (Vdata) is performed in an odd frame of 1/3/5/7 …/59 as a data writing sub-frame (active frame); the data signal (Vdata) is not written in the 2/4/6/8 …/60 even Frame as the hold subframe (Idle Frame). Thus, the 30Hz line scan time coincides with the 60Hz line scan time. In fig. 9, VSYNC represents a vertical synchronization signal.

In some embodiments, as shown in fig. 10, the display panel includes two first display areas AA1 and one second display area AA2, and the second display area AA2 is located between the two first display areas AA 1. The frame refresh frequencies of the first display area AA1 are both the first refresh frequency F1, and the frame refresh frequencies of the second display area AA2 are both the second refresh frequency F2. For example, if F1 is 120HZ and F2 is 1HZ, the refresh rate switching sequence for the entire display area is 120HZ to 1HZ to 120HZ.

As shown in fig. 11, the Frame refresh frequency of the first display area AA1 is 120HZ, the operation of the pixel circuits in the first display area AA1 may include only a data writing sub-Frame (Active Frame), the Frame refresh frequency of the second display area AA2 is 1HZ, and the operation of the pixel circuits in the second display area AA2 may include a data writing sub-Frame (Active Frame) and a holding sub-Frame (Idle Frame). The refresh frequency switching sequence is 120HZ to 1HZ to 120HZ, and the gate driving circuit needs to output the timing shown in fig. 12. It can be understood that the main output terminal Gout of the shift register for driving the first display area AA1 needs to output a timing corresponding to 120HZ, and the main output terminal Gout of the shift register for driving the second display area AA2 needs to output a timing corresponding to 1 HZ.

As described above, in the data writing sub-frame, the writing of the data signal (Vdata) is required, and in the holding sub-frame, the writing of the data signal (Vdata) is not performed any more. To avoid affecting the writing of the data signal during the refresh frequency switching, the output control module 113 may remain on during the data writing sub-frame and the output control module 113 may be turned off during the holding sub-frame.

For example, the output control module 113 is turned off when the control signal SW is at a high level, turned on when it is at a low level, the high level may be equal to the level of the high level signal terminal VGH, and the low level may be equal to the level of the low level signal terminal VGL. As shown in fig. 10, the two first display areas AA1 may include only data writing subframes, and the control signals SW received by the output control modules 113 of the shift registers corresponding to the two first display areas AA1 may be at a low level. The second display area AA2 may include a data writing sub-frame and a holding sub-frame, and the control signal SW received by the output control module 113 of the shift register corresponding to the second display area AA2 in the holding sub-frame may be at a high level.

In the embodiment of the application, in the data writing sub-frame, the output control module 113 can be kept on, in the holding sub-frame, the output control module 113 can be cut off, so that in the data writing sub-frame, waveforms of the main output end Gout of the shift register corresponding to the display area with high refresh frequency and the display area with low refresh frequency are normally output, and the conversion of the waveforms of the main output end Gout of the shift register corresponding to the refresh frequency switching occurs in the holding sub-frame, thereby not only realizing the frequency switching, but also avoiding influencing the writing of data signals in the refresh frequency switching process.

In some embodiments, referring to fig. 10, the display area AA includes a first edge a1 extending along a first direction X. The first display area AA1 and the second display area AA2 are adjacent in the second direction Y, and the first direction and the second direction intersect. For example, a boundary between one of the first display area AA1 and the second display area AA2 is L.

The operation scene of the display panel may include a first scene and a second scene. In the first scene, the minimum distance between the boundary L and the first edge a1 is d1, and in the second scene, the minimum distance between the boundary L and the first edge a1 is d2, d1+.d2.

Therefore, the partition positions of the display areas with different refreshing frequencies can be not fixed, and the dynamic adjustment of the positions can be realized according to scene requirements and/or display pictures.

For example, the control signal SW of the output control module 113 may be synchronized with a scene requirement or a picture requirement, for example, the positions of the display areas of different refresh frequencies may be determined according to the scene requirement or the picture requirement, and then the level of the control signal SW is determined according to the positions of the display areas of different refresh frequencies.

In order to better understand that the shift register provided by the embodiment of the present application can realize the switching of the refresh frequency, the working process of the shift register is described below with the circuit structure shown in fig. 3.

Referring to fig. 3 and 14 in combination, the control signal SW is high in all stages t11 to t14, and the first transistor M9 is turned off.

In the stage t11, the start signal terminal SIN and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, the transistors M1 and M5 are turned on, the first node N1 and the second node N2 are both low level, the transistors M10, M11, M6 and M7 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

In the stage t12, the start signal terminal SIN and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 maintains a low level, the potential of the second node N2 changes to a high level, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs a low level, but the main output terminal Gout maintains a high level due to the turn-off of the first transistor M9.

In the stage t13, the start signal terminal SIN and the second clock signal terminal SCK2 provide a high level, the first clock signal terminal SCK1 provides a low level, the potential of the first node N1 changes to a high level, the potential of the second node N2 changes to a low level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

In the stage t14, the start signal terminal SIN and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 maintains a high level, the potential of the second node N2 maintains a low level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

In the following, the auxiliary output terminal Carry outputs a high level and the main output terminal Gout outputs a high level due to the turn-off of the transistor M7 regardless of the level of the control signal SW. Thus, in addition to the control signal SW, a cycle of phases t13 and t14 follows.

It can be seen that the auxiliary output terminal Carry normally outputs a waveform when the control signal SW is at a high level, and the signal of the main output terminal Gout is at a high level.

Note that, in fig. 14, the control signal SW is shown as a low level in a stage subsequent to the stage t14, which is not intended to limit the present application. For example, in other examples, the control signal SW may be high at a stage subsequent to the t14 stage.

Referring to fig. 3 and 15 in combination, the control signal SW is low in all phases t15 to t18, and the first transistor M9 is turned on.

In the stage t15, the start signal terminal SIN and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, the transistors M1 and M5 are turned on, the first node N1 and the second node N2 are both low level, the transistors M10, M11, M6 and M7 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

In the stage t16, the start signal terminal SIN, the first clock signal terminal SCK1, the second clock signal terminal SCK2, the first node N1, the second node N2, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level due to the turn-on of the first transistor M9.

In the stage t17, the start signal terminal SIN and the second clock signal terminal SCK2 provide a high level, the first clock signal terminal SCK1 provides a low level, the potential of the first node N1 changes to a high level, the potential of the second node N2 changes to a low level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

In the stage t18, the start signal terminal SIN and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the potential of the first node N1 maintains a high level, the potential of the second node N2 maintains a low level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level.

The cycle of phases t17 and t18 follows.

It can be seen that the auxiliary output terminal Carry and the main output terminal Gout can normally output waveforms when the control signal SW is at a low level.

It can be seen that the switching from high refresh rate to low refresh rate and the switching from low refresh rate to high refresh rate can be achieved by controlling the output control module (the first transistor M9) to be turned on or off in combination with the use of the start signal generating unit (the transistors M10 and M11).

In order to further verify the function of the shift register provided by the embodiment of the present application, please refer to the simulation diagram shown in fig. 16, it can be clearly obtained: when the control signal SW is at a high level, the auxiliary output end Carry normally outputs waveforms, and the signal of the main output end Gout is at a high level; when the control signal SW is low, the auxiliary output terminal Carry and the main output terminal Gout can both output waveforms normally.

In the above embodiments, taking the signal output by the main output terminal Gout as an example for controlling the P-type transistor in the pixel circuit, the signal output by the main output terminal Gout of the gate driving circuit provided by the embodiment of the present application may also be used for controlling the N-type transistor in the pixel circuit.

As shown in fig. 17, the same points as those of fig. 2 are not described in detail, except that the transistors T4 and T5 are N-type transistors, the other transistors are P-type transistors, the scan signal S1N, S N is used for controlling the N-type transistors to be turned on or off, and the scan signal S1P, S P is used for controlling the P-type transistors to be turned on or off. The signal output by the main output terminal Gout of the gate driving circuit provided by the embodiment of the application can comprise a scanning signal S1N, S N.

In the case where the signal output from the main output terminal Gout is used to control the N-type transistor in the pixel circuit, as shown in fig. 18, the first signal terminal V1 may include the clock signal terminal SCK2, and the second signal terminal V2 may include the low level signal terminal VGL. The off level provided by the second signal terminal V2 may be a low level, and the on level provided by the first signal terminal V1 may be a high level.

Fig. 18 is different from fig. 3 in that the transistors shown in fig. 18 may be N-type transistors. The first pole of the transistor M5 is connected to the high-level signal terminal VGH, and the second pole of the transistor M3 is connected to the low-level signal terminal VGL. The gate of the transistor M8 is connected to the high-level signal terminal.

In the case that the signal output by the shift register is used to control the N-type transistor in the pixel circuit, the working process may be as follows:

referring to fig. 18 and 19 in combination, the control signal SW is low and the first transistor M9 is turned off in the period from t21 to t 24.

In the stage t21, the start signal terminal SIN and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the transistors M1 and M5 are turned on, the first node N1 and the second node N2 are both in a high level, the transistors M10, M11, M6 and M7 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

In the stage t22, the start signal terminal SIN, the first clock signal terminal SCK1 provides a low level, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 maintains the high level, the potential of the second node N2 becomes the low level, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs the high level, but the main output terminal Gout maintains the low level due to the turn-off of the first transistor M9.

In the stage t23, the start signal terminal SIN and the second clock signal terminal SCK2 provide a low level, the first clock signal terminal SCK1 provides a high level, the potential of the first node N1 becomes a low level, the potential of the second node N2 becomes a high level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

In the stage t24, the start signal terminal SIN and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 maintains a low level, the potential of the second node N2 maintains a high level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a high level.

In the following, the auxiliary output terminal Carry outputs a high level and the main output terminal Gout outputs a high level due to the turn-off of the transistor M7 regardless of the level of the control signal SW. Thus, in addition to the control signal SW, a cycle of phases t23 and t24 follows.

It can be seen that the auxiliary output port normally outputs a waveform when the control signal SW is at a low level, and the signal of the main output port Gout is at a low level.

Note that, in fig. 19, the control signal SW is shown as a high level at a stage subsequent to the stage t24, which is not intended to limit the present application. For example, in other examples, the control signal SW may be low at a stage subsequent to the t24 stage.

Referring to fig. 18 and 20 in combination, the control signal SW is high in all stages t25 to t28, and the first transistor M9 is turned on.

In the stage t25, the start signal terminal SIN and the first clock signal terminal SCK1 provide a high level, the second clock signal terminal SCK2 provides a low level, the transistors M1 and M5 are turned on, the first node N1 and the second node N2 are both in a high level, the transistors M10, M11, M6 and M7 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

In the stage t26, the start signal terminal SIN, the first clock signal terminal SCK1 provides a low level, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 maintains the high level, the potential of the second node N2 becomes a low level, the transistors M11 and M7 are turned on, the auxiliary output terminal Carry outputs a high level, and the main output terminal Gout outputs a high level due to the conduction of the first transistor M9.

In the stage t27, the start signal terminal SIN and the second clock signal terminal SCK2 provide a low level, the first clock signal terminal SCK1 provides a high level, the potential of the first node N1 becomes a low level, the potential of the second node N2 becomes a high level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

In the stage t28, the start signal terminal SIN and the first clock signal terminal SCK1 provide a low level, the second clock signal terminal SCK2 provides a high level, the potential of the first node N1 maintains a low level, the potential of the second node N2 maintains a high level, the transistors M10 and M6 are turned on, the auxiliary output terminal Carry outputs a low level, and the main output terminal Gout outputs a low level.

The cycle of phases t27 and t28 follows.

It can be seen that the auxiliary output terminal Carry and the main output terminal Gout can normally output waveforms when the control signal SW is at a high level.

It should be noted that, the specific structures of the shift register provided in the embodiments of the present application are only examples, and are not intended to limit the present application. The technical concept provided by the embodiment of the application based on the output control module and/or the start signal generating unit to realize the refresh frequency switching can also be applied to shift registers with other structures, and is not listed here.

It should be further noted that the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate potential of the N-type transistor is on between the first and second poles when the gate potential is high, and is off between the first and second poles when the gate potential is low. For a P-type transistor, the on level is low and the off level is high. That is, when the gate potential of the P-type transistor is at a low level, the first and second poles are turned on, and when the gate potential of the P-type transistor is at a high level, the first and second poles are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.

Based on the same inventive concept, the application also provides a display device comprising the display panel provided by the application. Referring to fig. 21, fig. 21 is a schematic structural diagram of a display device according to an embodiment of the application. Fig. 21 provides a display device 1000 including a display panel 100 according to any of the above embodiments of the present application. The embodiment of fig. 21 is only an example of a mobile phone, and the display device 1000 is described, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, which is not particularly limited in the present application. The display device provided by the embodiment of the present application has the beneficial effects of the display panel provided by the embodiment of the present application, and the specific description of the display panel in the above embodiments may be referred to specifically, and this embodiment is not repeated here.

These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.

Claims (10)

1. A display panel, comprising:

the grid driving circuit comprises a plurality of stages of shift registers which are cascaded with each other;

the shift register includes:

the output unit comprises a first main output module, a second main output module and an output control module;

the output control module and the first main output module are connected in series between a first signal end and a main output end, and are used for transmitting signals of the first signal end to the main output end, the control end of the first main output module is connected with a first node, the control end of the second main output module is connected with a second node, the input end of the second main output module is connected with a second signal end, and is used for transmitting signals of the second signal end to the main output end, and the signals of the first signal end and the second signal end are transmitted to the main output end through a third node;

the display area of the display panel comprises a first display area and a second display area, the picture refreshing frequency of the first display area is a first refreshing frequency, the picture refreshing frequency of the second display area is a second refreshing frequency, the output control module in the shift register corresponding to the first display area is conducted, the output control module in the shift register corresponding to the second display area is cut off in at least part of time period, the first refreshing frequency is larger than the second refreshing frequency, the first signal end is used for providing alternating on level and off level, and the second signal end is used for providing off level.

2. The display panel of claim 1, wherein the shift register further comprises:

the input end of the first node control module is connected with a starting signal end, and the output end of the first node control module is connected with the first node;

the starting signal generation unit comprises a first auxiliary output module and a second auxiliary output module, wherein the control end of the first auxiliary output module is connected with the first node, the input end of the first auxiliary output module is connected with the first signal end, the control end of the second auxiliary output module is connected with the second node, the input end of the second auxiliary output module is connected with the second signal end, and the output end of the first auxiliary output module and the output end of the second auxiliary output module are connected with the auxiliary output end of the starting signal generation unit;

and an auxiliary output end of a starting signal generating unit in the ith stage of shift register is used as the starting signal end connected with a first node control module in the (i+1) th stage of shift register.

3. The display panel of claim 2, wherein the first auxiliary output module and the first main output module each comprise a transistor controlled by the first node, and the second auxiliary output module and the second main output module each comprise a transistor controlled by the second node;

Preferably, the shift register further includes a first capacitor, one end of the first capacitor is connected to the first node, and the other end of the first capacitor is connected to the auxiliary output end;

preferably, the shift register further includes a second capacitor, one end of the second capacitor is connected to the second node, and the other end of the second capacitor is connected to the second signal end.

4. The display panel of claim 1, wherein the output control module is connected between the first signal terminal and an input terminal of the first main output module;

or the output control module is connected between the output end of the first main output module and the third node;

alternatively, the output control module is connected between the third node and the main output.

5. The display panel of claim 1, wherein the main output terminal is connected to a pixel circuit of the display panel, the shift register comprises a plurality of transistors, the output control module comprises a first transistor, and a channel width-to-length ratio of the first transistor is greater than or equal to a channel width-to-length ratio of other transistors of the shift register.

6. The display panel of claim 1, wherein the output control module comprises a first transistor that is turned on or off under control of a control signal;

The first transistor is a P-type transistor, and the sum of the low level of the first signal end and the threshold voltage of the first transistor is larger than the conduction level of the control signal;

or the first transistor is an N-type transistor, and the sum of the high level of the first signal end and the threshold voltage of the first transistor is smaller than the conduction level of the control signal.

7. The display panel of claim 1, wherein the operation of the pixel circuits in the display panel includes a data write sub-frame in which the output control module is turned on;

the working process of the pixel circuit in the second display area further comprises a maintaining subframe, and the output control module is cut off in the maintaining subframe.

8. The display panel of claim 1 or 2, wherein the display region includes an edge extending along a first direction, the first display region and the second display region being adjacent in a second direction, the first direction and the second direction intersecting;

the working scene of the display panel comprises a first scene and a second scene, the minimum distance between the boundary line of the first display area and the second display area and the edge is d1, and the minimum distance between the boundary line of the first display area and the second display area and the edge is d2, wherein d1 is not equal to d2.

9. The display panel according to any one of claims 1 to 8, wherein the shift register further comprises:

the second node control module is used for transmitting the signal received by the input end of the second node control module to the second node;

and the mutual control module is used for controlling the first node and the second node to each other.

10. A display device comprising the display panel according to any one of claims 1 to 9.