CN113421604A

CN113421604A - Shift register, control method, gate drive circuit and display device

Info

Publication number: CN113421604A
Application number: CN202110690424.5A
Authority: CN
Inventors: 魏立恒; 杨慧娟; 刘庭良; 王予; 李灵通; 廖茂颖; 舒晓青; 刘松; 陈天赐
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-06-22
Filing date: 2021-06-22
Publication date: 2021-09-21
Anticipated expiration: 2041-06-22
Also published as: CN113421604B

Abstract

The application discloses a shift register, a grid driving circuit, a display device and a control method. The shift register includes an input sub-circuit, a first control sub-circuit, a second control sub-circuit, and an output sub-circuit. The input sub-circuit is connected to the first node and the second node, and controls potentials of the first node and the second node according to an input signal and a first clock signal. The first control sub-circuit is connected with the first node and the second node and is used for controlling the potential of the first node according to the potential of the second node and a second clock signal. The second control sub-circuit is connected with the first node, the second node and the third node and is used for controlling the potential of the third node according to the potential of the first node, the potential of the second node, a second clock signal and an input signal. The output sub-circuit is connected to the first node, the third node, the first level terminal and the second level terminal, and is capable of outputting a first output signal according to a potential of the third node. Therefore, the abnormal output phenomenon caused by the positive bias of the threshold voltage of the transistor is avoided.

Description

Shift register, control method, gate drive circuit and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a shift register, a control method, a gate driving circuit, and a display device.

Background

Generally, in the driving scheme of the conventional PMOS OLED internal compensation pixel circuit, an EM GOA circuit is required to output an EM (emission light) signal to the pixel driving circuit. In the related art, outputting the EM signal may be implemented by an EM GOA circuit of 12T 3C. However, in the EM GOA circuit using 12T3C, the threshold voltage Vth of some transistors is biased positively during operation, which results in abnormal output of the EM GOA circuit during some operation stages.

Disclosure of Invention

The present application is directed to solving at least one of the problems in the prior art. Therefore, the present application needs to provide a shift register, a control method, a gate driving circuit and a display device.

The shift register of the embodiment of the application comprises an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit;

the input sub-circuit is connected with a first node and a second node and is used for controlling the potentials of the first node and the second node according to an input signal and a first clock signal;

the first control sub-circuit is connected with the first node and the second node and is used for controlling the potential of the first node according to the potential of the second node and a second clock signal;

the second control sub-circuit is connected with the first node, the second node and a third node and is used for controlling the potential of the third node according to the potential of the first node, the potential of the second node, the second clock signal and the input signal;

the output sub-circuit is connected with the first node, the third node, the first level end and the second level end, and outputs a first output signal according to the potential of the third node or outputs a second output signal according to the potential of the first node;

the period of the first clock signal and the period of the second clock signal are two unit time lengths, and the shift register outputs the first output signal after receiving the input signal which is less than or equal to one unit time length.

In some embodiments, the second control sub-circuit comprises:

a first control unit connected to the first node, the third node, and the first level terminal;

a second control unit connected to the second node, the third node, the signal input terminal, a second clock signal terminal, the first level terminal, and the second level terminal.

In some embodiments, the first control unit includes a sixth transistor, a first pole of the sixth transistor is connected to the first level terminal, a second pole of the sixth transistor is connected to the third node, and a gate of the sixth transistor is connected to the first node.

In some embodiments, the second control unit includes a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor, and a third capacitor; wherein,

a first pole of the seventh transistor is connected with a second clock signal end, a second pole of the seventh transistor is connected with a seventh node, and a grid electrode of the seventh transistor is connected with an input signal end;

a first pole of the eighth transistor is connected to the ninth transistor, a second pole of the eighth transistor is connected to a third node, and a gate of the eighth transistor is connected to the seventh node;

a first pole of the ninth transistor is connected to the second level terminal, a second pole of the ninth transistor is connected to the second pole of the eighth transistor, and a gate of the ninth transistor is connected to the second node;

the second capacitor is connected with the second clock signal end and the second node;

the third capacitor is connected between the first level terminal and the seventh node.

In some embodiments, the first control sub-circuit comprises a fourth transistor, a fifth transistor, and a first capacitance;

a first pole of the fourth transistor is connected with a second clock signal end, a second pole of the fourth transistor is connected with a sixth node, and a grid electrode of the fourth transistor is connected with an input signal end and the first node;

a first pole of the fifth transistor is connected to the first level terminal, a second pole of the fifth transistor is connected to the sixth node, and a gate of the fifth transistor is connected to the second node;

the first capacitor is connected with the first node and the sixth node.

In some embodiments, the output sub-circuit includes a tenth transistor, an eleventh transistor, and a signal output terminal;

a first pole of the tenth transistor is connected to the first level terminal, a second pole of the tenth transistor is connected to the signal output terminal, and a gate of the tenth transistor is connected to the third node;

a first pole of the eleventh transistor is connected to the second level terminal, a second pole of the eleventh transistor is connected to the signal output terminal, and a gate of the eleventh transistor is connected to the first node.

In some embodiments, the input sub-circuit includes a first transistor, a second transistor, and a third transistor; wherein,

a first pole of the first transistor is connected with a signal input end, a second pole of the first transistor is connected with a fourth node, and a grid electrode of the first transistor is connected with a first clock signal end;

a first pole of the second transistor is connected with the first clock signal end, a second pole of the second transistor is connected with a fifth node, and a grid electrode of the second transistor is connected with the fourth node;

a first pole of the third transistor is connected to a second level terminal, a second pole of the third transistor is connected to the fifth node, and a gate of the third transistor is connected to the first clock signal terminal.

In some embodiments, the shift register further comprises an isolation subcircuit comprising a twelfth transistor and a thirteenth transistor; wherein,

a first pole of the twelfth transistor is connected to the fourth node, a second pole of the twelfth transistor is connected to the first node, and a gate of the twelfth transistor is connected to the second level terminal;

a first pole of the thirteenth transistor is connected to the fifth node, a second pole of the thirteenth transistor is connected to the second node, and a gate of the thirteenth transistor is connected to the second level terminal.

The gate driving circuit of the embodiment of the present application includes a plurality of cascaded shift registers, where except for the first stage shift register, a signal input terminal of the shift register of the present stage is electrically connected to a signal output terminal of the shift register of the previous stage.

The display device of the embodiment of the application comprises a pixel driving circuit and the gate driving circuit, wherein the gate driving circuit is connected with the pixel driving circuit to provide a light-emitting control signal for the pixel driving circuit.

A control method according to an embodiment of the present invention is a control method for controlling the shift register described in any one of the above, including:

providing the input signal to the shift register to control the shift register to output the first output signal after receiving the input signal for less than or equal to one unit time length; or

And stopping providing the input signal to the shift register to control the shift register to output the second output signal after stopping receiving the input signal for less than or equal to one unit time length.

In some embodiments, the control method further comprises:

determining the low level duration of the second clock signal as a low level signal;

and when the second clock signal is a low level signal and lasts for a preset time length, controlling the signal input end to transmit an input signal to the register, wherein the preset time length is less than the time length of the low level signal.

In the shift register, the gate driving circuit, the display device, and the control method according to the embodiments of the present application, the input sub-circuit, the first control sub-circuit, the second control sub-circuit, and the output sub-circuit are provided, and the first output signal is output after the input sub-circuit receives the input signal and is less than or equal to one unit duration. This is done. The positive bias of the threshold voltage Vth of the transistor in the shift register is avoided, and the output sub-circuit of the shift register can normally output the first output signal.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a block diagram of a shift register according to an embodiment of the present invention.

Fig. 2 is a schematic block diagram of a shift register according to an embodiment of the present invention.

Fig. 3 is a circuit connection diagram of a shift register according to an embodiment of the present invention.

Fig. 4 is a timing diagram of a shift register according to an embodiment of the present application in some scenarios.

Fig. 5 to 6 are schematic flowcharts of a shift register control method according to an embodiment of the present application.

Fig. 7 is a block diagram of a gate driving circuit according to an embodiment of the present disclosure.

Fig. 8 is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure in some scenarios.

Fig. 9 is a block diagram of a display device according to an embodiment of the present application.

Description of the main element symbols:

an input sub-circuit 11, a first transistor T1, a second transistor T2, a third transistor T3;

the first control sub-circuit 12, the fourth transistor T4, the fifth transistor T5, the first capacitor C1;

the second control sub-circuit 13, the first control unit 131, the sixth transistor T6, the second control unit 132, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the second capacitor C2, and the third capacitor C3;

the output sub-circuit 14, the tenth transistor T11, the eleventh transistor T12, and the signal output terminal OUT;

an isolation sub-circuit 15, a twelfth transistor T12, a thirteenth transistor T13;

a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, a sixth node N6, a seventh node N7;

the circuit comprises a signal input end STV, a first level end VGH, a second level end VGL, a first clock signal end CK and a second clock signal end CB;

a shift register 10, a gate driving circuit 100, a pixel driving circuit 200, and a display device 1000.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.

In addition, in the embodiments of the present application, the transistors used may be thin film transistors, field effect transistors, or other switching devices having the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is directly described as a second pole, so that the source and the drain of all or part of the transistors in the embodiments of the present disclosure may be interchanged as necessary.

In addition, the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors, and the embodiments of the present disclosure are all described by taking the P-type transistor as an example, that is, in the embodiments of the present disclosure, when the gate of the transistor receives a low level signal, the first pole and the second pole of the transistor are turned on. Based on the description and teaching of the P-type transistor implementation of the present disclosure, a person of ordinary skill in the art can easily conceive of an implementation in which the embodiments of the present disclosure employ an N-type transistor without making creative efforts, and therefore, such implementations are also within the protection scope of the present disclosure.

In general, in an EM GOA circuit (for example, 12T3C), the generation of an output signal is started after receiving an input signal for two unit time periods, and at the stage of starting the output signal, the threshold voltage Vth of some transistors in the EM GOA circuit is easily biased forward, so that the EM GOA circuit cannot normally output the signal in the process of outputting an EM (light emitting) signal to a pixel driving circuit.

In view of the above, referring to fig. 1, the present application provides a shift register 10, which includes an input sub-circuit 11, a first node N1, a second node N2, a third node N3, a first control sub-circuit 12, a second control sub-circuit 13, and an output sub-circuit 14.

The input sub-circuit 11 is connected to the first node N1, the second node N2, the first clock signal terminal CK, and the signal input terminal STV, and the input sub-circuit 11 is configured to control potentials of the first node N1 and the second node N2 according to an input signal transmitted from the signal input terminal STV and a first clock signal transmitted from the first clock signal terminal CK.

The first control sub-circuit 12 is connected to the first node N1, the second node N2, and the second clock signal terminal CB, and is configured to control the potential of the first node N1 according to the potential of the second node N2 and the second clock signal.

The second control sub-circuit 13 is connected to the first node N1, the second node N2, the third node N3, the second clock signal terminal CB, and the signal input terminal STV, and is configured to control the potential of the third node N3 according to the potential of the first node N1, the potential of the second node N2, the second clock signal of the second clock signal terminal CB, and the input signal of the signal input terminal STV.

The output sub-circuit 14 is connected to the first node N1, the third node N3, the first level terminal VGH, and the second level terminal VGL, and the output sub-circuit 14 is configured to output a first output signal according to the third node N3 or output a second output signal according to the potential of the first node N1. The period of the first clock signal and the second clock signal is two unit durations, and the shift register 10 outputs a first output signal after receiving the input signal less than or equal to one unit duration.

In the shift register 10 of the present application, by setting the input sub-circuit 11, the first control sub-circuit 12, the second control sub-circuit 13, and the output sub-circuit 14, the first output signal is output after the input sub-circuit 11 receives an input signal for less than or equal to one unit duration. This is done. The influence on the stability of the output signal caused by the positive bias of the threshold voltage Vth of the transistor in the shift register 10 after receiving the input signal for 2 unit time is avoided, so that the output sub-circuit 14 of the shift register 10 can normally output the first output signal.

Referring to fig. 3, in detail, the shift register 10 is respectively connected to the first clock signal terminal CK, the second clock signal terminal CB, the first level terminal VGH, the second level terminal VGL, the signal input terminal STV and the pixel driving circuit. The shift register 10 is used to supply a light emission signal to the pixel driving circuit. The first clock signal terminal CK is used for transmitting a first clock signal to the shift register 10. The second clock signal terminal CB is used to transmit a second clock signal to the shift register 10. The signal input terminal STV is used to transmit an input signal to the shift register 10. The first level terminal VGH is used to transmit a first level to the shift register 10, and the second level terminal VGL is used to transmit a second level to the shift register 10.

It should be noted that the input signal is a high level signal, the first output signal is a first level, and the second output signal is a second level. The first level is a high level signal, and the second level is a low level signal.

The first clock signal and the second clock signal comprise a high level signal and a low level signal, the clock period duration of the first clock signal and the clock period duration of the second clock signal are the same and are both 2 unit durations, and the high level signal duration is greater than the low level signal duration in one clock period. It should be noted that the unit time length refers to the time required for refreshing the pixels of each row. For example, in some examples, the shift register of the present application is used in an OLED display panel having a refresh rate of 90HZ, which includes 800 rows of pixels. The time for a row of pixels to refresh is 1 second divided by the refresh rate 90 divided by the number of rows 400, which equals 27.8 microseconds. That is, each unit time length is 27.8 microseconds.

The duration of the input signal is greater than the clock period of the first clock signal or the second clock signal, for example. The duration of the input signal is 3H, and one clock cycle is less than 3H. And the first clock signal and the second clock signal are 180 degrees out of phase.

The first and second clock signals may be high-level signals, and the first and second clock signals may be low-level signals.

The shift register 10 is explained below with specific circuit connections.

The shift register 10 includes an input sub-circuit 11, a first control sub-circuit 12, a second control sub-circuit 13, an output sub-circuit 14, a first node N1, a second node N2, and a third node N3.

The input sub-circuit 11 is implemented by connecting to the first node N1 and the second node N2 with the first control sub-circuit 12, the second control sub-circuit 13 and the output sub-circuit 14.

With further reference to fig. 3, the input sub-circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth node N4, and a fifth node N5. The first transistor T1 is connected to the second transistor T2 and the first node N1 through a fourth node N4, and the third transistor T3 is connected to the second transistor T2 and the second node N2 through a fifth node N5.

A first pole of the first transistor T1 is connected to the signal input terminal STV, a second pole of the first transistor T1 is connected to the fourth node N4, a gate of the first transistor T1 is connected to the first clock signal terminal CK, and the first transistor T1 is configured to transmit an input signal of the signal input terminal STV to the fourth node N4 according to the first clock signal of the first clock signal terminal CK to change potentials of the fourth node N4 and the first node N1 connected to the fourth node N4.

A first pole of the second transistor T2 is connected to the first clock signal terminal CK, a second pole of the second transistor T2 is connected to the fifth node N5, a gate of the second transistor T2 is connected to the fourth node N4, and the second transistor T2 is used to transmit the first clock signal of the first clock signal terminal CK to the fifth node N5 according to the potential of the fourth node N4.

A first pole of the third transistor T3 is connected to the second level terminal VGL, a second pole of the third transistor T3 is connected to the fifth node N5, and a gate of the third transistor T3 is connected to the first clock signal terminal CK. The third transistor T3 is for transmitting the second level of the second level terminal VGL to the fifth node N5 according to the first clock signal transmitted by the first clock signal terminal CK.

The first control sub-circuit 12 is connected to the input sub-circuit 11 and the output sub-circuit 14 by connecting to the first node N1 and the second node N2.

The first control sub-circuit 12 includes a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a sixth node N6. Wherein the first capacitor C1 is connected to the fourth transistor T4 and the fifth transistor T5 through the sixth node N6.

The first pole of the fourth transistor T4 is connected to the second clock signal terminal CB, the second pole of the fourth transistor T4 is connected to the sixth node N6, the gate of the fourth transistor T4 is connected to the first node N1, and the fourth transistor T4 is used to transmit the second clock signal of the second clock signal terminal CB to the sixth node N6 according to the potential of the first node N1.

A first pole of the fifth transistor T5 is connected to the first level terminal VGH, a second pole of the fifth transistor T5 is connected to the sixth node N6, and a gate of the fifth transistor T5 is connected to the fifth node N5, for writing the first level of the first level terminal VGH to the sixth node N6 according to the potential of the fifth node N5.

The first capacitor C1 connects the sixth node N6 and the first node N1. The first capacitor C1 is used for maintaining the potential of the first node N1 according to the potential of the sixth node N6.

The second control sub-circuit 13 comprises a first control unit 131 and a second control unit 132. The first control unit 131 connects the first node N1, the third node N3, and the first level terminal VGH. The second control unit 132 is connected to the second node N2, the third node N3, the signal input terminal STV, the second clock signal terminal CB, the first level terminal, and the VGH second level terminal VGL.

The first control unit 131 includes a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first level terminal VGH, a second pole of the sixth transistor T6 is connected to the third node N3, and a gate of the sixth transistor T6 is connected to the first node N1. The sixth transistor T6 is for writing the first level of the first level terminal VGH into the third node N3 according to the potential of the first node N1.

The second control unit 132 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a second capacitor C2, a third capacitor C3, and a seventh node N7. The eighth transistor T8 is connected to the seventh transistor T7 and the third capacitor C3 through a seventh node N7.

A first pole of the seventh transistor T7 is connected to the second clock signal terminal CB, a second pole of the seventh transistor T7 is connected to the seventh node N7, a gate of the seventh transistor T7 is connected to the signal input terminal STV, and the seventh transistor T7 is configured to write the second clock signal of the second clock signal terminal CB to the seventh node N7 according to an input signal of the signal input terminal STV.

The first pole of the eighth transistor T8 is connected to the ninth transistor T9, the second pole of the eighth transistor T8 is connected to the third node N3, the gate of the eighth transistor T8 is connected to the seventh node N7, and the eighth transistor T8 is used to write the second level transmitted by the ninth transistor T9 to the third node N3 according to the potential of the seventh node N7.

A first pole of the ninth transistor T9 is connected to the second level terminal VGL, a second pole of the ninth transistor T9 is connected to the first pole of the eighth transistor T8, and a gate of the ninth transistor T9 is connected to the second node N2. The ninth transistor T9 is for writing the second level of the second level terminal VGL into the first pole of the eighth transistor T8 according to the potential of the second node N2.

The second capacitor C2 is connected between the second clock signal terminal CB and the second node N2, and is used for maintaining the potential of the second node N2 according to the second clock signal of the second clock signal terminal CB.

The third capacitor C3 is connected between the first level terminal VGH and the seventh node N7, and the third capacitor C3 is used to maintain the potential of the seventh node N7.

The output sub-circuit 14 includes a tenth transistor T10, an eleventh transistor T11, and a signal output terminal OUT.

A first pole of the tenth transistor T10 is connected to the first level terminal VGH, a second pole of the tenth transistor T10 is connected to the signal output terminal OUT, and a gate of the tenth transistor T10 is connected to the third node N3. The tenth transistor T10 is for writing the first level (first output signal) of the first level terminal VGH into the signal output terminal OUT according to the potential of the third node N3.

A first pole of the eleventh transistor T11 is connected to the second level terminal VGL, a second pole of the eleventh transistor T11 is connected to the signal output terminal OUT, and a gate of the eleventh transistor T11 is connected to the first node N1. The eleventh transistor T11 is for writing the second level (second output signal) of the second level terminal VGL into the signal output terminal OUT according to the potential of the first node N1.

Referring to fig. 2 and 4, in some embodiments, the shift register 10 further includes an isolation sub-circuit 15, and the isolation sub-circuit 15 includes a twelfth transistor T12 and a thirteenth transistor T13.

A first pole of the twelfth transistor T12 is connected to the fourth node N4, a second pole of the twelfth transistor T12 is connected to the first node N1, and a gate of the twelfth transistor T12 is connected to the second level terminal VGL. The twelfth transistor T12 is used to isolate the first node N1 and the fourth node N4.

A first pole of the thirteenth transistor T13 is connected to the fifth node N5, a second pole of the twelfth transistor T12 is connected to the second node N2, and a gate of the thirteenth transistor T13 is connected to the second level terminal VGL. The thirteenth transistor T13 is used to isolate the fifth node N5 from the second node N2.

The working process of the shift register 10 of the present application includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6, a seventh stage t7, and an eighth stage t 8. In the working process of the shift register 10, the duration of the high level signal of the first clock signal and the second clock signal is greater than 1 unit duration, and the duration of the low level signal is less than or equal to one unit duration. The duration of the input signal is greater than the clock period of the second clock signal, and the second clock signal is at a low level when the signal input terminal STV starts to transmit the input signal. In addition, it should be noted that the fifth operation phase and the sixth operation phase can be cycled by prolonging the duration of the input signal.

The operation of the shift register 10 will be described with reference to the shift register 10 of fig. 3 and the timing chart of fig. 4.

In a first phase t1

The signal transmitted by the input signal terminal STV is a low level signal, the first clock signal of the first clock signal terminal CK is a low level signal, and the second clock signal of the second clock signal terminal is a high level signal.

The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on. The low level signal of the signal input terminal STV is written into the fourth node N4 and the first node N1 through the first transistor T1. The sixth transistor T6 and the eleventh transistor T11 are turned on. The second clock signal of the second clock signal terminal CB is a high level signal, and the eighth transistor T8 is turned off. The first level of the first level terminal VGH is written into the third node N3, the third node N3 is at a high level, and the tenth transistor T10 is turned off. Meanwhile, the second level of the second level terminal VGL is written to the signal output terminal OUT through the eleventh transistor T11, and the signal output terminal OUT outputs a low level.

In the second stage T2

The signal transmitted by the input signal terminal STV is a low level signal and is switched to a high level signal (input signal), the first clock signal of the first clock signal terminal CK is a high level signal, and the second clock signal of the second clock signal terminal CB is a low level signal.

When the signal transmitted from the input signal terminal STV is switched from the low level to the high level, the seventh transistor T7 is turned off, the second clock signal of the second clock signal terminal CB is written into the seventh node N7 before being turned off, the third node N7 is a low level signal, and the eighth transistor T8 is turned on.

The first clock signal of the first clock signal terminal CK is a high level signal, the first transistor T1 and the third transistor T3 are turned off, the first capacitor C1 maintains the potentials of the first node N1 and the fourth node N4, so that the potentials of the first node N1 and the fourth node N4 are kept at a low level, and the second transistor T2, the sixth transistor T6 and the eleventh transistor T11 are turned on. The first level of the first level terminal VGH is written to the third node N3 and the tenth transistor T10 is turned off. Meanwhile, the second level of the second level terminal VGL is written into the signal output terminal OUT through the eleventh transistor T11, and the signal output terminal OUT keeps outputting a low level.

At a third stage t3

The signal transmitted by the input signal terminal STV is a high level signal, the first clock signal of the first clock signal terminal CK is a low level signal, and the second clock signal of the second clock signal terminal CB is a high level signal.

The first transistor T1 and the third transistor T3 are turned on.

The high level signal transmitted from the input signal terminal STV is written into the first node N1, the fourth node N4, and the seventh transistor T7, and the second transistor T2, the sixth transistor T6, the seventh transistor T7, and the eleventh transistor T11 are turned off; the third capacitor C3 maintains the potential of the seventh node N7, the potential of the seventh node N7 is maintained at a low level, and the eighth transistor T8 is turned on.

The second level of the second level terminal VGL is written in the fifth node N5 and the second node N2, the ninth transistor T9 is turned on, and the second level of the second level terminal VGL is written in the third node N3 through the ninth transistor T9 and the eighth transistor T8. The potential of the third node N3 is low level, the tenth transistor T10 is turned on, the first level of the first level terminal VGH is written into the signal output terminal OUT through the tenth transistor T10, and the signal output terminal OUT outputs high level.

At a fourth stage t4

The signal transmitted by the input signal terminal STV is a high level signal (input signal), the first clock signal of the first clock signal terminal CK is a high level signal, and the second clock signal of the second clock signal terminal CB is a low level signal.

The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned off. The first capacitor C1 maintains the potentials of the first node N1 and the fourth node N4 such that the potentials of the first node N1 and the fourth node N4 maintain a high level, and the second transistor T2, the sixth transistor T6, and the eleventh transistor T11 are turned off. The second capacitor C2 pulls down the potential of the second node N2, the potential of the second node N2 is low, and the ninth transistor T9 is turned on. The third capacitor C3 maintains the potential of the seventh node N7, the eighth transistor T8 is turned on, the second level of the second level terminal VGL is written into the third node N3 through the ninth transistor T9 and the eighth transistor T8, the potential of the third node N3 is low level, the tenth transistor T10 is turned on, the first level of the first level terminal VGH is written into the signal output terminal OUT through the tenth transistor T10, and the signal output terminal OUT outputs high level.

It should be noted that, in this operation phase, the threshold voltage Vth of the second transistor T2 is easily biased forward, so that the first clock signal of the first clock signal terminal CK is written into the second node N2 through the second transistor T2, and further the ninth transistor T9 is turned off, and the first level of the first level terminal CK cannot be written into the third node N3 through the ninth transistor T9 and the eighth transistor T8. It is to be understood that, since the potential of the third node N3 is maintained at a low level during the third phase, even if the threshold voltage Vth of the second transistor T2 is positively biased during this phase, which causes the ninth transistor T9 to turn off, if the third node N3 can be maintained at a low level, the tenth transistor T10 is turned on, so that the signal output terminal OUT can normally output a high level. If the third node N3 is at a high level, so that the tenth transistor T10 is turned off, the signal output terminal OUT at this stage can maintain a high level since the signal output terminal OUT at the previous stage outputs a high level.

In a fifth stage t5

The first transistor T1 and the third transistor T3 are turned on, and the seventh transistor T7 is turned off. The high level signal transmitted from the input signal terminal STV is written into the fourth node N4 and the first node N1, and the second transistor T2, the sixth transistor T6, and the eleventh transistor T11 are turned off. The second level of the second level terminal VGL is written from the third transistor T3 to the fifth node N5 and the second node N2, the ninth transistor T9 is turned on, the third capacitor C3 maintains the potential of the seventh node N7 so that the potential of the seventh node N7 is kept at a low level, the eighth transistor T8 is turned on, the second level of the second level terminal VGL is written to the third node N3 through the ninth transistor T9 and the eighth transistor T8, the potential of the third node N3 is at a low level, the tenth transistor T10 is turned on, the first level of the first level terminal VGH is written to the signal output terminal OUT through the tenth transistor T10, and the signal output terminal OUT outputs a high level.

In a sixth phase t6

The signal transmitted by the input signal terminal STV is a high level signal, the first clock signal of the first clock signal terminal CK is a high level signal, and the second clock signal of the second clock signal terminal CB is a low level signal.

In the seventh stage t7

The signal transmitted by the input signal terminal STV is a low level signal, the first clock signal of the first clock signal terminal CK is a low level signal, and the second clock signal of the second clock signal terminal CB is a high level signal.

The first transistor T1, the third transistor T3, and the seventh transistor T7 are turned on. The low level signal of the signal input terminal STV is written into the fourth node N4 and the first node N1 through the first transistor T1. The second transistor T2, the sixth transistor T6, and the eleventh transistor T11 are turned on. The second clock signal of the second clock signal terminal CB is written into the seventh node N7 through the seventh transistor T7, the low node is at a high level, and the eighth transistor T8 is turned off. The first level of the first level terminal VGH is written into the third node N3 through the sixth transistor T6, the third node N3 is at a high level, and the tenth transistor T10 is turned off. Meanwhile, the second level of the second level terminal VGL is written to the signal output terminal OUT through the eleventh transistor T11, and the signal output terminal OUT outputs a low level.

In the eighth stage t8

The signal transmitted by the input signal terminal STV is a low level signal, the first clock signal of the first clock signal terminal CK is a high level signal, and the second clock signal of the second clock signal terminal CB is a low level signal.

The first transistor T1 and the third transistor T3 are turned off, and the seventh transistor T7 is turned on. The first capacitor C1 further pulls down the potentials of the first node N1 and the fourth node N4 so that the potentials of the first node N1 and the fourth node N4 maintain a low level, the second transistor T2, the sixth transistor T6, and the eleventh transistor T11 are turned on, the first level of the first level terminal VGH is written into the third node N3 through the sixth transistor T6, and the tenth transistor T10 is turned off. Meanwhile, since the first clock signal of the first clock signal terminal CK is a high level signal, the second node N2 maintains a high level, and the ninth transistor T9 is turned off. It should be noted that, in this stage, the fourth transistor T4 is turned on, the second clock signal is written into the sixth node N6, so that the sixth node N6 is at a low level, the first capacitor C1 makes the potential of the first node N1 lower, and the low level output by the eleventh transistor T11 is lower than the low level output by the seventh stage.

Referring to fig. 5, an embodiment of the present application further provides a control method for controlling the shift register 10 according to any one of the above embodiments, where the control method includes:

s12: providing an input signal to the shift register to control the shift register to output a first output signal after receiving the input signal for less than or equal to one unit duration; or

S14: and stopping providing the input signal to the shift register to control the shift register to output the second output signal after stopping receiving the input signal for less than or equal to one unit time length.

Please refer to fig. 6, the control method further includes:

s16: determining the low level duration time of the second clock signal as a low level signal;

s18: and when the second clock signal is a low level signal and lasts for a preset time length, the input end of the control signal transmits an input signal to the register, and the preset time length is less than the time length of the low level signal.

For example, the predetermined time period may be half of the low level signal in the second clock signal.

Referring to fig. 7, the present embodiment further provides a gate driving circuit 100, which includes a plurality of cascaded shift registers 10, and except for the first stage of shift register 10, a signal input terminal STV of the shift register 10 of the present stage is electrically connected to a signal output terminal OUT of the shift register 10 of the previous stage.

For example, referring to fig. 8, in some examples, the gate driving circuit 100 includes 4 cascaded shift registers 10, where the signal input terminals STV of the shift registers 10 in the first row are connected, the signal output terminal OUT serves as the signal input terminal of the shift register 10 in the second row, the signal output terminal of the shift register 10 in the second row serves as the signal input terminal of the shift register 10 in the third row, and the signal output terminal of the shift register 10 in the third row serves as the signal input terminal of the shift register 10 in the fourth row. Thus, after the first row shift register 10 receives the signal input terminal STV, the first row, the second row, the third row and the fourth row of shift registers 10 sequentially output high levels at intervals less than or equal to 1 unit duration.

With further reference to fig. 9, the present application also provides a display device 1000, which includes the pixel driving circuit 20 and the gate driving circuit 100 as described above. The gate driving circuit 100 is connected to the pixel driving circuit 200, and the gate driving circuit 100 is configured to transmit a gate control signal to the pixel driving circuit 200 after receiving an input signal.

The gate control signal is a high level signal output from the shift register 10 through the signal output terminal OUT.

The display device 1000 can be applied to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A shift register is characterized by comprising an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit;

2. The shift register of claim 1, wherein the second control sub-circuit comprises:

3. The shift register according to claim 2, wherein the first control unit includes a sixth transistor, a first pole of the sixth transistor is connected to the first level terminal, a second pole of the sixth transistor is connected to the third node, and a gate of the sixth transistor is connected to the first node.

4. The shift register according to claim 2, wherein the second control unit includes a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor, and a third capacitor; wherein,

5. The shift register of claim 1, wherein the first control sub-circuit includes a fourth transistor, a fifth transistor, and a first capacitance;

the first capacitor is connected with the first node and the sixth node.

6. The shift register of claim 1, wherein the output sub-circuit includes a tenth transistor, an eleventh transistor, and a signal output terminal;

7. The shift register of claim 1, wherein the input sub-circuit includes a first transistor, a second transistor, and a third transistor; wherein,

8. The shift register of claim 7, further comprising an isolation subcircuit, the isolation subcircuit including a twelfth transistor and a thirteenth transistor; wherein,

9. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 8 connected in cascade, wherein the shift register of the present stage except the first stage has a signal input terminal electrically connected to a signal output terminal of the shift register of the previous stage.

10. A display device comprising a pixel drive circuit and the gate drive circuit of claim 9, the gate drive circuit being connected to the pixel drive circuit to provide the pixel drive circuit with a gate control signal.

11. A control method of a shift register, for controlling the shift register according to any one of claims 1 to 8, the control method comprising:

12. The control method according to claim 11, characterized by further comprising: