CN116594929A - SARM type FPGA timing refresh and on-track reconstruction system and method - Google Patents

SARM type FPGA timing refresh and on-track reconstruction system and method Download PDF

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Publication number
CN116594929A
CN116594929A CN202310476427.8A CN202310476427A CN116594929A CN 116594929 A CN116594929 A CN 116594929A CN 202310476427 A CN202310476427 A CN 202310476427A CN 116594929 A CN116594929 A CN 116594929A
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China
Prior art keywords
fpga
interface
sarm
reconstruction
chip
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CN202310476427.8A
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Chinese (zh)
Inventor
甄凡凡
江波
叶冰心
徐雪莲
文义红
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CETC 32 Research Institute
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CETC 32 Research Institute
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Priority to CN202310476427.8A priority Critical patent/CN116594929A/en
Publication of CN116594929A publication Critical patent/CN116594929A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application provides a SARM type FPGA timing refreshing and on-orbit reconstruction system and method, wherein the main frequency of a processor is up to 1GHz; the memory chip adopts DDR3 and is mounted on a DDR memory controller of the processor, and the frequency is up to 800MHz. The working clock of the refreshing chip is 10MHz, and the interface FPGA is refreshed, reloaded and reconstructed at regular time; the interface FPGA is an SRAM type FPGA chip, and is communicated with the CPU by adopting a PCIE interface, and is communicated with the outside by adopting a rapidIO high-speed interface. The application realizes the timing refreshing function of the SRAM type FPAG with high performance; the refresh function of the SRAM type FPGA can refresh every 3min at regular time, so that the FPGA program is ensured not to frequently turn over in single event, the quick reconfiguration function is realized on the basis of ensuring the dynamic refresh function, and the requirement of the application function on the satellite is met.

Description

SARM type FPGA timing refresh and on-track reconstruction system and method
Technical Field
The present application relates to high performance FPGAs, and in particular, to SARM FPGA timing refresh and on-rail reconstruction systems and methods.
Background
The application on the satellite is more and more complex, and the requirements on the processing capacity are increasingly higher, so that the high-performance FPGA is more and more widely used. Most high-performance FPGAs are SRAM type, are easily irradiated by high-energy particles in the in-orbit process, and are subjected to single event upset, so that the accumulated faults of functions and tasks can be caused.
In the prior art, the current mainstream solution is triple modular redundancy plus timing refresh. Patent document CN202798645U discloses a triple modular redundancy circuit structure for radiation protection, in which the combination logic circuit and the sequential logic circuit of the circuit are duplicated into three parts, and voters are added after the three sequential logic circuits, so that each path of the circuit becomes three parts. In addition, voter is added in each path, and single particle faults are eliminated in each path by the structure formed by redundant paths and voter.
Aiming at the problem of on-orbit reconstruction of a FLASH chip, on one hand, the problem of single event upset easily occurs in a space environment, and on the other hand, the product function has the requirement of updating iteration in the use process.
Disclosure of Invention
In view of the shortcomings in the prior art, it is an object of the present application to provide a SARM-type FPGA timing refresh and on-rail reconstruction system and method.
According to the present application, there is provided a SARM type FPGA timing refresh and on-rail reconstruction system comprising: the device comprises a processing unit, a memory chip, a refreshing chip, an interface FPGA and a functional FPGA;
the main frequency of the processor is up to 1GHz, and the processor is provided with a DDR memory controller;
the memory chip adopts DDR3, is mounted on a DDR storage controller of the processor, has the capacity of 2GB, has the ECC (error correction and detection) checking function, and has the frequency of up to 800MHz;
the working clock of the refreshing chip is 10MHz, and the interface FPGA is refreshed, reloaded and reconstructed at regular time;
the interface FPGA is an SRAM type FPGA chip, and is communicated with the CPU by adopting a PCIE interface, and is communicated with the outside by adopting a rapidIO high-speed interface.
Preferably, a Local Bus interface is adopted between the function FPGA and the processor to carry out interconnection communication of the reconstruction data.
Preferably, a Select MAP interface is adopted between the function FPGA and the refreshing chip, and the interface FPGA is configured.
Preferably, the method further comprises: a NOR FLASH chip;
and two NOR FLASH chips are simultaneously mounted on the functional FPGA and used as main and standby configuration chips of the interface FPGA, and when the configuration of the main NOR FLASH chip fails, the main and standby configuration chips can be switched to the standby NOR FLASH chips for starting.
Preferably, the method further comprises: NAND FLASH memory;
the NAND FLASH memory is mounted on the function FPGA to realize a file system, and programs of different task functions of the interface FPGA can be stored.
Preferably, the program to be updated is transmitted to the interface FPGA through the rapidIO interface, is transmitted to the CPU of the processor through the PCIE interface and is uploaded to the DDR3 memory chip;
the processor CPU writes the program cached in the memory chip DDR3 into a file system through an instruction;
when the program needs to be updated, the CPU reads out the cache from the file system through the Local Bus interface and the memory chip DDR3 through different update instructions, and then writes the cache into the main NOR FLASH or the standby NOR FLASH through the function FPGA.
Preferably, in the path of reconstruction update, the RapidIO interface and the PCIE interface are high-speed interfaces, and the line rate is 2.5Gbps; the main frequency of the memory chip DDR3 is 400MHz, and the data rate is 800MHz x 64 bit=25 Gbps; the Local Bus interface clock is 125MHz, and the data rate is 125MHz with 16=2Gbps; the effective data rate of the file system is 4-6 MB/s.
According to the SARM type FPGA timing refreshing and on-track reconstruction method provided by the application, the SARM type FPGA timing refreshing and on-track reconstruction system is adopted to carry out SARM type FPGA timing refreshing and/or on-track reconstruction.
Preferably, the on-rail reconstruction is performed on the interface FPGA configuration program.
Preferably, the on-track reconstruction is a whole-chip interface FLASH reconstruction or an interface FLASH partition reconstruction.
Compared with the prior art, the application has the following beneficial effects:
1. the application realizes the timing refreshing function of the SRAM type FPAG with high performance; the refreshing function of the SRAM type FPGA can refresh every 3min at regular time, so that the FPGA program is ensured not to frequently turn over by single event.
2. The application realizes the quick reconstruction function on the basis of ensuring the dynamic refreshing function, can realize partial reconstruction, can improve the quick reconstruction technology of the FPGA program from about 40min to about 7min when using the serial port, can effectively improve one order of magnitude of reconstruction time, reduces the influence on the application function, and meets the requirement of the application function on the satellite.
3. According to the application, the reloading of the FPGA program can be used for main-standby switching, so that the reliability of the FPGA program in on-satellite operation is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a schematic diagram of the system of the present application.
Fig. 2 is a schematic diagram of a serial port reconstruction path of a refresh chip.
Fig. 3 is a schematic diagram of a fast reconstruction path.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
As shown in FIG. 1, FIG. 1 is a schematic diagram of the system components of the present application providing a SARM FPGA timing refresh and on-rail reconstruction system.
The application relates to a system based on an FPGA (V2) chip and an external high-speed interface, which comprises a hardware product and FPGA software, wherein the hardware part comprises a processing unit, a refreshing chip, an FPGA control unit and a storage unit, and the software part is mainly the FPGA control software.
The processor adopts a high-performance low-power-consumption processor, the main frequency can reach 1GHz at most, the memory chip adopts DDR3, the capacity of the memory chip is 2GB on the DDR memory controller of the mounted processor, the memory chip has ECC (error correction and detection) checking function, and the frequency can reach 800MHz at most.
The refreshing chip adopts the JFMRS01RH model of the complex denier microelectronics, the working clock is 10MHz, the timing refreshing, reloading and reconstructing functions of the FPGA (V7) are mainly realized, and the FPGA (V7) is 7 series FPGA. The function FPGA adopts a V2 series BQR V3000 and adopts a Local Bus interface with the processor to realize the interconnection communication of the reconstruction data; two NOR FLASH chips are simultaneously mounted on the function FPGA and used as a main configuration chip and a standby configuration chip of the interface FPGA (V7), and when the configuration of the main FLASH chip fails, the function FPGA can be switched to the standby FLASH chip for starting; a Select MAP interface is adopted between the function FPGA and the refreshing chip, so that the configuration function of the interface FPGA (V7) is realized; the NAND FLASH memory is mounted on the function FPGA, and programs of different task functions of the interface FPGA (V7) can be stored.
The SRAM type FPGA chip adopts 690T of V7 series, adopts PCIE interface communication with the CPU, and externally adopts RapidIO high-speed interface for communication.
The system components can breakthrough realize the rapid reconstruction of the configuration program of the interface FPGA (V7).
The present application will be described in more detail below.
As shown in fig. 2, fig. 2 is a schematic diagram of a serial port reconstruction path of a refresh chip. The conventional refresh chip-based reconstruction is realized through a serial port of the refresh chip, and the main FLASH or the standby FLASH is subjected to integral reconstruction through the serial port via the refresh chip, and the reconstruction path is shown in fig. 2. Taking an FPGA (V7690T) used in the module as an example, when the bit stream size is 229878496bit and the chip is injected through the serial port, the chip is erased first, the chip erasing time is about 256 s=4.27 min according to the characteristics of the selected chip, and the chip programming time is 229878496bit/115200 bit/s= 1995.47 s=33.26 min, so the total reconstruction time is 37.53min. The reconstruction time in the above mode is long, however, the startup time of the on-board equipment is short, generally about 10 minutes, and the reconstruction time requirement cannot be met.
As shown in fig. 3, fig. 3 is a schematic diagram of a fast reconstruction path. For the fast reconstruction technology, the program to be updated is transmitted to the FPGA (V7) through the rapidIO interface, is transmitted to the CPU through the PCIE interface and is uploaded to the memory chip DDR3 of the module. The CPU writes the program cached in DDR3 into the file system through an instruction, so that power-down cannot be lost. When the program needs to be updated, the CPU reads out the data from the file system through different update instructions and caches the data in DDR3 through a Local Bus interface, and writes the data into the main FLASH or the standby FLASH through the FPGA (V2), and the details are shown in FIG. 3.
In the whole updated path, the rapidIO interface and the PCIE interface are high-speed interfaces, and the line speed is 2.5Gbps; DDR3 has a primary frequency of 400MHz and a data rate of 800MHz x 64 bit=25 Gbps (effective data rate of about 1 Gbps); the Local Bus interface clock is 125MHz, and the data rate is 125MHz with 16=2Gbps; the effective data rate of the file system is 4-6 MB/s. Therefore, when the program is updated in the above manner, the bottleneck of the interface speed is that the Local Bus interface controls the rate of writing FLASH. As can be seen from the above, the chip erasing time is about 4.27min, the chip programming time is about 229878496bit/16bit 10 us=2.39 min, and the total program reconfiguration time is about 4.27min+2.39 min=6.66 min; the size of a single Flash sector is 128KB, the sector erasing time is 1s, the sector programming time is about 128 x 1024//16 x 10us = 0.081s, and therefore the single sector reconstruction time is about 1.081s; meets the demand of reconstruction time of the on-board equipment.
Therefore, the rapid reconstruction mode provided by the application can greatly shorten the reconstruction time and reduce the influence on the application function no matter the whole FLASH is reconstructed or the partition is reconstructed.
Furthermore, the application also provides a SARM type FPGA timing refreshing and on-track reconstruction method, which adopts the SARM type FPGA timing refreshing and on-track reconstruction system to carry out timing refreshing and on-track reconstruction on the FPGA.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.

Claims (10)

1. A SARM-type FPGA timing refresh and on-rail reconstruction system comprising: the device comprises a processing unit, a memory chip, a refreshing chip, an interface FPGA and a functional FPGA;
the main frequency of the processor is up to 1GHz, and the processor is provided with a DDR memory controller;
the memory chip adopts DDR3, is mounted on a DDR storage controller of the processor, has the capacity of 2GB, has the ECC (error correction and detection) checking function, and has the frequency of up to 800MHz;
the working clock of the refreshing chip is 10MHz, and the interface FPGA is refreshed, reloaded and reconstructed at regular time;
the interface FPGA is an SRAM type FPGA chip, and is communicated with the CPU by adopting a PCIE interface, and is communicated with the outside by adopting a rapidIO high-speed interface.
2. The SARM FPGA timing refresh and on-track reconstruction system of claim 1, wherein a Local Bus interface is used between the functional FPGA and the processor for interconnection communication of the reconstructed data.
3. The SARM FPGA timing refresh and on-rail reconfiguration system of claim 1, wherein a Select MAP interface is employed between the functional FPGA and the refresh chip to configure the interface FPGA.
4. The SARM FPGA timing refresh and on-rail reconstruction system of claim 1, further comprising: a NOR FLASH chip;
and two NOR FLASH chips are simultaneously mounted on the functional FPGA and used as main and standby configuration chips of the interface FPGA, and when the configuration of the main NOR FLASH chip fails, the main and standby configuration chips can be switched to the standby NOR FLASH chips for starting.
5. The SARM FPGA timing refresh and on-rail reconstruction system of claim 4, further comprising: NAND FLASH memory;
the NAND FLASH memory is mounted on the function FPGA to realize a file system, and programs of different task functions of the interface FPGA can be stored.
6. The SARM FPGA timing refresh and on-track reconfiguration system of claim 5, wherein the program to be updated is transferred to the interface FPGA through the RapidIO interface, and is transferred to the processor CPU through the PCIE interface and uploaded to the memory chip DDR 3;
the processor CPU writes the program cached in the memory chip DDR3 into a file system through an instruction;
when the program needs to be updated, the CPU reads out the cache from the file system through the Local Bus interface and the memory chip DDR3 through different update instructions, and then writes the cache into the main NOR FLASH or the standby NOR FLASH through the function FPGA.
7. The SARM FPGA timing refresh and on-track reconfiguration system of claim 6, wherein in the reconfiguration update path, the RapidIO interface and PCIE interface are high-speed interfaces with a line rate of 2.5Gbps; the main frequency of the memory chip DDR3 is 400MHz, and the data rate is 800MHz x 64 bit=25 Gbps; the Local Bus interface clock is 125MHz, and the data rate is 125MHz with 16=2Gbps; the effective data rate of the file system is 4-6 MB/s.
8. A method for timing refresh and on-track reconstruction of an SARM-type FPGA, characterized in that the method for timing refresh and/or on-track reconstruction of an SARM-type FPGA is performed using the system for timing refresh and on-track reconstruction of an SARM-type FPGA according to any one of claims 1 to 7.
9. The SARM FPGA timing refresh and on-rail reconstruction method of claim 8, wherein the on-rail reconstruction is performed on the interface FPGA configuration program.
10. The SARM FPGA timing refresh and on-track reconstruction method of claim 8, wherein the on-track reconstruction is a full-slice interface FLASH reconstruction or an interface FLASH partition reconstruction.
CN202310476427.8A 2023-04-27 2023-04-27 SARM type FPGA timing refresh and on-track reconstruction system and method Pending CN116594929A (en)

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