CN116594557A - Cyclic read-write control method and system for satellite-borne code stream data - Google Patents
Cyclic read-write control method and system for satellite-borne code stream data Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/061—Improving I/O performance
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0638—Organizing or formatting or addressing of data
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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Abstract
The application provides a circulating read-write control method and a system for satellite-borne code stream data, wherein the method comprises the following steps: 1) The cyclic read-write address pointer maintains a fixed safety interval; 2) When the cyclic write mode is in a write-stop state, the cyclic read address pointer may remain consistent with the cyclic write address pointer; 3) And after the circulation read-write task is finished, respectively storing the read-write breakpoint and the storage block state information. The application can effectively solve the problem of conflict of read-write address pointers of the satellite remote sensing code stream data recorded and played back by adopting a circulating read-write mode by taking the storage block as a storage unit, improves the timeliness of playing back the satellite-borne data, and realizes the integrity of the data transmission of the current task.
Description
Technical Field
The application relates to the technical field of information storage and transmission, in particular to a circulating read-write control method and system for satellite-borne code stream data.
Background
At present, the loading data storage mode of domestic satellites is mainly based on file forms and code stream data, and some mapping remote sensing satellites adopt the storage mode of the code stream data according to satellite loading tasks and application characteristics. The solid-state storage device is used with the storage block as an address unit, and a certain time overhead is required for the read-write access of the single storage block. In order to avoid the conflict of read-write pointers in the recording and playback processes of remote sensing data, the traditional design adopts the way that the read-write pointers are staggered by a certain address interval to provide protection, otherwise, the simultaneous read-write conflict of the same storage block can occur, and the data loss and the error code are caused. On the other hand, in the ground test and in-orbit use process, when the data of the secondary task cannot be completely downloaded in real time due to the existence of the address protection interval, the data needs to be read out in the next playback task, and the ground is spliced. Or the complete data is read in a mode of playback according to time-selective segments after the payload data is recorded. The method greatly reduces the effectiveness of on-orbit data transmission and application, and also adds an additional operation flow for ground data receiving and testing.
The comparison has disclosed the method: patent literature of a method for storing satellite remote sensing image data (CN 107066562 a) proposes a method for storing satellite remote sensing image data, which proposes that satellite remote sensing data is divided into layer files according to wave bands, then is divided into image blocks according to geographic coordinate characteristics of the data and is stored in a plurality of storage blocks, and a distributed storage scheme is adopted, so that the problem of large data volume single machine storage rate in a file form is mainly solved. The method adopts a storage block as a storage unit, but is not a distributed design mode, and mainly aims to solve the problems of cycle read-write time sequence conflict of code stream remote sensing data and the problems of code stream data playback integrity and timeliness.
The patent name of the patent is a method and a system for rapidly storing/reading code stream data (CN 104536700A) provides a method for analyzing and processing a code stream data packet, labeling the generated identifiable code stream packet to generate a marked code stream packet, establishing an address index for labeling the code stream packet with an offset when directly storing the marked code stream packet, and reducing the memory consumption of independent hardware of a system by labeling the code stream data format, but the effective data bit space is reduced due to the introduction of a label position. The method adopts an independent hardware storage unit PROM to store the circulating read-write address pointer and the recording time of the code stream data storage block.
The patent name of the patent is 'stream data storage control system and method' (CN 102968422A) discloses a system composed of a plurality of functional modules such as a RAID control module, a logical volume management module, a stream data access interface module, a time index and space management module, a host interface driving module and the like, and the connection relation among the modules and the specific functions and workflow of each functional module are provided. The method maps the storage space into a plurality of RAID spaces, divides the RAID spaces into a plurality of logic volumes, and provides a storage interface for accessing stream data and time indexes to improve the data reading and writing efficiency.
According to the published document, a circulating read-write time sequence design method of code stream type remote sensing data is not found, and the problems of the playback integrity and timeliness of the code stream data are not solved.
At present, a method for controlling cyclic read-write of code stream remote sensing data is not yet seen, so a new technical scheme is required to be provided to improve the technical problems.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide a circulating read-write control method and system for satellite-borne code stream data.
The application provides a cyclic read-write control method for satellite-borne code stream data, which comprises the following steps:
step S1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
step S2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
step S3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
step S4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
step S5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
Preferably, the read address pointer and the write address pointer of the memory module in the cyclic read-write mode are all connected end to end, and the read address pointer and the write address pointer start from an initial value of 0 after overflowing.
Preferably, the memory module in the cyclic read-write mode uses a memory block as an address unit, and the memory block expands the capacity by adjusting the memory depth and the bit width.
Preferably, when performing a circular write operation, the next non-free address is sequentially queried from the current write address pointer for an autonomous circular erase operation, one memory block at a time being erased and marked as free.
Preferably, the memory block status information includes a read, unread, free status of the memory block and a recording time of the memory block data.
The application also provides a circulating read-write control system of the satellite-borne code stream data, which comprises the following modules:
module M1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
module M2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
module M3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
module M4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
module M5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
Preferably, the read address pointer and the write address pointer of the memory module in the cyclic read-write mode are all connected end to end, and the read address pointer and the write address pointer start from an initial value of 0 after overflowing.
Preferably, the memory module in the cyclic read-write mode uses a memory block as an address unit, and the memory block expands the capacity by adjusting the memory depth and the bit width.
Preferably, when performing a circular write operation, the next non-free address is sequentially queried from the current write address pointer for an autonomous circular erase operation, one memory block at a time being erased and marked as free.
Preferably, the memory block status information includes a read, unread, free status of the memory block and a recording time of the memory block data.
Compared with the prior art, the application has the following beneficial effects:
1. the application can effectively solve the problem of conflict of read-write address pointers of the satellite remote sensing code stream data recorded and played back by adopting a circulating read-write mode by taking the storage block as a storage unit, improves the timeliness of playing back the satellite-borne data, and realizes the integrity of the data transmission of the current task;
2. according to the application, the cyclic read-write state is set and triggered under different conditions, and the autonomous transfer of the cyclic read-write state can avoid time sequence conflict of cyclic read-write data, and can ensure timeliness and completeness of cyclic playback of the current remote sensing data, and the erasure and state information storage of the storage block are all completed autonomously.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a cyclic read state transition diagram of the present application;
FIG. 2 is a cyclic write state transition diagram of the present application;
FIG. 3 is a schematic diagram of the FAT table structure of the memory module according to the present application;
fig. 4 is a schematic block diagram of a memory module according to the present application.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
Example 1:
the application provides a cyclic read-write control method for satellite-borne code stream data, which comprises the following steps:
step S1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
step S2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
step S3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
step S4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
step S5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
The read address pointer and the write address pointer of the memory module in the cyclic read-write mode are connected end to end, and the read address pointer and the write address pointer start from an initial value 0 after overflowing.
The memory module in the cyclic read-write mode takes a memory block as an address unit, and the memory block expands the capacity by adjusting the memory depth and the bit width.
And when the cyclic write operation is performed, sequentially inquiring the next non-idle address from the current write address pointer to perform autonomous cyclic erase operation, and erasing one memory block at a time and marking the memory block as an idle state.
The memory block state information includes the read, unread, free state of the memory block and the recording time of the memory block data.
Example 2:
example 2 is a preferable example of example 1 to more specifically explain the present application.
The application also provides a circulating read-write control system of the satellite-borne code stream data, which comprises the following modules:
module M1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
module M2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
module M3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
module M4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
module M5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
The read address pointer and the write address pointer of the memory module in the cyclic read-write mode are connected end to end, and the read address pointer and the write address pointer start from an initial value 0 after overflowing.
The memory module in the cyclic read-write mode takes a memory block as an address unit, and the memory block expands the capacity by adjusting the memory depth and the bit width.
And when the cyclic write operation is performed, sequentially inquiring the next non-idle address from the current write address pointer to perform autonomous cyclic erase operation, and erasing one memory block at a time and marking the memory block as an idle state.
The memory block state information includes the read, unread, free state of the memory block and the recording time of the memory block data.
Example 3:
example 3 is a preferable example of example 1 to more specifically explain the present application.
Aiming at the defects of the prior art, the application aims to provide a cyclic read-write control method for satellite-borne code stream data, which effectively solves the problems of time sequence control and timeliness of cyclic read-write of satellite remote sensing data by adopting a code stream mode.
The application provides a circulating read-write control method of satellite-borne code stream data, which comprises the following steps:
step 1: when receiving the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states.
Step 2: when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state from the read enabling state, and in the read waiting state, the data playback function pauses, and the cyclic write enables the write address to be continuously accumulated in the enabling state. When the read-write address pointer interval is not smaller than 2 address bits again, the cyclic read mode automatically enters a read enabling state from a read waiting state, and the state transition diagram of cyclic read is shown in fig. 1.
Step 3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as the next writable address, the cyclic write operation is started from the write breakpoint only when the write enabling instruction is received again, and only when the write mode is in the write stop state, the read address pointer can catch up and be consistent with the write address pointer. The state transition diagram of the cyclic writing is shown in fig. 2.
Step 4: when a read-stop instruction is received or the read address pointer is consistent with the write address pointer, after the current address operation is to be read, the cyclic read mode enters a read-stop state, the read breakpoint is saved as the next unread address, the read-stop state needs to receive the read instruction again to enter a read enabling state, and when the read enabling instruction is received again, the cyclic read operation is started from the read breakpoint.
Step 5: when the circulation read-write mode is finished, the address pointer of the circulation read-write breakpoint and the storage block state information are stored on the independent external storage chip.
Preferably, in the method for controlling cyclic read-write of satellite-borne code stream data, the read-write address pointers of the memory module for cyclic read-write are all connected end to end, and the read-write address pointer starts from an initial value of 0 if overflowed.
Preferably, in the method for controlling cyclic read-write of satellite-borne code stream data, the memory module for cyclic read-write uses the memory block as an address unit, and the memory block can perform capacity expansion by adjusting the memory depth and bit width.
Preferably, in the method for controlling cyclic read-write of satellite-borne code stream data, when writing operation is performed, the FAT table information of the next non-idle address is sequentially queried from the current write address pointer to perform autonomous cyclic erase operation, and each time, one memory block is erased and marked as an idle state.
The memory block state information includes the read, unread, free state of the memory block and the recording time of the memory block data. The memory module adopts FAT table form to establish corresponding relation with memory logic address. The data block information bit width of each address storage is 32 bits, wherein the upper 24 bits identify words, and the lower 8 bits are EDAC check bits. When the identification word value of the Bit24-Bit1 is all 1, the bad block area of the storage space represented by the address is represented, and the storage space can not be used. When the Bit24-Bit1 identification word value is all 0, the storage space represented by the address is represented as a free area, and the storage space is used for new data recording. When the current address recording operation is completed, the FAT table bit24-bit23 is identified as 00 representing unread, and bit22-bi1 is allocated as a recording time code. Fig. 3 is a schematic diagram of a FAT table of a memory module, and the total number of addresses in the address space is 4096 in this embodiment.
The design of the storage module takes generalization, modularization and reliability as design guiding principles. The storage module consists of a plurality of storage sub-modules, and each group of storage sub-modules consists of a control unit, a storage unit and a cascade device and are completely independent from each other. The control unit mainly completes various bottom layer time sequence control and error correction coding and decoding of the storage unit; the storage unit is formed by cascading 9 FLASH chips which are three-dimensionally packaged by a 3Dplus company with 128Gb in parallel, wherein 8 chips are used as data storage and 1 chip is used as verification. The cascade switch sets the cascade relation of the storage sub-modules, and can expand the depth or bit width of the storage block, thereby realizing the expansion of the storage capacity and the storage speed. A block diagram of the memory module design is shown in fig. 4.
The present embodiment will be understood by those skilled in the art as more specific descriptions of embodiment 1 and embodiment 2.
Those skilled in the art will appreciate that the application provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the application can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.
Claims (10)
1. The method for controlling the cyclic read-write of the satellite-borne code stream data is characterized by comprising the following steps:
step S1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
step S2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
step S3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
step S4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
step S5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
2. The method for controlling cyclic read-write of satellite-borne code stream data according to claim 1, wherein the storage module in the cyclic read-write mode has a read address pointer and a write address pointer both connected end to end, and the read address pointer and the write address pointer start from an initial value of 0 after overflowing.
3. The method for controlling cyclic read-write of satellite-borne code stream data according to claim 1, wherein the memory module in the cyclic read-write mode uses a memory block as an address unit, and the memory block performs capacity expansion by adjusting a memory depth and a bit width.
4. The cyclic read-write control method of on-board code stream data according to claim 1, wherein when cyclic write operation is performed, the next non-free address is sequentially queried from the current write address pointer to perform autonomous cyclic erase operation, and each time a memory block is erased and marked as a free state.
5. The method according to claim 1, wherein the memory block status information includes a read, unread, free status of the memory block and a recording time of the memory block data.
6. The circulating read-write control system for the satellite-borne code stream data is characterized by comprising the following modules:
module M1: when the satellite receives the reading enabling instruction and the writing enabling instruction, respectively setting a cyclic reading mode and a cyclic writing mode as enabling states;
module M2: in the write enabling state, when the interval between the read pointer and the write pointer is equal to 1 address bit, the cyclic read mode enters a read waiting state, and when the interval between the read address pointer and the write pointer is not less than 2 address bits, the cyclic read mode automatically enters the read enabling state from the read waiting state;
module M3: when the cyclic write mode receives a write stop instruction in a write enabling state, after the current address operation is finished, the cyclic write mode enters a write stop state, a write breakpoint is saved as a next writable address, when the write enabling instruction is received again, cyclic write operation is performed from the write breakpoint, and only when the write mode is in the write stop state, the read address pointer can be consistent with the write address pointer;
module M4: when a read-stop instruction is received or a read address pointer is consistent with a write address pointer, after the current address operation is to be read, a cyclic read mode enters a read-stop state, a read breakpoint is saved as the next unread address, the read-stop state can enter a read enabling state only by receiving the read instruction again, and when the read enabling instruction is received again, cyclic read operation is started from the read breakpoint;
module M5: and after the circulation read-write mode is finished, saving the address pointer and the storage block state information of the circulation read-write breakpoint.
7. The cyclic read-write control system of on-board code stream data according to claim 6, wherein the memory module in the cyclic read-write mode has a read address pointer and a write address pointer both connected end to end, and the read address pointer and the write address pointer start from an initial 0 value after overflowing.
8. The cyclic read-write control system of the satellite-borne code stream data according to claim 6, wherein the memory module in the cyclic read-write mode uses a memory block as an address unit, and the memory block performs capacity expansion by adjusting a memory depth and a bit width.
9. The cyclic read-write control system of on-board code stream data according to claim 6, wherein when cyclic write operation is performed, the next non-free address is sequentially queried from the current write address pointer to perform autonomous cyclic erase operation, and each time a memory block is erased and marked as free.
10. The system of claim 6, wherein the memory block status information includes a read, unread, idle status of a memory block and a recording time of the memory block data.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310443728.0A CN116594557A (en) | 2023-04-23 | 2023-04-23 | Cyclic read-write control method and system for satellite-borne code stream data |
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