CN115268765A - Nandflash autonomous bad block management method and system based on FPGA - Google Patents

Nandflash autonomous bad block management method and system based on FPGA Download PDF

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Publication number
CN115268765A
CN115268765A CN202210666041.9A CN202210666041A CN115268765A CN 115268765 A CN115268765 A CN 115268765A CN 202210666041 A CN202210666041 A CN 202210666041A CN 115268765 A CN115268765 A CN 115268765A
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bad block
nandflash
block
index number
fpga
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李斌
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CETC 32 Research Institute
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a Nandflash autonomous bad block management method and a system based on FPGA, comprising the following steps: step 1: when the chip leaves the factory, carrying out factory retrieval on bad blocks; step 2: maintaining the bad block information; and 3, step 3: carrying out block address mapping; and 4, step 4: and carrying out mutual exclusion scheduling on the Nandflash interface. The invention moves the bad block management into the FPGA to realize the bad block management, thereby not only reducing the load of the CPU and leading the CPU to better complete the tasks of other system levels, but also fully utilizing the advantages of the FPGA such as quick response and parallel processing, and efficiently and reliably completing the storage and playback functions of the Nandflash.

Description

Nandflash autonomous bad block management method and system based on FPGA
Technical Field
The invention relates to the technical field of bad block management, in particular to a Nandflash autonomous bad block management method and system based on an FPGA.
Background
The common CPU and FPGA of the on-board computer are used as core architectures to jointly complete the functions of on-board storage, control and the like. In the conventional functional framework, nandflash is used as a storage device, interface logic control such as erasing, reading and writing is completed by an FPGA, and a CPU (central processing unit) completes control of stored data and reliability control (redundancy design or bad block management) of the Nandflash.
Patent document CN104765695A (application number: CN 201510158107.3) discloses a NAND FLASH bad block management system, which comprises a NAND FLASH interface control unit, a bad block management unit, a nonvolatile memory interface control unit and a nonvolatile memory, wherein the NAND FLASH interface control unit is connected with a NAND FLASH array, the NAND FLASH interface control unit is connected with the bad block management unit, and the bad block management unit is connected with the nonvolatile memory through the nonvolatile memory interface control unit. The non-volatile memory is an EEPROM. The bad block management unit is based on an FPGA.
Along with the increasing and more complex function requirements on the satellite and the increasing and more heavy workload of the CPU, bad block management is moved to the FPGA to achieve, the load of the CPU is reduced, the CPU can well complete tasks of other system levels, the advantages of fast response and parallel processing of the FPGA are fully utilized, and the storage and playback functions of the Nandflash are efficiently and reliably completed. The invention solves the specific problem of how to realize the functions of factory retrieval of bad blocks, bad block information maintenance, block address dynamic mapping and the like in an FPGA by using the on-satellite Nandflash.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a Nandflash autonomous bad block management method and system based on an FPGA.
The Nandflash autonomous bad block management method based on the FPGA provided by the invention comprises the following steps:
step 1: when the chip leaves the factory, carrying out factory retrieval on bad blocks;
and 2, step: maintaining bad block information;
and 3, step 3: carrying out block address mapping;
and 4, step 4: and carrying out mutual exclusion scheduling on the Nandflash interface.
Preferably, the step 1 comprises:
marking the first page of each bad block, wherein the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF;
after chip initialization and before erasing programming, traversing and retrieving all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into the non-bad block 0.
Preferably, the step 2 comprises:
step 2.1: opening up a BLOCK RAM space for caching and updating bad BLOCK list information, and moving the bad BLOCK index number in BLOCK0 to a random access memory RAM for use in address mapping;
step 2.2: in the process of solid memory operation, state reading is carried out after erasing or page programming, when a read-out state word bit0 is 1 according to a device manual, the operation is failed, a new bad block is considered to exist, 0x00 is written into a first page Byte4096 of the block according to a chip factory mode to serve as a mark of bad block information, the bad block is traversed again after the mark is completed, and the bad block information in the block0 is updated.
Preferably, the step 3 comprises: storing information of bad block index numbers in a Block RAM according to addresses from low to high, initializing the RAM and filling all 1 data, reading data from 0 according to the addresses when a module works, comparing the original block index numbers with the original block index numbers, adding 1 to a read address if the data output Dout of the RAM is greater than or equal to the original block index numbers, continuing circular comparison, stopping circular comparison until the data output Dout is less than the original block index numbers, and finally mapping the index numbers to be the original block index numbers plus the read address of the RAM plus 1.
Preferably, the step 4 comprises:
step 4.1: setting channel number polling through an FPGA (field programmable gate array), and receiving an access request;
and 4.2: when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use permission;
step 4.3: and when the Nandflash operation is completed, releasing the use permission of the current channel.
The Nandflash autonomous bad block management system based on the FPGA provided by the invention comprises:
a module M1: when the chip leaves the factory, carrying out factory retrieval on the bad block;
a module M2: maintaining the bad block information;
a module M3: carrying out block address mapping;
a module M4: and carrying out mutual exclusion scheduling on the Nandflash interface.
Preferably, the module M1 comprises:
marking the first page of each bad block, wherein the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF;
after chip initialization and before erasing programming, traversing and retrieving all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into the non-bad block 0.
Preferably, the module M2 comprises:
module M2.1: opening up a BLOCK RAM space for caching and updating bad BLOCK list information, and moving the bad BLOCK index number in BLOCK0 to a random access memory RAM for use in address mapping;
module M2.2: in the process of the solid storage operation, state reading is carried out after erasing or page programming, when a read-out state word bit0 is 1 according to a device manual, the operation is failed, a new bad block is considered to be added, 0x00 is written into the first page Byte4096 of the block according to a mode of leaving a factory of a chip and is used as a mark of bad block information, the bad block is traversed again after the mark is finished, and the bad block information in the block0 is updated.
Preferably, the module M3 comprises: storing the information of the bad block index number in a Block RAM from low to high according to the address, initializing the RAM and filling all 1 data, reading data from 0 according to the address when the module works, comparing the original block index number with the original block index number, adding 1 to the read address if the data output Dout of the RAM is greater than or equal to the original block index number, continuing circular comparison, stopping circular comparison until the data output Dout is less than the original block index number, and finally mapping the index number which is the original block index number plus 1 to the read address of the RAM.
Preferably, the module M4 comprises:
module M4.1: setting channel number polling through an FPGA (field programmable gate array), and receiving an access request;
module M4.2: when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use authority;
module M4.3: and when the Nandflash operation is completed, releasing the use permission of the current channel.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention moves the bad block management to FPGA to realize, not only reduces the load of CPU to make it better complete other system-level tasks, but also fully utilizes the advantages of FPGA quick response and parallel processing to efficiently and reliably complete the Nandflash memory playback function;
(2) The method solves the specific problem of how to realize the functions of factory retrieval of bad blocks, bad block information maintenance, block address dynamic mapping and the like in the FPGA by using the satellite Nandflash.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a flow chart of the operation of the present invention;
fig. 2 is a block address mapping operation diagram.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example (b):
the invention not only realizes basic interface time sequences of Nandflash (Nand flash memory, one kind of flash memory) such as initialization, erasing, page programming, page reading, but also completes bad block management and related functions:
(1) Carrying out factory retrieval on the bad blocks;
(2) Bad block information maintenance;
(3) Mapping block addresses;
(4) And mutually exclusive scheduling of the Nandflash interface.
The work flow diagram of the invention is shown in figure 1, and the specific method of the invention comprises the following steps:
1. bad block traversal search (BBCHK);
taking MT29F8G08 as an example, when a chip leaves a factory, the first page of each bad block is marked, the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF.
After chip initialization and before erasing programming, traversing and searching all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into block0, because block0 cannot be a bad block.
2. And (3) bad block information maintenance:
(1) UPDATE bad block list (UPDATE);
the FPGA will open up a BLOCK RAM space for caching bad BLOCK list information. The purpose of updating the bad block list is to move the bad block index number in block0 into random access memory RAM for later use in address mapping.
(2) Bad MARK (MARK);
in the process of the solid memory operation, a step of reading the state is followed after erasing or page programming, when a read-out state word bit0 is '1' according to a device manual, the operation is failed, a new bad block is considered, and 0x00 is written into a first page Byte4096 of the block as a mark of bad block information according to a similar mode of chip factory shipment. And traversing the bad blocks again after the marking is finished, and updating the bad block information in the block 0.
3. Block address mapping (blockman);
the purpose of the block address mapping is to bypass bad blocks and provide an available block index number for subsequent solid-state operations. The module operates according to the principle shown in figure 2.
The information of bad block index numbers is stored in a Block RAM from low to high according to addresses, the RAM is initialized and filled with all '1' data, when a module works, data are read out from 0 according to the addresses, namely the index number of a first bad block, the index number of an original block is compared with the data, if the data output Dout of the RAM is larger than or equal to the data output Dout of the RAM, a read address is added with 1, namely the index number of a second bad block is read out, circular comparison is continued until the read address is smaller than Dout, circulation is stopped, and finally the mapped index number is the sum of the original block index number and the read address of the RAM plus +1.
For example, if the RAM stores two bad block index numbers 6 and 10, then if the access block index number is 3, the index number becomes 4 after mapping by this module, because block0 is used to store the bad block information, and the index number is increased by 1;
if the access chunk index is 7, then the index becomes 9 after the module mapping.
4. Mutually exclusive scheduling of the Nandflash interface;
in order to meet the requirement that a plurality of channels access the Nandflash, exclusive scheduling needs to be performed on an access interface of the Nandflash, for example, a virtual channel 8 is set, so that 8 users can simultaneously access and use the Nandflash, and the scheduling of the channels is completed through time-sharing exclusive.
(1) Access request (CHN _ REQ);
the FPGA sets channel number polling and can receive access requests.
(2) Access acknowledgement (CHN _ ACK);
and when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use permission.
(3) Access switching (CHN _ SW);
and when the Nandflash operation is completed, releasing the use permission of the current channel.
The Nandflash autonomous bad block management system based on the FPGA provided by the invention comprises: a module M1: when the chip leaves the factory, carrying out factory retrieval on bad blocks; a module M2: maintaining the bad block information; a module M3: carrying out block address mapping; a module M4: and carrying out exclusive scheduling on the Nandflash interface.
The module M1 comprises: marking the first page of each bad block, wherein the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF; after chip initialization and before erasing programming, traversing and retrieving all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into the non-bad block 0. The module M2 comprises: module M2.1: opening up a BLOCK RAM space for caching and updating bad BLOCK list information, and moving the bad BLOCK index number in BLOCK0 to a random access memory RAM for use in address mapping; module M2.2: in the process of solid memory operation, state reading is carried out after erasing or page programming, when a read-out state word bit0 is 1 according to a device manual, the operation is failed, a new bad block is considered to exist, 0x00 is written into a first page Byte4096 of the block according to a chip factory mode to serve as a mark of bad block information, the bad block is traversed again after the mark is completed, and the bad block information in the block0 is updated. The module M3 comprises: storing the information of the bad block index number in a Block RAM from low to high according to the address, initializing the RAM and filling all 1 data, reading data from 0 according to the address when the module works, comparing the original block index number with the original block index number, adding 1 to the read address if the data output Dout of the RAM is greater than or equal to the original block index number, continuing circular comparison, stopping circular comparison until the data output Dout is less than the original block index number, and finally mapping the index number which is the original block index number plus 1 to the read address of the RAM. The module M4 comprises: module M4.1: setting channel number polling through an FPGA (field programmable gate array), and receiving an access request; module M4.2: when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use authority; module M4.3: and when the Nandflash operation is completed, releasing the use permission of the current channel.
It is known to those skilled in the art that, in addition to implementing the system, apparatus and its various modules provided by the present invention in pure computer readable program code, the system, apparatus and its various modules provided by the present invention can be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like by completely programming the method steps. Therefore, the system, the apparatus, and the modules thereof provided by the present invention may be considered as a hardware component, and the modules included in the system, the apparatus, and the modules for implementing various programs may also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims (10)

1. A Nandflash autonomous bad block management method based on FPGA is characterized by comprising the following steps:
step 1: when the chip leaves the factory, carrying out factory retrieval on the bad block;
step 2: maintaining the bad block information;
and step 3: carrying out block address mapping;
and 4, step 4: and carrying out mutual exclusion scheduling on the Nandflash interface.
2. The FPGA-based Nandflash autonomous bad block management method according to claim 1, wherein the step 1 comprises:
marking the first page of each bad block, wherein the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF;
after chip initialization and before erasing programming, performing traversal retrieval on all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into the non-bad block 0.
3. The FPGA-based Nandflash autonomous bad block management method according to claim 2, wherein the step 2 comprises:
step 2.1: opening a BLOCK RAM space for caching and updating bad BLOCK list information, and moving a bad BLOCK index number in BLOCK0 to a random access memory RAM for use in address mapping;
step 2.2: in the process of solid memory operation, state reading is carried out after erasing or page programming, when a read-out state word bit0 is 1 according to a device manual, the operation is failed, a new bad block is considered to exist, 0x00 is written into a first page Byte4096 of the block according to a chip factory mode to serve as a mark of bad block information, the bad block is traversed again after the mark is completed, and the bad block information in the block0 is updated.
4. The FPGA-based Nandflash autonomous bad block management method according to claim 3, wherein the step 3 comprises: storing the information of the bad block index number in a Block RAM from low to high according to the address, initializing the RAM and filling all 1 data, reading data from 0 according to the address when the module works, comparing the original block index number with the original block index number, adding 1 to the read address if the data output Dout of the RAM is greater than or equal to the original block index number, continuing circular comparison, stopping circular comparison until the data output Dout is less than the original block index number, and finally mapping the index number which is the original block index number plus 1 to the read address of the RAM.
5. The FPGA-based Nandflash autonomous bad block management method according to claim 1, wherein the step 4 comprises:
step 4.1: setting channel number polling through an FPGA (field programmable gate array), and receiving an access request;
and 4.2: when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use permission;
step 4.3: and when the Nandflash operation is completed, releasing the use permission of the current channel.
6. The Nandflash autonomous bad block management system based on the FPGA is characterized by comprising the following steps:
a module M1: when the chip leaves the factory, carrying out factory retrieval on the bad block;
a module M2: maintaining the bad block information;
a module M3: carrying out block address mapping;
a module M4: and carrying out mutual exclusion scheduling on the Nandflash interface.
7. The FPGA-based Nandflash autonomous bad block management system according to claim 6, wherein the module M1 comprises:
marking the first page of each bad block, wherein the marking position is Byte4096, the marking value is 0x00, and the normal value is 0xFF;
after chip initialization and before erasing programming, performing traversal retrieval on all blocks of the Nandflash; and storing the retrieved block index number information corresponding to 0x00 into the non-bad block 0.
8. The FPGA-based Nandflash autonomous bad block management system of claim 7, wherein the module M2 comprises:
module M2.1: opening a BLOCK RAM space for caching and updating bad BLOCK list information, and moving a bad BLOCK index number in BLOCK0 to a random access memory RAM for use in address mapping;
module M2.2: in the process of solid memory operation, state reading is carried out after erasing or page programming, when a read-out state word bit0 is 1 according to a device manual, the operation is failed, a new bad block is considered to exist, 0x00 is written into a first page Byte4096 of the block according to a chip factory mode to serve as a mark of bad block information, the bad block is traversed again after the mark is completed, and the bad block information in the block0 is updated.
9. The FPGA-based Nandflash autonomous bad block management system of claim 8, wherein said module M3 comprises: storing the information of the bad block index number in a Block RAM from low to high according to the address, initializing the RAM and filling all 1 data, reading data from 0 according to the address when the module works, comparing the original block index number with the original block index number, adding 1 to the read address if the data output Dout of the RAM is greater than or equal to the original block index number, continuing circular comparison, stopping circular comparison until the data output Dout is less than the original block index number, and finally mapping the index number which is the original block index number plus 1 to the read address of the RAM.
10. The FPGA-based Nandflash autonomous bad block management system of claim 6, wherein the module M4 comprises:
module M4.1: setting channel number polling through an FPGA (field programmable gate array), and receiving an access request;
module M4.2: when the current channel is idle, responding to the access request and giving an access response, wherein the channel occupies the Nandflash use permission;
module M4.3: and when the Nandflash operation is completed, releasing the use permission of the current channel.
CN202210666041.9A 2022-06-14 2022-06-14 Nandflash autonomous bad block management method and system based on FPGA Pending CN115268765A (en)

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