CN116578150A - Linear voltage stabilizer - Google Patents

Linear voltage stabilizer Download PDF

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Publication number
CN116578150A
CN116578150A CN202310433208.1A CN202310433208A CN116578150A CN 116578150 A CN116578150 A CN 116578150A CN 202310433208 A CN202310433208 A CN 202310433208A CN 116578150 A CN116578150 A CN 116578150A
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CN
China
Prior art keywords
voltage
node
unit
linear voltage
signal
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CN202310433208.1A
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Chinese (zh)
Inventor
俞向荣
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Wuxi Aiwei Integrated Circuit Technology Co ltd
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Wuxi Aiwei Integrated Circuit Technology Co ltd
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Priority to CN202310433208.1A priority Critical patent/CN116578150A/en
Publication of CN116578150A publication Critical patent/CN116578150A/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application relates to the field of integrated circuit design, and discloses a linear voltage stabilizer, which comprises: the soft start module is used for outputting an adjusting signal; the error amplifying module is connected with the soft start module and is used for adjusting the output voltage of the linear voltage stabilizer according to the adjusting signal; the logic control module is respectively connected with the soft start module and the error amplification module and is used for controlling the state of the soft start module according to the output voltage of the linear voltage stabilizer; when the regulating signal is a level signal which is gradually boosted, the output voltage of the linear voltage stabilizer is gradually risen, and when the output voltage of the linear voltage stabilizer is higher than the first reference voltage, the logic control module controls the soft start module to stop working, and the output voltage of the linear voltage stabilizer follows the second reference voltage. The linear voltage stabilizer has a simple structure, can ensure that the linear voltage stabilizer can smoothly finish starting, realizes gradual adjustment of output voltage in the initial starting stage of the linear voltage stabilizer, and inhibits the generation of surge current.

Description

Linear voltage stabilizer
Technical Field
The present application relates to the field of integrated circuit design, and in particular, to a linear voltage regulator.
Background
With the wide application of handheld devices and portable electronic products, the demand of the market for power management chips is continuously rising, and LDOs (Low DropoutRegulator, low dropout linear regulators) are widely applied due to the characteristics of high efficiency, low output voltage noise, small voltage ripple and the like. Specifically, the LDO is mainly used for making the power tube inside the LDO be in a saturated conduction state by utilizing the voltage difference to the ground, so as to output stable load voltage to stably drive an external load.
However, when the LDO is started to drive the external load, since the output voltage is 0V before the traditional LDO is started in the power-on process and there is no charge on the output capacitor, after the circuit is instantaneously started, the power tube charges the capacitor to generate a great surge current, so that the linear voltage regulator is likely to generate instantaneous overvoltage impact exceeding the normal working voltage of the external load, resulting in chip damage and even damage to the circuit system.
Disclosure of Invention
In order to solve the problem that the linear voltage stabilizer in the prior art is likely to generate transient overvoltage impact exceeding the normal working voltage of an external load, so that a chip is damaged and even a circuit system is damaged, the embodiment of the application provides the linear voltage stabilizer, which can reduce the generation of surge current.
The embodiment of the application provides a linear voltage stabilizer, which comprises the following components:
the soft start module is used for outputting an adjusting signal;
the error amplifying module is connected with the soft start module and is used for adjusting the output voltage of the linear voltage stabilizer according to the adjusting signal;
the logic control module is respectively connected with the soft start module and the error amplification module and is used for controlling the state of the soft start module according to the output voltage of the linear voltage stabilizer;
when the regulating signal is a level signal which is gradually boosted, the output voltage of the linear voltage stabilizer is gradually risen, and when the output voltage of the linear voltage stabilizer is higher than the first reference voltage, the logic control module controls the soft start module to stop working, and the output voltage of the linear voltage stabilizer follows the second reference voltage.
Specifically, the soft start module may output the adjustment signal during an initial start-up phase of the linear voltage regulator (i.e., when the output voltage of the linear voltage regulator is less than or equal to the first reference voltage) to slowly increase the output voltage of the linear voltage regulator, thereby reducing the surge current and the influence on the input power supply. And the logic control module judges whether the starting is finished or not by detecting the output voltage and comparing the output voltage with the first reference voltage, and outputs a control signal to close the soft starting function of the soft starting module when the starting is finished. Further, the error amplifying module is further configured to receive a second reference voltage, and when the soft start function of the soft start module is turned off, the output voltage of the linear voltage regulator is stabilized at the second reference voltage.
In a possible implementation of the first aspect, the soft start module is further configured to adjust a ramp-up speed of the output voltage of the linear regulator.
In one possible implementation of the first aspect, the soft start module includes an adjusting unit connected to the error amplifying module, the adjusting unit is configured to adjust a climbing speed of the output voltage of the linear voltage regulator, and the adjusting unit includes:
one end of the first capacitor is used for receiving the output voltage of the linear voltage stabilizer, and the other end of the first capacitor is connected to the first node;
and the drain electrode of the second NMOS tube is interconnected with the grid electrode and is connected to the first node through a second resistor, and the source electrode of the second NMOS tube is grounded.
Since the output voltage of the linear voltage regulator gradually climbs, current can be injected into the first node through the first capacitor, and the current I at the first node and the output voltage Vout of the linear voltage regulator satisfyWherein C is 1 The current at the first node is also equal to the current flowing through the second NMOS transistor and the second resistor, so that the ramp-up speed of the output voltage of the linear voltage regulator can be adjusted by adjusting the sizes or resistances (capacitance values) of the second NMOS transistor, the first capacitor and the second resistor.
In a possible implementation manner of the first aspect, the adjusting unit further includes a third NMOS transistor, a gate of which is configured to receive the bias voltage, a drain of which is connected to the first node, and a source of which is grounded.
Specifically, in the present embodiment, the current at the first node is equal to the sum of the currents flowing through the third NMOS transistor and the second NMOS transistor, and therefore, the ramp-up speed of the output voltage of the linear regulator can be adjusted by adjusting the sizes or the resistances (capacitance values) of the second NMOS transistor, the third NMOS transistor, the first capacitor, and the second resistor.
In a possible implementation manner of the first aspect, the adjusting unit further includes a second capacitor, one end of which is connected to the first node, and the other end of which is grounded.
The provision of the second capacitor may further enhance the stability of the current at the first node.
In a possible implementation of the first aspect, the soft start module is further configured to receive an external enable signal and output the adjustment signal according to the external enable signal.
Specifically, the soft start module may be configured to receive the external enable signal, and output the adjustment signal according to the external enable signal, where the adjustment signal is a low level signal when the external enable signal is a low level signal, and is a level signal that gradually increases when the external enable signal is a high level signal.
In one possible implementation of the first aspect, the soft start module includes:
the output unit is connected with the second node and is used for outputting an adjusting signal according to the voltage of the second node;
a bias unit for providing a bias current;
the pull-up unit is connected with the second node and the bias unit respectively and is used for receiving an external enabling signal, and when the external enabling signal is a high-level signal, the pull-up unit carries out boosting treatment on the voltage of the second node so as to enable the regulating signal to be a level signal which is gradually boosted;
the soft start control unit is connected with the logic control module, and the logic control module pulls up the voltage of the second node to a first preset voltage value by controlling the soft start control unit so as to enable the output unit to stop outputting the adjusting signal.
Specifically, the output unit stops outputting the adjusting signal, which is represented by that the voltage of the second node is pulled up to the first preset voltage value to turn off the fifth PMOS transistor, that is, the adjusting signal is no longer controlled by the soft start module but is controlled by the error amplification module, at this time, the soft start function of the soft start module is turned off, and the soft start module stops working. Further, the first preset value may be a power supply voltage.
In one possible implementation of the first aspect, the pull-up unit includes: the first inverter, the first PMOS tube, the second PMOS tube, the third PMOS tube and the first NMOS tube;
the input end of the first inverter is used for receiving an external enabling signal, the output end of the first inverter is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the first current source, the drain electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with each other and are connected with the biasing unit, the drain electrode of the second PMOS tube, the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other and are connected with the drain electrode of the first NMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with the power supply end, the drain electrode of the third PMOS tube is connected to the second node, and the source electrode of the first NMOS tube is connected with the biasing unit.
Specifically, when the external enabling signal is a high-level signal, the first PMOS to the third PMOS and the first NMOS are all turned on, so that the second node is turned on with the power supply end, so as to gradually pull up the voltage of the second node, and thus the output voltage of the linear voltage regulator is enabled to climb.
In a possible implementation manner of the first aspect, the soft start module further includes:
and the adjusting unit is connected with the error amplifying module and used for adjusting the climbing speed of the output voltage of the linear voltage stabilizer.
In a possible implementation of the first aspect, the adjusting unit includes:
one end of the first capacitor is connected with the error amplifying module and is used for receiving the output voltage of the linear voltage stabilizer;
and the drain electrode of the second NMOS tube is connected with the grid electrode, and is connected to the other end of the first capacitor through a second resistor, and the source electrode of the second NMOS tube is grounded.
In a possible implementation manner of the first aspect, the adjusting unit further includes a third NMOS transistor, a gate of which is configured to receive the bias voltage, a drain of which is connected to the other end of the first capacitor, and a source of which is grounded.
In a possible implementation manner of the first aspect, the adjusting unit further includes a second capacitor, one end of which is connected to the first node, and the other end of which is grounded.
In a possible implementation manner of the first aspect, the linear voltage regulator further includes a fourth NMOS transistor, where a gate is connected to the adjusting unit and the pull-up unit at the first node, a drain is connected to the second node, and a source is grounded;
the adjusting unit is further configured to adjust a conducting state of the fourth NMOS according to the voltage of the first node, so that the pull-up unit boosts the voltage of the second node.
Specifically, as the current is injected at the first node, the voltage at the first node gradually decreases, so that the conduction degree of the fourth NMOS transistor decreases, thereby gradually increasing the voltage at the second node.
In a possible implementation manner of the first aspect, the soft start module further includes:
and the pull-down unit is connected with the first node and is used for receiving an external enabling signal, and when the external enabling signal is a low-level signal, the pull-down unit pulls up the voltage at the first node to enable the fourth NMOS tube to be conducted, so that the voltage of the second node is pulled down to a second preset voltage value.
Specifically, the second preset voltage value may be 0, and the adjustment signal voltage outputs a low level signal.
In a possible implementation of the first aspect, the pull-down unit includes: and the grid electrode of the fourth PMOS tube is used for receiving an external enabling signal, the source electrode of the fourth PMOS tube is connected with the second current source, and the drain electrode of the fourth PMOS tube is connected with the first node.
Specifically, when the external enable signal is a low level signal, the fourth PMOS transistor is turned on, and the voltage at the first node is pulled up to a high level, so that the fourth NMOS transistor is turned on, thereby pulling down the voltage at the second node to 0.
In a possible implementation manner of the first aspect, the soft start control unit includes a fifth NMOS transistor, a gate of which is connected to the logic control module, a drain of which is connected to a gate of the fourth NMOS transistor, and a source of which is grounded.
Specifically, when the output voltage of the linear voltage stabilizer is higher than the first reference voltage, the logic control module outputs a high-level signal, so that the fifth NMOS tube is turned on, the voltage of the first node is pulled down to 0, the fourth NMOS tube is turned off, and the voltage at the second node is pulled up to a first preset value, so that the output module stops outputting the adjusting signal.
In a possible implementation of the first aspect, the output unit includes: and the grid electrode of the fifth PMOS tube is connected with the second node, the source electrode of the fifth PMOS tube is used for outputting the adjusting signal, and the drain electrode of the fifth PMOS tube is grounded.
In a possible implementation of the first aspect, the error amplifying module includes;
the drain electrode of the power tube is used for outputting the output voltage of the linear voltage stabilizer, the grid electrode of the power tube is connected with the third node, and the source electrode of the power tube is connected with the power supply end;
a current mirror load unit is provided with a current mirror,
the climbing unit is respectively connected with the soft start module, the current mirror load unit and the third node, and is used for receiving the adjusting signal, outputting voltage to the third node according to the adjusting signal so as to adjust the conducting state of the power tube, so that the output voltage of the linear voltage stabilizer gradually climbs;
the input pair tube is connected with the current mirror load unit and is used for receiving the second reference voltage and the output voltage of the linear voltage stabilizer so as to enable the output voltage of the linear voltage stabilizer to be stabilized at the second reference voltage when the soft start module stops working;
and the bias current unit is respectively connected with the power tube, the climbing unit and the input pair tube and is used for providing bias current.
In a possible implementation of the first aspect, the linear voltage regulator further includes a switching unit, configured to receive an external enable signal, and control the power tube to be turned on or off according to the external enable signal.
Specifically, when the external enable signal is a low level signal, the power tube is turned off, and the output voltage of the linear voltage regulator is 0 at this time, and when the external enable signal is a high level signal, the power tube is turned on, and the output voltage of the linear voltage regulator gradually tends to and stabilizes at the second reference voltage at this time.
In a possible implementation manner of the first aspect, the switching unit includes a sixth PMOS transistor, a gate thereof is configured to receive the external enable signal, a source thereof is connected to the power supply terminal, and a drain thereof is connected to the third node.
In a possible implementation manner of the first aspect, the climbing unit includes a seventh PMOS transistor, a gate connected to the soft start module, configured to receive the adjustment signal, a source connected to the power supply terminal, and a drain connected to the third node.
Specifically, the power tube is a PMOS tube, the drain electrode of the power tube is used for outputting the output voltage of the linear voltage stabilizer, and in the process that the soft start module outputs the adjusting signal which is gradually boosted, the gate voltage of the seventh PMOS tube gradually rises, so that the conducting state of the seventh PMOS tube gradually drops, and the voltage at the third node gradually drops, namely the gate voltage of the power tube gradually drops, and the power tube gradually conducts, so that the output voltage gradually increases.
In one possible implementation manner of the first aspect, the logic control module includes a comparator, which is connected to the error amplifying module and the soft start module, respectively, and two input ends of the comparator are respectively configured to receive the output voltage of the linear voltage regulator and the first reference voltage, and when the output voltage of the linear voltage regulator is higher than the first reference voltage, the logic control module outputs the control signal of a high level.
In a possible implementation of the first aspect, the logic control module further includes a second inverter and a third inverter sequentially connected in series to an output of the comparator.
By providing two inverters, the signal output by the comparator is rectified while the level type (i.e., high level and low level) of the signal output by the comparator is not changed, so that the stability of the signal is improved.
Drawings
FIG. 1 illustrates a block diagram of a linear voltage regulator, according to some embodiments of the application;
FIG. 2 illustrates a circuit schematic of a soft start module, according to some embodiments of the application;
FIG. 3 illustrates a circuit schematic of an error amplification module, according to some embodiments of the application;
fig. 4 illustrates a circuit schematic of a logic control module, according to some embodiments of the application.
Detailed Description
The application will be further described with reference to specific examples and figures. It is to be understood that the illustrative embodiments of the present disclosure, including but not limited to linear regulators, are described herein in terms of specific embodiments for illustrating the application, and are not limiting of the application. Furthermore, for convenience of description, only some, but not all, structures or processes related to the present application are shown in the drawings.
Further advantages and effects of the present application will become apparent to those skilled in the art from the disclosure of the present specification, by describing the embodiments of the present application with specific examples. While the description of the application will be presented in connection with a preferred embodiment, it is not intended that the application be limited to this embodiment. Rather, the purpose of the application described in connection with the embodiments is to cover other alternatives or modifications, which may be extended by the claims based on the application. The following description contains many specific details for the purpose of providing a thorough understanding of the present application. The application may be practiced without these specific details. Furthermore, some specific details are omitted from the description in order to avoid obscuring the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.
The linear voltage stabilizer according to the embodiment of the application comprises a soft start module for outputting a regulating signal STG, an error amplifying module connected with the soft start module and used for regulating the output voltage VOUT of the linear voltage stabilizer according to the regulating signal STG, and a logic control module respectively connected with the soft start module and the error amplifying module and used for controlling the state of the soft start module according to the output voltage VOUT of the linear voltage stabilizer. When the regulating signal STG is a level signal with gradually increased voltage, the output voltage VOUT of the linear voltage regulator is gradually increased, and when the output voltage VOUT of the linear voltage regulator is higher than the first reference voltage VREF1, the logic control module controls the soft start module to stop working, and then the output voltage of the linear voltage regulator follows the second reference voltage.
In some embodiments of the present application, the soft start module includes an adjusting unit connected to the error amplifying module, where the adjusting unit is configured to adjust a climbing speed of the output voltage VOUT of the linear voltage regulator.
The adjustment unit includes a first capacitor and a second NMOS transistor. Specifically, one end of the first capacitor is used for receiving the output voltage VOUT of the linear voltage regulator, and the other end of the first capacitor is connected to the first node; the drain electrode and the grid electrode of the second NMOS tube are interconnected and connected to the first node through a second resistor, and the source electrode of the second NMOS tube is grounded.
Since the output voltage VOUT of the linear voltage regulator gradually climbs, current can be injected into the first node through the first capacitor C1, and the current I at the first node and the output voltage VOUT of the linear voltage regulator satisfyWherein C is 1 The current at the first node is also equal to the current flowing through the second NMOS transistor in the present embodiment, so the ramp-up speed of the output voltage VOUT of the linear voltage regulator can be adjusted by adjusting the dimensions (resistance/capacitance) of the second NMOS transistor, the first capacitor and the second resistor.
In some embodiments of the application, the soft start module further comprises:
an output unit connected to the second node for outputting an adjustment signal STG according to a voltage of the second node;
a bias unit for providing a bias current;
the pull-up unit is respectively connected with the second node and the bias unit and is used for receiving an external enable signal EN, and when the external enable signal EN is a high-level signal, the pull-up unit carries out boosting treatment on the voltage of the second node so as to enable the regulating signal STG to be a level signal which is gradually boosted;
the soft start control unit is connected with the logic control module, and the logic control module pulls up the voltage of the second node to a first preset voltage value by controlling the soft start control unit so as to enable the output unit to stop outputting the regulating signal STG.
In the application, the soft start module can output the regulating signal STG in the initial start-up stage of the linear voltage regulator (i.e. when the output voltage VOUT of the linear voltage regulator is less than or equal to the first reference voltage VREF 1) so as to slowly increase the output voltage VOUT of the linear voltage regulator, thereby reducing the surge current and the influence on the input power supply. And the logic control module judges whether the starting is finished or not by detecting the output voltage VOUT and comparing the output voltage VOUT with the first reference voltage VREF1, and outputs a control signal to close the soft starting function of the soft starting module when the starting is finished. The linear voltage stabilizer has the characteristics of simple structure, and can ensure that the linear voltage stabilizer can smoothly finish starting and realize gradual regulation of the output voltage VOUT in the initial starting stage of the linear voltage stabilizer.
Specifically, fig. 1 illustrates a block diagram of a linear voltage regulator, according to some embodiments of the application.
As shown in fig. 1, the linear voltage regulator includes a soft start module 1, an error amplification module 2, and a logic control module 3. The soft start module 1 is used for outputting an adjusting signal STG;
the error amplifying module 2 is connected with the soft start module 1 and is used for receiving the regulating signal STG and the second reference voltage VREF2 and adjusting the output voltage VOUT of the linear voltage stabilizer according to the regulating signal STG;
The logic control module 3 is respectively connected with the soft start module 1 and the error amplification module 2 and is used for controlling the state of the soft start module 1 according to the output voltage VOUT of the linear voltage stabilizer;
when the regulating signal STG is a level signal that gradually increases, the output voltage VOUT of the linear voltage regulator gradually increases, and when the output voltage VOUT of the linear voltage regulator is higher than the first reference voltage VREF1, the logic control module 3 controls the soft start module 1 to stop working, and thereafter, the output voltage VOUT of the linear voltage regulator follows the second reference voltage VREF2.
The soft start module 1 is also for receiving an external enable signal EN and outputting a regulating signal STG according to the external enable signal EN. As shown in fig. 2, the soft start module 1 includes an output unit 16, a bias unit 12, a pull-up unit 11, a pull-down unit 14, a soft start control unit 15, and an adjustment unit 13.
Specifically, the bias unit 12 may be configured to provide a bias current to the circuit, and the pull-up unit 11 is connected to the second node b and the bias unit 12, respectively, and is configured to receive the external enable signal EN, and when the external enable signal EN is a high level signal, the pull-up unit 11 performs a step-up process on the voltage of the second node b to make the adjustment signal STG appear as a gradually step-up level signal; the pull-down unit 14 is connected to the second node b and is configured to receive the external enable signal EN, and when the external enable signal EN is a low level signal, the pull-down unit 14 pulls down the voltage of the second node b to a second preset voltage value, so that the adjustment signal STG becomes a low level signal; the output unit 16 is connected to the second node b, and is configured to output the adjustment signal STG according to the voltage of the second node b; the adjusting unit 13 is connected with the error amplifying module 2 and is used for adjusting the rising speed of the output voltage VOUT of the linear voltage stabilizer; the soft start control unit 15 is connected to the logic control module 3, and the logic control module 3 controls the soft start control unit 15 to pull up the voltage of the second node b to a first preset voltage value so that the output unit 16 stops outputting the adjusting signal STG. Specifically, when the output voltage VOUT of the linear voltage regulator is higher than the first reference voltage VREF1, the logic control module 3 sends a high level signal to the soft start control unit 15 to stop the output of the output unit 16, and at this time, the adjustment signal STG is completely adjusted by the error amplifying module 2, that is, the soft start is completed, and the logic control module 3 controls the soft start function of the soft start module 1 to be turned off.
Further, the soft start module 1 further includes a fourth NMOS transistor MN4, whose gate is connected to the adjusting unit 13 and the pull-up unit 11 at the first node a, whose drain is connected to the second node b, and whose source is grounded.
Specifically, the adjusting unit 13 is further configured to adjust the conducting state of the fourth NMOS transistor MN4 according to the voltage of the first node a, so that the pull-up unit 11 performs the step-up process on the voltage of the second node b. The pull-down unit 14 is further connected to the fourth NMOS MN4, and when the external enable signal EN is a low level signal, the pull-down unit 14 turns on the fourth NMOS MN4 to pull down the voltage of the second node b to a second predetermined voltage value (e.g. zero level).
Specifically, with continued reference to fig. 2, the pull-up unit 11 includes a first inverter INV1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a first NMOS transistor MN1; the adjusting unit 13 includes a first capacitor C1, a second NMOS transistor MN2, a third NMOS transistor MN3, a second resistor R2, and a second capacitor C2; the pull-down unit 14 includes a fourth PMOS transistor MP4; the soft start control unit 15 includes a fifth NMOS transistor MN5; the output unit 16 comprises a fifth PMOS tube MP5; the bias unit 12 includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and a first resistor R1.
In other embodiments of the present application, an NMOS transistor may be used instead, where the gate of the NMOS transistor is used to receive the external enable signal EN, the source is connected to the bias unit 12, the drain is connected to the first current source I1, and the same function as the combination of the first inverter INV1 and the first PMOS transistor MP1 may also be achieved.
Specifically, the input end of the first inverter INV1 is configured to receive the external enable signal EN, the output end of the first inverter INV1 is connected to the gate of the first PMOS tube MP1, and the first inverter INV1 is configured to invert the external enable signal EN and output the external enable signal EN to the first PMOS tube MP1. The source electrode of the first PMOS tube MP1 is connected with a first current source I1, the drain electrode of the first PMOS tube MP1 and the grid electrode of the first NMOS tube MN1 are connected with one end of a first resistor R1 in the biasing unit 12, the drain electrode and the grid electrode of the second PMOS tube MP2 and the grid electrode of the third PMOS tube MP3 are connected with the drain electrode of the first NMOS tube MN1, the source electrode of the second PMOS tube MP2 and the source electrode of the third PMOS tube MP3 are connected with a power supply end VIN, the drain electrode of the third PMOS tube MP3 is connected with a second node b, and the source electrode of the first NMOS tube MN1 is connected with the drain electrode of a seventh NMOS tube MN7 in the biasing unit 12; the drain and the gate of the sixth NMOS transistor MN6 and the gate of the seventh NMOS transistor MN7 are interconnected and connected to the other end of the first resistor R1, and the sources of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are grounded, specifically, the sixth NMOS transistor MN6 and the second BMOS transistor may be used to generate the bias voltage VBN, where the bias voltage VBN is led out from the gate connection ends of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN 7. Specifically, the bias voltage VBN may enable the third NMOS transistor MN3 and the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, and the tenth NMOS transistor MN10 in the error amplification module 2 to be turned on.
The gate of the fourth PMOS MP4 is configured to receive the external enable signal EN, the source is connected to the second current source I2, and the drain is connected to the first node a, so as to pull up the voltage of the first node a to the high level voltage when the external enable signal EN is a low level signal. Alternatively, an inverter and an NMOS transistor may be used as another alternative to the fourth PMOS transistor MP 4. In this embodiment, the input end of the inverter is used for receiving the external enable signal EN, the output end is connected with the grid electrode of the NMOS tube, the source electrode of the NMOS tube is connected with the first node a, and the drain electrode is connected with the second current source I2.
One end of the first capacitor C1 is connected to the error amplifying module 2, and is configured to receive the output voltage VOUT of the linear voltage regulator, and the other end is connected to the first node a. When the output voltage VOUT of the linear voltage regulator rises, the output voltage VOUT charges the first capacitor C1 to generate a current, so that the voltage of the first node a is pulled up. The gate of the third NMOS transistor MN3 is connected with the bias voltage VBN, the drain is connected with the first node a, and the source is grounded; one end of the second resistor R2 is connected to the first node a, the gate and the drain of the second NMOS transistor MN2 are interconnected and connected to the other end of the second resistor R2, the source of the second NMOS transistor MN2 is grounded, and specifically, the third NMOS transistor MN3 and the second NMOS transistor MN2 are used for sharing the current injected from the first capacitor C1 to the first node a. Optionally, a second capacitor C2 is further connected in parallel to one end of the second resistor R2 and the source of the second NMOS transistor MN2, so as to further stabilize the current injected into the first node a by the first capacitor C1.
The gate of the fourth NMOS transistor MN4 is connected with the first node a, the drain is connected with the second node b, and the source is grounded. The gate of the fifth PMOS MP5 is connected to the second node b, the source is configured to output the adjustment signal STG, and the drain is grounded. When the voltage at the first node a is pulled up to a high level, the fourth NMOS transistor MN4 is fully turned on, so that the voltage at the second node b is pulled up to a zero level, and the fifth PMOS transistor MP5 is turned on.
Specifically, the fifth NMOS MN5 is further included, the gate is connected to the logic control module 3, and is configured to receive a control signal output by the logic control module 3, the source is grounded, the drain is connected to the gate of the fourth NMOS MN4, when the logic control module 3 sends out a control signal (is a high level signal), the fifth NMOS MN5 is turned on, so that the voltage at the gate of the fourth NMOS MN4 is pulled down to zero level, resulting in the fourth NMOS MN4 being turned off, and further, the voltage at the second node b is pulled up to the power supply voltage, so that the fifth PMOS MP5 is turned off, at this time, the soft start module 1 turns off the soft start function, and the adjustment signal STG is completely controlled by the error amplification module 2.
Specifically, the operation flow of the soft start function is briefly described with reference to the specific circuit diagram of the soft start module 1 shown in fig. 2.
When the circuit is just started, the external enable signal EN is 0, at this time, the first PMOS transistor MP1, the third PMOS transistor MP3, the first NMOS transistor MN1, and the like are all turned off, the fourth PMOS transistor MP4 is turned on, so that the current of the second current source I2 flows to the second resistor R2 and the second NMOS transistor MN2, the voltage Va at the first node a is va=i 2 R 2 +V GS_MN5 At this time, the voltage Va of the first node a is pulled up to a high voltage sufficient to turn on the fourth NMOS transistor MN 4. And because the third PMOS tube MP3 is turned off at this time, the voltage Vb of the second node b is pulled down to zero potential, so that the fifth PMOG tube is turned on, and the voltage value of the regulating signal STG output by the source electrode of the fifth PMOS tube MP5 is V STG ＝V b +V MP_5 ＝V MP_5 。
When the external enable signal EN of high level arrives, the first to third PMOS tubes MP1 to MP3 of the soft start module 1, the first, sixth and seventh NMOS tubes MN1, MN6 and MN7 are all turned on, the fourth PMOS tube MP4 is turned off, and the voltage at the first node a gradually decreases and the voltage at the second node b gradually increases due to the pull-down action of the third and second NMOS tubes MN3 and MN2 and the pull-up action of the third PMOS tube MP3, and the voltage value V of the regulating signal STG STG ＝V b +V GS_MP5 The voltage at the first node a is lower and lower with time, so that the conduction state of the fourth NMOS transistor MN4 is gradually reduced, the passing current is smaller and smaller, and the voltage at the second node b is higher and higher from heat. It should be noted that in this process, the voltage at the first node a gradually decreases although it decreases The voltage drop is not enough to turn off the fourth NMOS transistor MN4 completely. Similarly, the voltage of the second node b is also increased gradually in the process, but the increase is insufficient to completely turn off the fifth PMOS transistor MP 5. Therefore, the voltage value of the regulating signal STG output by the source electrode of the fifth PMOS transistor MP5 is always increased in the process until the voltage value of the output voltage VOUT of the linear voltage regulator output by the error amplifying module 2 is higher than the first reference voltage VREF1, the logic control module 3 outputs a high-level control signal to turn on the fifth NMOS transistor MN5, so as to pull down the voltage at the gate electrode (i.e., the first node a) of the fourth NMOS transistor MN4 to zero level, thereby completely turning off the fourth NMOS transistor MN4, and the second node b is pulled up to the power supply voltage under the pull-up action of the third PMOS transistor MP3, so that the fifth PMOS transistor MP5 is completely turned off, at this time, the regulating signal STG is no longer controlled by the fifth PMOS transistor MP5, i.e., the soft start function of the soft start module 1 is turned off, and the regulating signal STG is completely determined by the inside of the error amplifying module 2.
In addition, in the step of rising the output voltage VOUT, the rising speed of the output voltage VOUT can be adjusted by adjusting the dimensions (resistance/capacitance) of the third NMOS transistor MN3, the second NMOS transistor MN2, the first capacitor C1, and the second resistor R2. Specifically, the following is described.
After the output voltage VOUT starts to rise, VOUT injects a current I into the first node a through the first capacitor C1, which satisfies:
C 1 the capacitance of the first capacitor C1, vout, is the value of the output voltage Vout.
In order to ensure the stability of the circuit, the third NMOS transistor MN3 and the second NMOS transistor MN2 are arranged such that the current at the first node a is equal to the sum of the currents flowing through the third NMOS transistor MN3 and the second NMOS transistor MN2, i.e. I=I MN4 +I MN5 Therefore, the rising slope (i.e., the rising speed) of the output voltage VOUT is:
that is, the rising slope of the output voltage VOUT is substantially constant, and the rising slope of the output voltage VOUT can be adjusted by adjusting the dimensions (resistance/capacitance) of the second NMOS transistor MN2, the third NMOS transistor MN3, the first capacitor C1, and the second resistor R2.
Referring to fig. 3, the error amplification module 2 includes a power tube MP10, a current mirror load unit 21, a ramp-up unit 23, an input pair tube 22, a bias current unit 25, and a switch unit 24.
Specifically, the drain electrode of the power tube MP10 is configured to output the output voltage VOUT of the linear voltage regulator, the gate electrode thereof is connected to the third node c, and the source electrode thereof is connected to the power supply terminal VIN; the current mirror load unit 21 includes an eighth PMOS transistor MP8 and a ninth PMOS transistor MP9 having gate interconnections, and the input pair transistor 22 includes an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12 having source interconnections. Specifically, the gate electrode of the eighth PMOS transistor MP8 and the drain electrode thereof are interconnected and connected to the drain electrode of the eleventh NMOS transistor MN11 in the input pair of transistors 22, the drain electrode of the ninth PMOS transistor MP9 is connected to the drain electrode of the twelfth NMOS transistor MN12 in the input pair of transistors 22, the source electrodes of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply terminal VIN, and the current mirror load unit 21 is configured to supply a driving current to the structures such as the input pair of transistors 22. The gate of the eleventh NMOS transistor MN11 is configured to receive the second reference voltage VREF2, the source is connected to the drain of the eighth NMOS transistor MN8 in the bias current unit 25, the gate of the twelfth NMOS transistor MN12 is configured to receive the output voltage VOUT of the linear voltage regulator, and the input pair transistor 22 is configured to enable the output voltage VOUT of the linear voltage regulator to be stabilized at the second reference voltage VREF2 when the soft start module 1 stops operating. Further, the gate of the eighth NMOS transistor MN8 is connected to the bias voltage VBN in the soft start module 1, and the source is grounded for providing a bias current thereto.
The climbing unit 23 is respectively connected to the soft start module 1, the current mirror load unit 21 and the third node c, and is configured to receive the adjustment signal STG, and output a voltage VOUT to the third node c according to the adjustment signal STG to adjust the on state of the power tube MP10, so that the output voltage VOUT of the linear voltage regulator gradually climbs. Specifically, the climbing unit 23 includes a seventh PMOS MP7, a gate connected to the soft start module 1, configured to receive the adjustment signal STG, a source connected to the power supply terminal VIN, and a drain connected to the third node c. When the voltage of the regulating signal STG gradually increases, the conducting state of the seventh PMOS MP7 gradually decreases, so that the voltage of the third node c gradually decreases under the pull-down action of the ninth NMOS MN9, and the conducting state of the power transistor MP10 gradually increases, so that the output voltage VOUT of the linear regulator gradually rises. When the output voltage VOUT exceeds the first reference voltage VREF1, the soft start function of the soft start module 1 is turned off, and at this time, the adjustment signal STG is determined by the error amplification module 2, and the output voltage VOUT of the linear voltage regulator is stabilized at the second reference voltage VREF2 by the clamping function of the error amplification module 2 (i.e. under the action of the input pair tube 22). Specifically, the first reference voltage VREF1 is slightly smaller than the second reference voltage VREF2.
Further, the bias current unit 25 is respectively connected to the power tube MP10, the climbing unit 23 and the input pair tube 22, and is used for providing bias current, specifically, the bias current unit 25 includes three NMOS tubes, the sources of which are grounded and the gates of which are all connected to the bias voltage VBN output by the soft start module 1, specifically, the three NMOS tubes are respectively an eighth NMOS tube MN8, a ninth NMOS tube MN9 and a tenth NMOS tube MN10, wherein, the drain electrode of the eighth NMOS tube is connected to the source electrode of the NMOS tube in the input pair tube 22, the drain electrode of the ninth NMOS tube MN9 is connected to the drain electrode of the seventh PMOS tube MP7, and the drain electrode of the tenth NMOS tube MN10 is connected to the drain electrode of the power tube MP 10.
Further, the error amplifying module 2 further includes a switching unit 24 for receiving the external enable signal EN and controlling the power tube MP10 to be turned on or off according to the external enable signal EN. The switch unit 24 includes a sixth PMOS MP6 having a gate for receiving the external enable signal EN, a source connected to the power supply terminal VIN, and a drain connected to the third node c. When the external enable signal EN is a low level signal, the sixth PMOS MP6 is turned on, so that the voltage at the third node c is pulled up to the power voltage, and the power transistor MP10 is turned off, and the output voltage VOUT of the linear voltage regulator is 0.
The linear voltage stabilizer of the application increases the device selection surface when preparing the linear voltage stabilizer. Furthermore, two NMOS transistors are selected as the input pair transistors 22 in the operational amplifier module 2, so that the size of the linear voltage regulator can be reduced, and the performance of the linear voltage regulator can be improved.
The soft start module 1 outputs an adjusting signal to ensure that the input pair tube 22 in the error amplifying module 2 can be driven in the initial start stage, and the linear voltage stabilizer is prevented from being out of balance in the initial start stage. And, the output voltage starts to gradually increase from the initial value until the output voltage is increased to the first reference voltage, so that the gradual increase of the output voltage VOUT is ensured.
Specifically, referring to fig. 4, the logic control module 3 includes a comparator, which is connected to the error amplifying module 2 and the soft start module 1, respectively, and has two input ends respectively for receiving the output voltage VOUT of the linear voltage regulator and the first reference voltage VREF1, and an output end connected to the gate of the sixth NNMOS transistor in the soft start module 1, and when the output voltage VOUT of the linear voltage regulator is higher than the first reference voltage VREF1, the logic control module 3 outputs a control signal of a high level to the gate of the fifth NMOS transistor MN5, so that the fifth NMOS transistor MN5 is turned on, and the voltage at the first node a is pulled down to a zero level.
Further, the logic control module 3 may further include two inverters, as shown in fig. 4, including a second inverter INV2 and a third inverter INV3, connected in series to an output end of the comparator, and configured to rectify a signal output by the comparator, so as to improve stability of the signal.
The operation of the linear voltage regulator will be described specifically below by taking the circuit configuration of each module shown in fig. 2 to 4 as an example.
When the circuit is just started, the external enable signal EN is 0, and at this time, the first PMOS transistor MP1, the third PMOS transistor MP3, the first NMOS transistor MN1, etc. are all turned off, and the fourth PMOS transistor MP4 is turned on, so that the current of the second current source I2 flows to the second resistor R2 and the second NMOS transistor MN2, and the voltage Va at the first node a is va=i 2 R 2 +V GS_MN5 At this time, the voltage Va of the first node a is pulled up to a high voltage sufficient to turn on the fourth NMOS transistor MN 4. And because the third PMOS tube MP3 is turned off at this time, the voltage Vb of the second node b is pulled down to zero potential, so that the fifth PMOS tube MP5 is turned on, and the voltage value of the regulating signal STG output by the source electrode of the fifth PMOS tube MP5 is V STG ＝V b +V MP_5 ＝V MP_5 . In addition, since the external enable signal EN is 0, the sixth PMOS transistor MP6 in the error amplifying module 2 is turned on, so that the gate voltage of the power transistor MP10 is pulled up to the power voltage, so that the power transistor MP10 is in the off state, and the output voltage VOUT of the linear voltage regulator is 0.
When the external enable signal EN of high level arrives, the first to third PMOS tubes MP1 to MP3 of the soft start module 1, the first, sixth and seventh NMOS tubes MN1, MN6 and MN7 are all turned on, the fourth PMOS tube MP4 is turned off, and the voltage Va at the first node a gradually decreases and the voltage Vb at the second node b gradually increases due to the pull-down action of the third and second NMOS tubes MN3 and MN2 and the pull-up action of the third PMOS tube MP3, the voltage value V of the regulating signal STG STG ＝V b +V GS_MP5 The output voltage VOUT of the error amplifying module 2 gradually rises, when the output voltage VOUT rises to the first reference voltage VREF1, the logic control module 3 outputs a control signal CTRL with a high level, the fifth NMOS transistor MN5 is turned on to pull the voltage Va at the first node a to a zero level, which results in the turn-off of the fourth NMOS transistor MN4, the voltage Vb at the second node b is raised to the power supply voltage due to the pull-up action of the third PMOS transistor MP3, so that the fifth PMOS transistor MP5 is turned off, so that the voltage of the adjustment signal STG is completely determined by the inside of the error amplifying module 2, and the value of the output voltage VOUT is stabilized at the second reference voltage VREF2 by the clamping function of the error amplifying module 2, wherein the first reference voltage VREF1 is slightly smaller than the second reference voltage VREF2.
The linear voltage stabilizer provided by the application comprises a soft start module 1, an error amplification module 2 and a logic control module 3. The soft start module 1 slowly increases the output voltage VOUT when the power supply is started, so that surge current and influence on the input power supply are reduced; the error amplification module 2 suppresses voltage ripple by adjusting the grid of the power tube MP10, so as to realize the stabilization of the output voltage VOUT; the logic control module 3 determines whether the start is completed by detecting the output voltage VOUT and comparing with the first reference voltage VREF1, and outputs a logic control signal. The linear voltage stabilizer in the application adopts a simpler circuit architecture, can effectively prevent surge current, realize smooth rising of output voltage VOUT, and can ensure the stability and reliability of the circuit. In addition, the rising slope of the output voltage VOUT of the linear voltage regulator can be adjusted by adjusting the sizes of the third NMOS transistor MN3, the second NMOS transistor MN2, the first capacitor C1 and the second resistor R2, so as to improve the flexibility of the linear voltage regulator.
In the drawings, some structural or methodological features may be shown in a particular arrangement and/or order. However, it should be understood that such a particular arrangement and/or ordering may not be required. Rather, in some embodiments, these features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of structural or methodological features in a particular figure is not meant to imply that such features are required in all embodiments, and in some embodiments, may not be included or may be combined with other features.
It should be noted that, in the embodiments of the present application, each unit/module mentioned in each device is a logic unit/module, and in physical terms, one logic unit/module may be one physical unit/module, or may be a part of one physical unit/module, or may be implemented by a combination of multiple physical units/modules, where the physical implementation manner of the logic unit/module itself is not the most important, and the combination of functions implemented by the logic unit/module is only a key for solving the technical problem posed by the present application. Furthermore, in order to highlight the innovative part of the present application, the above-described device embodiments of the present application do not introduce units/modules that are less closely related to solving the technical problems posed by the present application, which does not indicate that the above-described device embodiments do not have other units/modules.
It should be noted that in the examples and descriptions of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
While the application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims (17)

1. A linear voltage regulator, comprising:
the soft start module is used for outputting an adjusting signal;
the error amplification module is connected with the soft start module and is used for adjusting the output voltage of the linear voltage stabilizer according to the adjusting signal;
the logic control module is respectively connected with the soft start module and the error amplification module and is used for controlling the state of the soft start module according to the output voltage of the linear voltage stabilizer;
when the regulating signal is a level signal which is gradually boosted, the output voltage of the linear voltage stabilizer is gradually boosted, and when the output voltage of the linear voltage stabilizer is higher than a first reference voltage, the logic control module controls the soft start module to stop working, and the output voltage of the linear voltage stabilizer follows a second reference voltage.
2. The linear voltage regulator of claim 1, wherein the soft start module is further configured to receive an external enable signal and output the adjustment signal based on the external enable signal.
3. The linear voltage regulator of claim 2, wherein the soft start module comprises:
the output unit is connected with the second node and is used for outputting the adjusting signal according to the voltage of the second node;
a bias unit for providing a bias voltage;
the pull-up unit is respectively connected with the second node and the bias unit and is used for receiving the external enabling signal, and when the external enabling signal is a high-level signal, the pull-up unit carries out step-up processing on the voltage of the second node so as to enable the regulating signal to be a level signal which is gradually stepped up;
the soft start control unit is connected with the logic control module, and the logic control module pulls up the voltage of the second node to a first preset voltage value by controlling the soft start control unit so that the output unit stops outputting the adjusting signal.
4. The linear voltage regulator of claim 3, wherein the pull-up unit comprises: the first inverter, the first PMOS tube, the second PMOS tube, the third PMOS tube and the first NMOS tube;
the input end of the first inverter is used for receiving the external enabling signal, the output end of the first inverter is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with a first current source, the drain electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with each other and the bias unit, the drain electrode and the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube are connected with each other and the drain electrode of the first NMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube are connected with a power supply end, the drain electrode of the third PMOS tube is connected to the second node, and the source electrode of the first NMOS tube is connected with the bias unit.
5. The linear voltage regulator of claim 3, wherein the soft start module further comprises:
and the adjusting unit is connected with the error amplifying module and used for adjusting the climbing speed of the output voltage of the linear voltage stabilizer.
6. The linear voltage regulator of claim 5, wherein the adjustment unit comprises:
one end of the first capacitor is connected with the error amplifying module and is used for receiving the output voltage of the linear voltage stabilizer;
and the drain electrode of the second NMOS tube is connected with the grid electrode, and is connected to the other end of the first capacitor through a second resistor, and the source electrode of the second NMOS tube is grounded.
7. The linear voltage regulator of claim 6, wherein the adjustment unit further comprises a third NMOS transistor having a gate for receiving the bias voltage, a drain connected to the other end of the first capacitor, and a source connected to ground.
8. The linear voltage regulator of claim 5, further comprising a fourth NMOS transistor having a gate connected to the regulator unit and the pull-up unit, respectively, at a first node, a drain connected to the second node, and a source connected to ground;
the adjusting unit is further configured to adjust a conducting state of the fourth NMOS according to the voltage of the first node, so that the pull-up unit performs a step-up process on the voltage of the second node.
9. The linear voltage regulator of claim 8, wherein the soft start module further comprises:
and the pull-down unit is connected with the first node and is used for receiving the external enabling signal, and when the external enabling signal is a low-level signal, the pull-down unit enables the fourth NMOS tube to be conducted by pulling up the voltage at the first node so as to pull down the voltage of the second node to a second preset voltage value.
10. The linear voltage regulator of claim 9, wherein the pull-down unit comprises: and the grid electrode of the fourth PMOS tube is used for receiving the external enabling signal, the source electrode of the fourth PMOS tube is connected with the second current source, and the drain electrode of the fourth PMOS tube is connected with the first node.
11. The linear voltage regulator of claim 8, wherein the soft start control unit comprises a fifth NMOS transistor having a gate connected to the logic control module, a drain connected to the gate of the fourth NMOS transistor, and a source connected to ground.
12. The linear voltage regulator of claim 3, wherein the output unit comprises: and the grid electrode of the fifth PMOS tube is connected with the second node, the source electrode of the fifth PMOS tube is used for outputting the regulating signal, and the drain electrode of the fifth PMOS tube is grounded.
13. The linear voltage regulator of claim 1, wherein the error amplification module comprises;
the drain electrode of the power tube is used for outputting the output voltage of the linear voltage stabilizer, the grid electrode of the power tube is connected with the third node, and the source electrode of the power tube is connected with the power end;
a current mirror load unit;
the climbing unit is respectively connected with the soft start module, the current mirror load unit and the third node, and is used for receiving the adjusting signal, outputting voltage to the third node according to the adjusting signal so as to adjust the conducting state of the power tube, and gradually climbing the output voltage of the linear voltage stabilizer;
the input pair tube is connected with the current mirror load unit and is used for receiving a second reference voltage and the output voltage of the linear voltage stabilizer so that the output voltage of the linear voltage stabilizer follows the second reference voltage when the soft start module stops working;
and the bias current unit is respectively connected with the power tube, the climbing unit and the input pair tube and is used for providing bias current.
14. The linear voltage regulator of claim 13, further comprising a switching unit for receiving an external enable signal and controlling the turn-on and turn-off of the power tube according to the external enable signal.
15. The linear voltage regulator of claim 14, wherein the switching unit comprises a sixth PMOS transistor having a gate for receiving the external enable signal, a source connected to the power supply terminal, and a drain connected to the third node.
16. The linear voltage regulator of claim 13, wherein the ramp-up unit comprises a seventh PMOS transistor having a gate connected to the soft start module for receiving the regulation signal, a source connected to a power supply terminal, and a drain connected to the third node.
17. The linear voltage regulator of claim 1, wherein the logic control module comprises a comparator connected to the error amplification module and the soft start module, respectively, wherein two input terminals of the comparator are respectively used for receiving an output voltage of the linear voltage regulator and a first reference voltage, and when the output voltage of the linear voltage regulator is higher than the first reference voltage, the logic control module outputs a control signal of a high level.
CN202310433208.1A 2023-04-21 2023-04-21 Linear voltage stabilizer Pending CN116578150A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117175927A (en) * 2023-11-03 2023-12-05 合芯科技(苏州)有限公司 Self-adaptive soft start circuit for relieving discharge overshoot and reference voltage source circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117175927A (en) * 2023-11-03 2023-12-05 合芯科技(苏州)有限公司 Self-adaptive soft start circuit for relieving discharge overshoot and reference voltage source circuit
CN117175927B (en) * 2023-11-03 2024-02-09 合芯科技(苏州)有限公司 Self-adaptive soft start circuit for relieving discharge overshoot and reference voltage source circuit

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