CN116564987A - Preparation method of back-illuminated CMOS image sensor - Google Patents

Preparation method of back-illuminated CMOS image sensor Download PDF

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Publication number
CN116564987A
CN116564987A CN202310646312.9A CN202310646312A CN116564987A CN 116564987 A CN116564987 A CN 116564987A CN 202310646312 A CN202310646312 A CN 202310646312A CN 116564987 A CN116564987 A CN 116564987A
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substrate
layer
image sensor
cmos image
illuminated cmos
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Inventor
邓生泉
周祖源
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202310646312.9A priority Critical patent/CN116564987A/en
Publication of CN116564987A publication Critical patent/CN116564987A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The invention provides a preparation method of a backside illuminated CMOS image sensor, which comprises the steps of respectively preparing a First substrate with a pixel array layer and a connecting circuit layer and a second substrate with a TSV column, bonding the First substrate and the second substrate to realize the electric connection of the TSV column and the connecting circuit layer, preparing a light selection layer and bonding the light selection layer and the light transmission substrate, so that the preparation process time of the backside illuminated CMOS image sensor can be shortened, the yield can be improved, the alignment precision of the TSV column and the connecting circuit layer can be improved through a TSV First process, the electric performance of the backside illuminated CMOS image sensor can be improved, the damage probability of the backside illuminated CMOS image sensor can be reduced, and the packaging yield can be improved.

Description

Preparation method of back-illuminated CMOS image sensor
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a preparation method of a back-illuminated CMOS image sensor.
Background
Image sensors have been developed based on electro-optical technology, i.e. sensors that are capable of sensing optical image information and converting it into a usable output signal.
The image sensor can be classified into a CCD (Charge-Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor according to the principle that it adopts. Since the 90 s of the last century, CMOS image sensor technology has gained attention and a great deal of research and development resources in the industry, CMOS image sensors have begun to gradually replace CCD image sensors, and today, CMOS image sensors have taken an absolute predominance in the market.
CMOS image sensors include both front-illuminated (FSI) and back-illuminated (BSI). With the increasing number of pixels of CMOS image sensors, the pixel size is continuously reduced, and the demands of people for resolution and definition of the image sensor are continuously increased. The back-illuminated CMOS image sensor is optimized to change the internal structure of the element, change the position of the photosensitive layer element and make the light energy irradiate from the back of the device, so that the influence of the circuit and transistor between the micro lens and the photodiode on the light in the front-illuminated CMOS image sensor structure can be avoided, the light efficiency can be obviously improved, and the shooting effect under the low illumination condition is greatly improved, so that the CMOS image sensor industry has been transited from FSI technology to BSI technology.
The preparation process of the back-illuminated CMOS image sensor of the current mainstream mainly comprises the following steps: preparing a pixel array layer with a CMOS and a photodiode, forming a connection circuit layer on one surface of the pixel array layer, forming a light selection layer comprising a light filter and a micro lens on the other surface of the pixel array layer, bonding with a light-transmitting substrate to form a cavity, and forming a circuit leading-out layer which is provided with TSV and RDL and is electrically connected with the connection circuit layer. However, this preparation process often has the following problems in packaging due to the preparation of the TSV in the later stage: the internal structure of the CMOS image sensor is easy to damage, the TSV alignment precision is low, and the package interconnection and the conductivity are weak.
Therefore, it is necessary to provide a method for manufacturing a backside illuminated CMOS image sensor.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a backside illuminated CMOS image sensor, which is used for solving the problem of packaging yield in the prior art when manufacturing the backside illuminated CMOS image sensor.
To achieve the above and other related objects, the present invention provides a method for manufacturing a backside illuminated CMOS image sensor, comprising the steps of:
providing a first substrate, wherein the first substrate comprises a substrate, a pixel array layer positioned on the substrate and a connection circuit layer electrically connected with the pixel array layer;
providing a second substrate, wherein the second substrate comprises a TSV column, a first end of the TSV column is exposed out of the second substrate, and a second end of the TSV column is positioned in the second substrate;
bonding the first substrate and the second substrate, and electrically connecting the first end of the TSV column with the connection circuit layer;
removing the substrate to expose the pixel array layer;
forming a light selection layer on the pixel array layer;
providing a light-transmitting substrate, bonding the light-transmitting substrate with the pixel array layer, and forming a cavity coating the light selection layer between the light-transmitting substrate and the pixel array layer;
thinning the second substrate reveals a second end of the TSV column.
Optionally, the substrate comprises a P-type substrate, the pixel array layer comprises a P-type epitaxial layer in contact with the P-type substrate, and the doping concentration of the P-type epitaxial layer is smaller than that of the P-type substrate.
Optionally, the light-transmitting substrate includes a glass substrate or a plastic substrate.
Optionally, a patterned support is formed on a surface of the light-transmitting substrate, and the light-transmitting substrate is bonded to the pixel array layer through the support.
Optionally, the light selection layer includes a filter including one or a combination of a red filter, a green filter, and a blue filter, and an on-chip lens.
Optionally, the backside illuminated CMOS image sensor is fabricated as a wafer level chip scale package.
Optionally, a dicing step is further included to divide the wafer level backside illuminated CMOS image sensor into a plurality of individual chips.
Optionally, the method further comprises:
forming a rewiring layer on the second substrate, wherein the rewiring layer is electrically connected with the second end of the TSV column;
and forming a metal bump electrically connected with the rewiring layer on the rewiring layer.
Optionally, the method for forming the TSV column includes a laser drilling method or a plasma etching method.
Optionally, the TSV pillars comprise one or a combination of Cu pillars, al pillars, and W pillars.
As described above, in the method for manufacturing a backside illuminated CMOS image sensor according to the present invention, the First substrate having the pixel array layer and the connection circuit layer and the second substrate having the TSV pillar are manufactured separately, and the First substrate and the second substrate are bonded to each other, so that the TSV pillar is electrically connected to the connection circuit layer, and then the light selection layer is manufactured and bonded to the light-transmitting substrate, so that the manufacturing process time of the backside illuminated CMOS image sensor can be shortened, the yield can be improved, the alignment precision of the TSV pillar and the connection circuit layer can be improved, the electrical performance of the backside illuminated CMOS image sensor can be improved, the damage probability of the backside illuminated CMOS image sensor can be reduced, and the packaging yield can be improved.
Drawings
Fig. 1 is a flowchart of a process for fabricating a backside illuminated CMOS image sensor according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a first substrate according to an embodiment of the invention.
Fig. 3 is a schematic structural diagram of a second substrate according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram of a first substrate and a second substrate bonded according to an embodiment of the invention.
Fig. 5 is a schematic view of a structure after removing a substrate according to an embodiment of the invention.
Fig. 6 is a schematic structural diagram of the light selecting layer formed in the embodiment of the invention.
Fig. 7 is a schematic view of a structure after forming a cavity according to an embodiment of the invention.
Fig. 8 is a schematic diagram of a structure of a thinned second substrate with a second end of the TSV pillar exposed in an embodiment of the invention.
Fig. 9 is a schematic diagram of a structure after forming a rewiring layer according to an embodiment of the invention.
Fig. 10 is a schematic diagram of a structure after forming metal bumps according to an embodiment of the invention.
Description of element reference numerals
101 P-type substrate
102 P-type epitaxial layer
103 CMOS sensing layer
104. Connection circuit layer
201. Silicon substrate
202 TSV column
301. Red filter
302. Green filter
303. Blue filter
400. On-chip lens
500. Glass substrate
600. Support member
700. Cavity cavity
801. Dielectric layer
802. Metal wiring layer
900. Metal bump
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
As described in detail in the embodiments of the present invention, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures, including embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact, and further, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.
As shown in fig. 1, the present embodiment provides a method for manufacturing a backside illuminated CMOS image sensor, which includes the following steps:
s1: providing a first substrate, wherein the first substrate comprises a substrate, a pixel array layer positioned on the substrate and a connection circuit layer electrically connected with the pixel array layer;
s2: providing a second substrate, wherein the second substrate comprises a TSV column, a first end of the TSV column is exposed out of the second substrate, and a second end of the TSV column is positioned in the second substrate;
s3: bonding the first substrate and the second substrate, and electrically connecting the first end of the TSV column with the connection circuit layer;
s4: removing the substrate to expose the pixel array layer;
s5: forming a light selection layer on the pixel array layer;
s6: providing a light-transmitting substrate, bonding the light-transmitting substrate with the pixel array layer, and forming a cavity coating the light selection layer between the light-transmitting substrate and the pixel array layer;
s7: thinning the second substrate reveals a second end of the TSV column.
According to the preparation method of the backside illuminated CMOS image sensor, the First substrate with the pixel array layer and the connection circuit layer and the second substrate with the TSV column are respectively prepared, the First substrate and the second substrate are bonded, the electric connection of the TSV column and the connection circuit layer is achieved, then the light selection layer is prepared and bonded with the light-transmitting substrate, so that the preparation process time of the backside illuminated CMOS image sensor can be shortened, the yield is improved, the alignment precision of the TSV column and the connection circuit layer can be improved through a TSV First process, the electric performance of the backside illuminated CMOS image sensor is improved, the damage probability of the backside illuminated CMOS image sensor can be reduced, and the packaging yield is improved.
The following describes a method for manufacturing the backside illuminated CMOS image sensor with reference to fig. 2 to 10 of the specification.
First, referring to fig. 1 and 2, step S1 is performed to provide a first substrate, where the first substrate includes a substrate, a pixel array layer on the substrate, and a connection circuit layer 104 electrically connected to the pixel array layer.
Specifically, the step of forming the first substrate may include:
providing a P-type substrate 101;
forming a P-type epitaxial layer 102 on a P-type substrate 101 by epitaxy, forming an isolation reflective structure (not shown), a photodiode (PD, not shown), and an active region of CMOS (not shown) disposed corresponding to the photodiode in the P-type epitaxial layer 102, and forming a gate of CMOS (not shown) on the P-type epitaxial layer 102 to form the pixel array layer including the P-type epitaxial layer 102 and the CMOS sensor layer 103;
a passivation layer (not shown), such as a silicon nitride layer, is deposited, and metal members (not shown), such as metal pillars, metal wires, and metal pads, electrically connected to the CMOS (not shown) are formed in the passivation layer to constitute the connection circuit layer 104.
In this embodiment, the P-type substrate 101 is adopted as the substrate, the pixel array layer includes the P-type epitaxial layer 102 contacting the P-type substrate 101, and preferably, the doping concentration of the P-type epitaxial layer 102 is smaller than that of the P-type substrate 101, i.e., the P-type substrate 101 adopts a heavily doped P-type semiconductor material layer, and the P-type epitaxial layer 102 adopts a lightly doped P-type semiconductor material layer, so that the effective removal of the P-type substrate 101 is realized through the control of the selective etching ratio of the P-type substrate 101 and the P-type epitaxial layer 102, as shown in fig. 5, so that the P-type epitaxial layer 102 has a flat surface, thereby facilitating the control of the subsequent process.
The specific structure, material and preparation of the first substrate are not limited thereto, and may be selected as desired.
Next, referring to fig. 1 and 3, step S2 is performed to provide a second substrate, where the second substrate includes a TSV pillar 202, and a first end of the TSV pillar 202 is exposed to the second substrate, and a second end of the TSV pillar 202 is located in the second substrate.
Specifically, in this embodiment, the second substrate is prepared by using the silicon substrate 201, where the method for forming the TSV pillar 202 may include the steps of patterning the silicon substrate 201, performing metal deposition, and planarizing, and the method for patterning the silicon substrate 201 may include a laser drilling method or a plasma etching method, and the formed TSV pillar 202 may include one or a combination of Cu pillar, al pillar, and W pillar.
Further, to avoid leakage, a dielectric layer (not shown), such as a silicon nitride layer, a silicon oxide layer, etc., may be formed at the contact between the TSV pillars 202 and the silicon substrate 201.
The specific structure, material and preparation of the second substrate are not limited thereto, and may be selected as desired.
Next, referring to fig. 1 and 4, step S3 is performed to bond the first substrate and the second substrate, and the first end of the TSV pillar 202 is electrically connected to the connection circuit layer 104.
Specifically, since the surface of the first substrate has the metal pad for electrical connection, the surface of the second substrate exposes the first end of the TSV pillar 202, so that after the alignment bonding, the first substrate and the second substrate can be electrically connected, and the alignment bonding process is simple to control and has higher alignment precision, so that the electrical performance of the backside illuminated CMOS image sensor manufactured later can be improved, and since the TSV pillar 202 is preferentially manufactured, the first substrate and the second substrate are respectively and independently manufactured, the manufacturing process time of the backside illuminated CMOS image sensor can be shortened, the yield can be improved, the damage probability to the backside illuminated CMOS image sensor can be reduced, and the packaging yield can be improved.
Next, referring to fig. 1 and 5, step S4 is performed to remove the substrate to expose the pixel array layer.
Specifically, as shown in fig. 5, the P-type substrate 101 may be removed by using CMP in combination with etching, such as wet etching, to expose the P-type epitaxial layer 102, so that the P-type epitaxial layer 102 has a flat surface, but the method for removing the substrate is not limited thereto, and may also be used by using CMP only, which is not limited thereto.
Next, referring to fig. 1 and 6, step S5 is performed to form a light selection layer on the pixel array layer.
Specifically, the light selecting layer may include filters, such as a color filter including one or a combination of a red (R) filter 301, a green (G) filter 302, and a blue (B) filter 303, and an on-chip lens 400 on the filters, so that incident light of a specific color may be allowed to pass through the arrangement of the filters, thereby realizing light selection, and a condensing effect may be realized through the arrangement of the on-chip lens 400, so as to obtain a better condensing effect.
The material of the on-chip lens 400 may be, for example, an oxide or an organic material, and may be patterned by coating, exposing and developing processes, and then a reflow process is used to obtain the on-chip lens 400 with a convex surface, and the type and distribution of the optical filter, and the material and preparation of the on-chip lens 400 are not limited thereto, and may be selected according to requirements.
Next, referring to fig. 1 and 7, step S6 is performed to provide a transparent substrate, bonding the transparent substrate and the pixel array layer, and forming a cavity 700 between the transparent substrate and the pixel array layer, wherein the cavity covers the light selection layer.
In particular, the light-transmitting substrate may include a glass substrate 500 or a plastic substrate, etc. having good light transmission, and the specific type may be selected according to need.
When the light-transmitting substrate and the pixel array layer are bonded, a patterned support 600 may be formed on the surface of the light-transmitting substrate and/or the pixel array layer, so that the bonded light-transmitting substrate and the pixel array layer form the sealed cavity 700 by the support of the support 600, thereby avoiding the pollution of moisture, air, and the like to the light-selecting layer.
In this embodiment, the support 600 is preferably formed on the surface of the glass substrate 500 by coating, exposing and developing to reduce the contamination to the light selection layer, and the material of the support 600 may be PI, but is not limited thereto.
Next, referring to fig. 1 and 8, step S7 is performed to thin the second substrate to expose the second end of the TSV pillar 202.
Specifically, the method of thinning the second substrate may adopt a CMP method, but is not limited thereto, and the exposed second end of the TSV pillar 202 may be used as an electrical lead-out end to be electrically connected with a subsequent substrate such as a PCB substrate as required.
Further, as required, as shown in fig. 9 and 10, the method may further include the following steps:
forming a re-wiring layer on the second substrate electrically connected to the second end of the TSV column 202;
metal bumps 900 electrically connected to the re-wiring layer are formed on the re-wiring layer.
Specifically, the re-wiring layer may include a dielectric layer 801 and a metal wiring layer 802 located in the dielectric layer 801 and electrically connected to the second end of the TSV pillar 202, where the re-wiring layer may have a single layer of the metal wiring layer 802 or may have multiple layers of the metal wiring layer 802, so as to expand the number of I/os and improve the flexibility of electrical connection. The material, structure and preparation of the rewiring layer are not limited, and may be selected as required.
After the re-wiring layer is formed, the metal bump 900 for electrical extraction may be formed on the re-wiring layer, i.e., a bump array having the metal bump 900 electrically connected to the metal wiring layer 802 may be formed by ball-mounting or solder paste printing and reflow. The material, structure, distribution and preparation of the metal bump 900 are not limited herein, and may be selected according to need.
As an example, the backside illuminated CMOS image sensor may be fabricated in a wafer level chip scale package to improve productivity, wherein the wafer level chip scale may include, for example, 6 inches, 8 inches, 12 inches, etc., and when the backside illuminated CMOS image sensor is in a wafer level chip scale package, a dicing step such as mechanical dicing or laser dicing may be further included to divide the backside illuminated CMOS image sensor at the wafer level into a plurality of individual chips.
The size and dicing method of the wafer level chip are not limited herein, and may be selected as desired.
In summary, in the method for manufacturing the backside illuminated CMOS image sensor according to the present invention, the First substrate having the pixel array layer and the connection circuit layer and the second substrate having the TSV pillar are manufactured separately, and the First substrate and the second substrate are bonded to electrically connect the TSV pillar and the connection circuit layer, and then the light selection layer is manufactured and bonded to the light-transmitting substrate, so that the time for manufacturing the backside illuminated CMOS image sensor can be shortened, the yield can be improved, the alignment accuracy of the TSV pillar and the connection circuit layer can be improved by a First process, the electrical performance of the backside illuminated CMOS image sensor can be improved, the damage probability of the backside illuminated CMOS image sensor can be reduced, and the packaging yield can be improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the back-illuminated CMOS image sensor is characterized by comprising the following steps of:
providing a first substrate, wherein the first substrate comprises a substrate, a pixel array layer positioned on the substrate and a connection circuit layer electrically connected with the pixel array layer;
providing a second substrate, wherein the second substrate comprises a TSV column, a first end of the TSV column is exposed out of the second substrate, and a second end of the TSV column is positioned in the second substrate;
bonding the first substrate and the second substrate, and electrically connecting the first end of the TSV column with the connection circuit layer;
removing the substrate to expose the pixel array layer;
forming a light selection layer on the pixel array layer;
providing a light-transmitting substrate, bonding the light-transmitting substrate with the pixel array layer, and forming a cavity coating the light selection layer between the light-transmitting substrate and the pixel array layer;
thinning the second substrate reveals a second end of the TSV column.
2. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the substrate comprises a P-type substrate, the pixel array layer comprises a P-type epitaxial layer contacted with the P-type substrate, and the doping concentration of the P-type epitaxial layer is smaller than that of the P-type substrate.
3. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the light-transmitting substrate comprises a glass substrate or a plastic substrate.
4. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: and a patterned supporting piece is formed on the surface of the light-transmitting substrate, and the light-transmitting substrate is bonded with the pixel array layer through the supporting piece.
5. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the light selection layer includes an optical filter including one or a combination of a red filter, a green filter, and a blue filter, and an on-chip lens.
6. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the backside illuminated CMOS image sensor is prepared as a wafer level chip scale package.
7. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 6, wherein: a dicing separation step is also included to divide the wafer level backside illuminated CMOS image sensor into a plurality of individual chips.
8. The method of manufacturing a backside illuminated CMOS image sensor according to claim 1, further comprising:
forming a rewiring layer on the second substrate, wherein the rewiring layer is electrically connected with the second end of the TSV column;
and forming a metal bump electrically connected with the rewiring layer on the rewiring layer.
9. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the method for forming the TSV column comprises a laser drilling method or a plasma etching method.
10. The method for manufacturing a backside-illuminated CMOS image sensor according to claim 1, wherein: the TSV pillars include one or a combination of Cu pillars, al pillars, and W pillars.
CN202310646312.9A 2023-06-01 2023-06-01 Preparation method of back-illuminated CMOS image sensor Pending CN116564987A (en)

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