CN116564965A - Inverter based on quasi-enhancement gallium nitride device and manufacturing method thereof - Google Patents

Inverter based on quasi-enhancement gallium nitride device and manufacturing method thereof Download PDF

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Publication number
CN116564965A
CN116564965A CN202310403315.XA CN202310403315A CN116564965A CN 116564965 A CN116564965 A CN 116564965A CN 202310403315 A CN202310403315 A CN 202310403315A CN 116564965 A CN116564965 A CN 116564965A
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load transistor
depletion type
gallium nitride
gate electrode
region
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曹平予
崔苗
赵胤超
李帆
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Xian Jiaotong Liverpool University
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Xian Jiaotong Liverpool University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides an inverter based on a quasi-enhancement type gallium nitride device and a manufacturing method thereof, wherein the inverter comprises a depletion type load transistor and a quasi-enhancement type load transistor, the quasi-enhancement type load transistor is formed by connecting a plurality of diodes in series between a source electrode and a grid electrode of the depletion type load transistor, the diodes are Schottky barrier diodes which are prepared together with the transistor, and a drain electrode of the quasi-enhancement type load transistor is connected with the source electrode and the grid electrode of the depletion type load transistor. The quasi-enhancement type device and the depletion type device are integrated on one epitaxial wafer at the same time, and the quasi-enhancement type device and the depletion type device are connected through metal to form a monolithically integrated inverter circuit.

Description

Inverter based on quasi-enhancement gallium nitride device and manufacturing method thereof
Technical Field
The invention relates to an inverter based on a quasi-enhancement gallium nitride device and a manufacturing method thereof.
Background
Gallium nitride (GaN) materials have large forbidden bandwidths, high electron saturation speeds, and high breakdown voltages. Therefore, a High Electron Mobility Transistor (HEMT) based on an aluminum gallium nitride/gallium nitride (AlGaN/GaN) heterojunction structure has the advantages of large saturation current, small on-state resistance, and the like. Therefore, the GaN HEMT can work under extreme conditions such as high voltage, high frequency, high temperature and the like, and is widely applied to important fields such as automobile industry, aerospace, military equipment and the like.
The GaN HEMT device forms two-dimensional electron gas under the dual actions of spontaneous polarization and piezoelectric polarization, so that a conductive channel between a drain electrode and a source electrode is formed. Due to the presence of an AlGaN/GaN heterojunction, only when a negative voltage is applied to the gate, the two-dimensional electron gas can be depleted, and the device is in an off state, and is therefore called a depletion mode (D-mode) device. The inverter circuit is typically composed of a D-mode device and an enhancement mode (E-mode) device in series, so that it is necessary to prepare an E-mode GaN HEMT, i.e., the device will conduct only if a positive voltage is applied to the gate. At present, four modes for realizing the E-mode GaN HEMT are mainly adopted: gate Recess (Gate process) technology, p-GaN cap technology, fluorine ion implantation technology, and cascades structure technology. The first two methods have higher requirements on etching technology and equipment, and are easy to cause surface damage of devices, thereby causing degradation of the performance of the devices. The fluorine ion implantation technology can reduce the thermal stability of the device, while the cascades technology can increase the resistance of the device and reduce the operating frequency of the device.
Gate grooving:
and etching the AlGaN barrier layer under the gate by using etching technologies such as ICP and the like to deplete the conductive channel, thereby realizing the E-mode device. However, the damage and interface state caused by the etching of the gate trench can affect the performance of the device, so that the problems of increased gate leakage, reduced channel electron mobility, increased on-resistance and the like are caused.
The full etching scheme of the p-GaN layer:
the two-dimensional electron gas is exhausted through the p-GaN layer, and the p-GaN layer below the grid electrode is etched through an ICP (inductively coupled plasma) and other etching technologies. The method still needs to use an etching technology, so that certain etching damage is brought, the interface characteristic of the device is poor, and current collapse is easy to generate.
Fluorine ion implantation technique:
the technology can realize an enhanced device by injecting fluorine ions, and the concentration and depth distribution of the injected fluorine ions are controllable. However, this technique may affect the thermal stability of the device, resulting in deterioration of the high temperature characteristics of the device.
Cascade structure technology:
the technology is to Cascade an enhanced silicon (Si) -based field effect transistor (MOSFET) device and a depletion type GaN device to form a Cascade structure. Therefore, the total on-resistance is the sum of the two, and since the on-resistance of the Si-based device is large, the total on-resistance of the device is large. Meanwhile, the switching speed of the device also depends on the Si-based device, so that the working frequency of the technical scheme is low.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an inverter based on a quasi-enhanced gallium nitride device and a manufacturing method thereof, which do not need etching process, realize high reliability by a simple process and reduce the problems of damage and interface states caused by etching.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an inverter based on a quasi-enhancement gallium nitride device, comprising:
a depletion type first load transistor;
a drain electrode of the depletion type second load transistor is connected to a source electrode and a gate electrode of the depletion type first load transistor; a kind of electronic device with high-pressure air-conditioning system
A plurality of diodes connected in series between the source electrode and the gate electrode of the depletion type second load transistor;
the first load transistor of depletion type and the second load transistor of depletion type are all normally-on gallium nitride high electron mobility transistors;
the depletion type second load transistor and a plurality of diodes form a normally-off quasi-enhancement type gallium nitride high electron mobility transistor.
An inverter based on a quasi-enhanced gallium nitride device comprises a base layer and a passivation layer which are sequentially arranged, wherein the base layer sequentially comprises a silicon substrate, a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer, the base layer is isolated to form a first device region and a second device region, a source electrode, a gate electrode and a drain electrode of a depletion type first load transistor are formed on the first device region, a source electrode, a gate electrode and a drain electrode of a depletion type second load transistor are formed on the second device region, the source electrode, the gate electrode and the drain electrode are formed in the passivation layer, a metal connecting part is formed on the passivation layer, and the metal connecting part is electrically connected with the gate electrode, the source electrode and the drain electrode of the depletion type first load transistor; a plurality of Schottky barriers are formed on the second device region, an insulating part is formed in the second device region, the insulating part isolates the subregions where the Schottky barriers are located from each other, ohmic contact regions are formed on the second device region corresponding to the Schottky barriers, and a current path is formed in the second device region through the ohmic contact regions and the Schottky barriers by source electrodes and drain electrodes of the depletion type second load transistors.
Further, an aluminum oxide structure is formed between the gate electrode and the AlGaN barrier layer.
On the basis, the invention also provides a manufacturing method of the inverter based on the quasi-enhanced gallium nitride device, which comprises the following specific steps:
1) Providing a silicon substrate, and sequentially forming a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer on the silicon substrate to form a base layer;
2) Forming an isolation part in the AlGaN barrier layer and the GaN epitaxial layer to isolate two sides of the isolation part to form a first device region and a second device region, and forming a plurality of insulation parts in the AlGaN barrier layer and the GaN epitaxial layer corresponding to the second device region;
3) Photoetching source electrode and drain electrode region windows of a depletion type first load transistor on an AlGaN barrier layer corresponding to a first device region, photoetching source electrode, drain electrode and ohmic contact region windows of a depletion type second load transistor on an AlGaN barrier layer corresponding to a second device region, and depositing metal on the source electrode and drain electrode region windows of the first device region and the source electrode, drain electrode and ohmic contact region windows of the second device region by adopting an electron beam evaporation process to form source electrode and drain electrode of the depletion type first load transistor, source electrode and drain electrode of the depletion type second load transistor and ohmic contact region;
4) Growing an aluminum oxide insulating layer on the aluminum gallium nitride barrier layer;
5) Photoetching a gate electrode region window of a depletion type first load transistor in a first device region, photoetching a gate electrode region window of a depletion type second load transistor in a second device region, and removing alumina insulation layers of the first device region and the second device region except the gate electrode window;
6) Photoetching a gate electrode region window of a depletion type first load transistor on an AlGaN barrier layer corresponding to a first device region, photoetching a gate electrode and a Schottky contact region window of a depletion type second load transistor on an AlGaN barrier layer corresponding to a second device region, depositing metal on the gate electrode region window of the first device region, the gate electrode and the Schottky contact region window of the second device region by adopting an electron beam evaporation process to form a gate electrode of the depletion type first load transistor and a gate electrode of the depletion type second load transistor, and forming a Schottky barrier;
7) Growing a passivation layer on the AlGaN barrier layer;
8) Openings are formed in the passivation layer at positions corresponding to the gate electrode, the source electrode and the drain electrode of the depletion type first load transistor and at positions corresponding to the gate electrode, the source electrode and the drain electrode of the depletion type second load transistor;
9) And depositing metal on the gate electrode, the source electrode and the drain electrode of the depletion type load transistor to form a metal connection part through an electron beam evaporation process so as to electrically connect the gate electrode, the source electrode and the drain electrode of the depletion type load transistor to form the inverter.
Further, in step 3, the deposited metal is one of a combination of Ti/Al/Ni/Au, a combination of Ti/Al/Ni/TiN, and a combination of Ti/Al/Ni/W; in step 4, the deposited metal is a combination of Ni/TiN or a combination of Ni/Au.
Further, in step 3, after the electron beam evaporation process, a step of annealing in a nitrogen atmosphere is further included.
Further, the annealing treatment temperature is 200-1030 ℃.
Further, the temperature of the annealing treatment was 880 ℃.
Further, the hole opening method in the step 6 adopts one of RIE, ICP, BOE processes.
Further, the isolation portion and the insulation portion in the step 2 are implemented by injecting positively charged ions through an ion implantation process.
The invention has the beneficial effects that:
by changing the structure of the device, a quasi-enhanced GaN HEMT device with positive threshold voltage is prepared, the semiconductor layer does not need to be etched, the requirement on etching equipment is reduced, the circuit preparation flow is simplified, meanwhile, the damage caused by etching is avoided, and the performance of the device is improved; integrating the quasi-enhancement device and the depletion device on an epitaxial wafer at the same time, wherein the quasi-enhancement device and the depletion device are connected through metal to form a monolithically integrated inverter circuit; the method of the present invention can also be combined with MIS HEMT structures to reduce gate electrode leakage.
The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is an equivalent circuit diagram of an inverter according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the equivalent circuit diagram of FIG. 1 with resistors in series to reduce on-state losses;
FIG. 3 is a schematic diagram showing an inverter according to an embodiment of the present invention after completion of the preparation step 2;
FIG. 4 is a schematic diagram showing the structure of an inverter according to an embodiment of the present invention after completing the preparation steps 3-6;
FIG. 5 is a schematic diagram showing an inverter according to an embodiment of the present invention after completing the preparation step 7;
FIG. 6 is a schematic diagram showing the structure of an inverter according to an embodiment of the present invention after completing the preparation steps 8-9;
FIG. 7 is a graph of a transmission characteristic of a quasi-enhanced load transistor according to an embodiment of the present invention;
fig. 8 is a graph of input voltage versus output voltage for a quasi-enhancement mode device forming an inverter according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the positional or positional relationship indicated by the terms such as "upper", "lower", "inner", "outer", etc. are based on the positional or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The structure of the proposed inverter based on the quasi-enhancement mode gallium nitride device according to the present embodiment is shown in fig. 1, and the inverter includes a depletion type first load transistor, a depletion type second load transistor, and a plurality of diodes, wherein the drain electrode 9 of the depletion type second load transistor is connected to the source electrode 8 and the gate electrode 7 of the depletion type first load transistor, and the plurality of diodes are connected in series between the source electrode 11 and the gate electrode 10 of the depletion type second load transistor, and the diodes generate a schottky barrier between the source electrode 11 and the gate electrode 10 through a process, so that the depletion type second load transistor forms the quasi-enhancement mode load transistor. In practical applications, the number of diodes may be set according to practical requirements, and the depletion-type first load transistor and the depletion-type second load transistor are all normally-on gallium nitride high electron mobility transistors, and the threshold voltage of the depletion-type second load transistor becomes positive due to the addition of the schottky barrier, so as to form the normally-on gallium nitride high electron mobility transistor. Preferably, a resistor is connected between the source electrode 8 of the depletion type first load transistor and the drain electrode 9 of the quasi-enhancement type load transistor, and referring to fig. 2, the on-state loss of the inverter can be reduced.
Specifically, the inverter comprises a base layer and a passivation layer 14 which are sequentially arranged, wherein the base layer sequentially comprises a silicon substrate 1, a gallium nitride epitaxial layer 2 and an aluminum gallium nitride barrier layer 3, the base layer is also called an epitaxial layer, the base layer is isolated to form a first device region and a second device region, a source electrode 8, a gate electrode 7 and a drain electrode 6 of a depletion type first load transistor are formed on the first device region, a source electrode 11, a gate electrode 10 and a drain electrode 9 of a depletion type second load transistor are formed on the second device region, the source electrodes 8, 11, the gate electrodes 7, 10 and the drain electrodes 6, 9 of the depletion type first load transistor and the depletion type second load transistor are all formed in the passivation layer 14, a metal connecting part is formed on the passivation layer 14, the metal connecting part 15 is electrically connected with the gate electrode 7 of the depletion type first load transistor, the source electrode 8 and the drain electrode 9 of the depletion type second load transistor, and an aluminum oxide structure is formed between the gate electrode 7 of the depletion type first load transistor and the aluminum gallium nitride barrier layer 3; the second device region is provided with a plurality of Schottky barriers, an insulating part 5 is formed in the second device region, the insulating part 5 isolates the subregions where the Schottky barriers are located from each other, the second device region is also provided with a source electrode 11 and a drain electrode 9 of a second load transistor with a depletion type ohmic contact region 13 corresponding to the Schottky barriers 12, and a current path is formed in the second device region through the ohmic contact region 13 and the Schottky barriers 12. .
Referring to fig. 3 to 6, a specific process for manufacturing the inverter of the present embodiment is as follows:
1) A silicon substrate 1 is provided, and a gallium nitride epitaxial layer 2 and an aluminum gallium nitride barrier layer 3 are sequentially formed on the silicon substrate 1 to form a base layer.
The infrastructure may be prepared by a metal organic chemical vapor deposition MOCVD apparatus of the prior art.
2) An isolation part 4 is formed in the AlGaN barrier layer 3 and the GaN epitaxial layer 2 to isolate two sides of the isolation part 4 to form a first device region and a second device region, and a plurality of insulation parts 5 are formed in the AlGaN barrier layer 3 and the GaN epitaxial layer 2 corresponding to the second device region.
The isolation portion 4 and the insulation portion 5 may be formed by implanting positively charged ions, such as oxygen ions, through an ion implantation process.
3) The source electrode 8 and the drain electrode 6 area window of the first load transistor are photo-etched on the aluminum gallium nitride barrier layer 3 corresponding to the first device area, the source electrode 8 and the drain electrode 11 of the second load transistor are photo-etched on the aluminum gallium nitride barrier layer 3 corresponding to the second device area, the area window of the ohmic contact area is photo-etched on the source electrode 8 and the drain electrode 6 area window of the first device area, the source electrode 11 and the drain electrode 9 of the second device area and the area window of the ohmic contact area are deposited with metal by adopting an electron beam evaporation process, and the deposited metal is one of Ti/Al/Ni/Au combination, ti/Al/Ni/TiN combination, ti/Al/Ni/W combination and the like, and the combination of Ti/Al/Ni/TiN is the best. And after the deposition is finished, carrying out a stripping process to remove redundant metal, wherein the rest metal is an ohmic metal layer, and then annealing in a nitrogen environment, wherein the annealing can be carried out in other inert atmospheres, and the annealing temperature is 200-1030 ℃ and is optimal at 880 ℃. After annealing, ohmic contact electrodes with flat surface morphology are formed, namely, a source electrode 8 and a drain electrode 6 of a depletion type first load transistor, a source electrode 11 and a drain electrode 9 of a depletion type second load transistor are formed, and an ohmic contact region 13 positioned in a second device region is also formed.
The second device region is divided into a plurality of sub-regions by a plurality of insulating portions 5, each ohmic contact 13 being located over a respective one of the sub-regions. The source electrode 11 of the depletion type second load transistor is located in the sub-region at the edge, and after annealing, ti ions and Al ions of the drain electrode 9, the source electrode 11 region and the ohmic contact region 13 of the depletion type second load transistor diffuse into the underlying algan barrier layer 3. The ohmic contact region 13 forms a current path between the aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 of the subregion, and thus the conductive channel is conducted to the ohmic contact region 13 corresponding to the subregion.
4) An aluminum oxide structure (not shown in the drawings) is grown as an insulating layer on the aluminum gallium nitride barrier layer 3 by an atomic layer deposition apparatus ALD. Other insulating materials may also be deposited as insulating layers.
5) And photoetching a gate electrode 7 area window of the depletion type first load transistor in a first device area, photoetching a gate electrode 10 area window of the depletion type second load transistor (namely the quasi-enhancement type load transistor in the step 3) in a second device area, and removing the alumina insulation layer of the first device area except the gate electrode window and the second device area except the gate electrode window through a BOE solution.
6) And photoetching a region window and a gate region window of a Schottky contact region of a depletion type second load transistor (namely a quasi-enhancement type load transistor) and a gate window of a first load transistor on the aluminum gallium nitride barrier layer 3 corresponding to the second device region, depositing metal on a region window of a gate electrode 7 of the first device region, a gate electrode 10 of the second device region and a region window of the Schottky contact region by adopting an electron beam evaporation process, wherein the deposited metal is a combination of Ni/TiN or a combination of Ni/Au, and the combination of Ni/TiN is the best. After the deposition, the gate electrode 7 of the depletion type first load transistor, the gate electrode 10 of the depletion type second load transistor (quasi-enhancement type load transistor), and the schottky barrier 12 are formed by lift-off. Schottky contacts are formed between the gate electrode 7 of the depletion type first load transistor, the gate electrode 10 of the depletion type second load transistor and the algan barrier layer 3. The depletion type second load transistor is thus a complete quasi-enhancement type load transistor.
Due to the formation of the schottky barrier 12, the threshold voltage of the depletion type second load transistor becomes positive to form a quasi-enhancement type load transistor. The diode in the equivalent circuit diagram of the inverter has no physical structure, the body is a schottky barrier 12, and the diode is physically formed between the source electrode 11 and the gate electrode 10 of the enhanced load transistor.
The gate electrode 10 of the quasi-enhancement load transistor, the AlGaN barrier layer 3 and the insulating layer between the two form an MIS structure together, the gate electrode 7 of the depletion type first load transistor, the AlGaN barrier layer 3 and the insulating layer between the two form an MIS structure together, and the MIS structure relieves the electric leakage condition of the gate electrode 10/7.
The schottky barrier 12 and the ohmic contact region 13 serve to conduct between the two sub-regions, so that a current path is formed in each sub-region. The dashed line segment and the arrow direction in fig. 4 are conducting directions, wherein the current path between the corresponding aluminum gallium nitride barrier layer 3 and the gallium nitride epitaxial layer 2 at the horizontal dashed line segment is also called a conducting channel, and the conducting channel has no physical structure.
7) A passivation layer 14 is grown on the aluminum gallium nitride barrier layer 3.
This step may be achieved by growing silicon nitride or other dielectric material by PECVD or LPCVD. The passivation layer 14 structure corresponding to the position between the gate electrode 7 and the source electrode 8 of the depletion type first load transistor, and the passivation layer 14 structure corresponding to the position between the source electrode 8 of the depletion type first load transistor and the drain electrode 9 of the quasi-enhancement type load transistor are used for preventing circuit interconnection, also called a circuit interconnection isolation layer, and improving interface states.
8) One of RIE, ICP, BOE processes is used to open holes in the passivation layer 14 at positions corresponding to the gate electrode 7, source electrode 8, and drain electrode 6 of the depletion type first load transistor and at positions corresponding to the gate electrode 10, source electrode 11, and drain electrode 9 of the enhancement type load transistor.
Although RIE, ICP, BOE is an etching process, the passivation layer 14 is etched in step 6, and the passivation layer acts on the surface of the electrode metal, so that the semiconductor is not affected, and a conductive channel between the AlGaN barrier layer 3 and the GaN epitaxial layer 2 is not etched. The etching process applied in the prior art acts on the semiconductor layer to bring certain etching damage, so that the interface characteristic of the device is poor.
9) A metal connection portion 15 is formed by depositing a metal on the gate electrode 7, the source electrode 8, and the drain electrode 9 of the depletion type first load transistor by an electron beam evaporation process so that the three are electrically connected to form an inverter.
The working procedure of the inverter of this embodiment is as follows: the drain electrode 6 of the depletion type GaN HEMT is connected with a VDD power supply, and the source electrode 8 of the depletion type GaN HEMT is connected with the gate electrode 7 and then connected with the drain electrode 9 of the quasi-enhancement type GaN HEMT. The source electrode 11 of the quasi-enhancement GaN HEMT is grounded. When no voltage is applied to the gate electrode 10 of the quasi-enhancement GaN HEMT, the lower tube is turned off, and the upper tube is in a conducting state at this time because the upper tube is a depletion device, and the output voltage is at a high level at this time. When a positive voltage is applied to the gate electrode 10 of the quasi-enhancement GaN HEMT, the lower tube is in an on state, and the output voltage of the circuit is at a low level. Thus, the circuit can realize the function of inversion.
The proposed quasi-enhancement GaN HEMT and the inverter circuit formed by the same are verified by means of Advanced Design system simulation software. Fig. 1 is an equivalent circuit diagram of a quasi-enhancement GaN HEMT. This structure introduces multiple schottky barriers 12 (i.e., diodes) into the conduction channel, and the quasi-enhancement GaN HEMT will turn on only if the voltage applied by the gate electrode 10 reaches the PN junction turn-on voltage. Therefore, the threshold voltage of the quasi-enhancement GaN HEMT is positive, i.e. the device is a quasi-enhancement device. Fig. 7 is a transmission characteristic curve of a quasi-enhanced GaN HEMT, and the threshold voltage of the quasi-enhanced GaN HEMT is positive. Fig. 8 is a graph of input voltage versus output voltage for a quasi-enhancement mode device forming an inverter, where the output voltage is high when the input voltage is low. When the input voltage is at a high level, the output voltage is at a low level, satisfying the logic relationship of the inverter circuit.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. An inverter based on a quasi-enhancement gallium nitride device, comprising:
a depletion type first load transistor;
a drain electrode of the depletion type second load transistor is connected to a source electrode and a gate electrode of the depletion type first load transistor; a kind of electronic device with high-pressure air-conditioning system
A plurality of diodes connected in series between the source electrode and the gate electrode of the depletion type second load transistor;
the depletion type first load transistor and the depletion type second load transistor are all normally-on gallium nitride high-electron mobility transistors;
the depletion-mode second load transistor and the plurality of diodes form a normally-off quasi-enhancement gallium nitride high electron mobility transistor.
2. An inverter based on a quasi-enhanced gallium nitride device is characterized by comprising a base layer and a passivation layer which are sequentially arranged, wherein the base layer sequentially comprises a silicon substrate, a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer, the base layer is isolated to form a first device region and a second device region, a source electrode, a gate electrode and a drain electrode of a depletion type first load transistor are formed on the first device region, a source electrode, a gate electrode and a drain electrode of a depletion type second load transistor are formed on the second device region, the source electrode, the gate electrode and the drain electrode are formed in the passivation layer, a metal connecting part is formed on the passivation layer, and the metal connecting part is electrically connected with the gate electrode of the depletion type first load transistor, the source electrode and the drain electrode of the depletion type second load transistor; the second device region is provided with a plurality of Schottky barriers, an insulating part is formed in the second device region, the insulating part isolates the subregions where the Schottky barriers are located from each other, the second device region is also provided with ohmic contact areas corresponding to the Schottky barriers, and a current path is formed in the second device region through the ohmic contact areas and the Schottky barriers by the source electrode and the drain electrode of the depletion type second load transistor.
3. An inverter based on a quasi-enhancement mode gallium nitride device according to claim 2, wherein an alumina structure is formed between the gate electrode and the aluminum gallium nitride barrier layer.
4. The manufacturing method of the inverter based on the quasi-enhancement gallium nitride device is characterized by comprising the following specific steps:
1) Providing a silicon substrate, and sequentially forming a gallium nitride epitaxial layer and an aluminum gallium nitride barrier layer on the silicon substrate to form a base layer;
2) Forming an isolation part in the AlGaN barrier layer and the GaN epitaxial layer to isolate two sides of the isolation part to form a first device region and a second device region, and forming a plurality of insulation parts in the AlGaN barrier layer and the GaN epitaxial layer corresponding to the second device region;
3) Photoetching source electrode and drain electrode region windows of a depletion type first load transistor on an AlGaN barrier layer corresponding to the first device region, photoetching source electrode, drain electrode and ohmic contact region windows of the depletion type load transistor on an AlGaN barrier layer corresponding to the second device region, and depositing metal on the source electrode and drain electrode region windows of the first device region and the source electrode and drain electrode and ohmic contact region windows of the second device region by adopting an electron beam evaporation process to form source electrode and drain electrode of the depletion type first load transistor, source electrode and drain electrode of the depletion type second load transistor and ohmic contact region;
4) Growing an aluminum oxide insulating layer on the aluminum gallium nitride barrier layer;
5) Photoetching a gate electrode region window of a depletion type first load transistor in the first device region, photoetching a gate electrode region window of a depletion type second load transistor in the second device region, and removing alumina insulation layers of the first device region and the second device region except the gate electrode window;
6) Photoetching a gate electrode region window of a depletion type first load transistor in the first device region, photoetching a gate electrode region window and a Schottky region window of a depletion type second load transistor in the second device region, depositing metal on the gate electrode region window of the first device region, the gate electrode of the second device region and the Schottky contact region window by adopting an electron beam evaporation process to form a gate electrode of the depletion type first load transistor and a gate electrode of the depletion type second load transistor, and forming a Schottky barrier;
7) Growing a passivation layer on the AlGaN barrier layer;
8) Openings are formed in the passivation layer at positions corresponding to the gate electrode, the source electrode and the drain electrode of the depletion type first load transistor and at positions corresponding to the gate electrode, the source electrode and the drain electrode of the depletion type second load transistor;
9) And depositing metal on the gate electrode, the source electrode and the drain electrode of the depletion type first load transistor to form a metal connection part through an electron beam evaporation process so as to electrically connect the gate electrode, the source electrode and the drain electrode of the depletion type second load transistor to form the inverter.
5. The method of fabricating an inverter based on a quasi-enhancement mode gallium nitride device according to claim 4, wherein in step 3, the metal deposited is one of a combination of Ti/Al/Ni/Au, a combination of Ti/Al/Ni/TiN, a combination of Ti/Al/Ni/W; in step 4, the deposited metal is a combination of Ni/TiN or a combination of Ni/Au.
6. The method of fabricating an inverter based on a quasi-enhancement mode gallium nitride device according to claim 4, further comprising the step of annealing in a nitrogen atmosphere after the electron beam evaporation process in step 3.
7. The method of fabricating an inverter based on a quasi-enhancement mode gallium nitride device according to claim 6, wherein the annealing treatment is at a temperature of 200 ℃ to 1030 ℃.
8. The method of fabricating a quasi-enhancement mode gallium nitride device-based inverter according to claim 7, wherein the annealing is performed at a temperature of 880 ℃.
9. The method of fabricating an inverter based on a quasi-enhancement mode gallium nitride device according to claim 4, wherein the opening method of step 6 uses one of RIE, ICP, BOE processes.
10. The method of fabricating an inverter based on a quasi-enhancement mode gallium nitride device according to claim 4, wherein the isolating and insulating portions of step 2 are implemented by implanting positively charged ions using an ion implantation process.
CN202310403315.XA 2023-04-17 2023-04-17 Inverter based on quasi-enhancement gallium nitride device and manufacturing method thereof Pending CN116564965A (en)

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