CN116564927A - Display panel and preparation method thereof - Google Patents

Display panel and preparation method thereof Download PDF

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Publication number
CN116564927A
CN116564927A CN202210100305.4A CN202210100305A CN116564927A CN 116564927 A CN116564927 A CN 116564927A CN 202210100305 A CN202210100305 A CN 202210100305A CN 116564927 A CN116564927 A CN 116564927A
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China
Prior art keywords
wiring layer
sub
layer
trace
display panel
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CN202210100305.4A
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Chinese (zh)
Inventor
刘娜
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Chengdu Vistar Optoelectronics Co Ltd
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Chengdu Vistar Optoelectronics Co Ltd
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Priority to CN202210100305.4A priority Critical patent/CN116564927A/en
Publication of CN116564927A publication Critical patent/CN116564927A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The application discloses display panel and preparation method thereof, display panel includes: the substrate is continuously arranged on part of the first surface, the first side surface and part of the second surface of the substrate; the trace includes a first trace layer disposed in succession and including a first portion covering a portion of the first surface adjacent the first side and a second portion entirely covering the first side, and a second trace layer disposed in succession and including a third portion covering a portion of the second surface adjacent the first side and a fourth portion entirely covering the second portion of the first trace layer. Through above-mentioned design, the broken probability of wiring can be reduced to this application.

Description

Display panel and preparation method thereof
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel and a preparation method thereof.
Background
The Micro LED display panel is a miniaturized LED array, and compared with an LCD display panel and an OLED display panel, the Micro LED display panel has the advantages of high brightness, high efficiency, short response time, long service life, wide working range and the like, and can be applied to terminal products such as televisions, augmented reality (AR/VR), vehicle-mounted display, wearable equipment, smart phones and the like.
At present, the requirements on the size of Micro LED display panels are higher and higher. In order to realize the Micro LED display panel with a large size, a more common way is to splice a plurality of display panels. In order to make the boundary between two adjacent spliced display panels not obvious during display, the display panels generally realize narrow frames or no frames in a side wiring mode. However, the current side routing method has a problem of easy breakage.
Disclosure of Invention
The application provides a display panel and a preparation method thereof, so as to reduce the probability of wire breakage.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: provided is a display panel including: the substrate is continuously arranged on part of the first surface, the first side surface and part of the second surface of the substrate; the first wiring layer is arranged continuously and comprises a first part covering the part of the first surface adjacent to the first side face and a second part completely covering the first side face, and the second wiring layer is arranged continuously and comprises a third part covering the part of the second surface adjacent to the first side face and a fourth part completely covering the second part of the first wiring layer.
In order to solve the technical problems, another technical scheme adopted by the application is as follows: provided is a method of manufacturing a display panel, including: providing a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and a first side surface connecting the first surface and the second surface; coating a film from one side of the first surface to form a first wiring layer on the first side surface and a part of the first surface adjacent to the first side surface at the same time; coating a film from one side of the second surface to form a second wiring layer on the first wiring layer positioned on the first side surface and a part of the second surface adjacent to the first side surface at the same time; the first and second trace layers are etched to form a plurality of traces, and each trace extends continuously from the first surface to the second surface through the first side.
In the prior art case of distinguishing, the beneficial effect of this application is: the wiring provided by the application comprises a first wiring layer and a second wiring layer, wherein the first wiring layer continuously covers a part of the first surface adjacent to the first side surface and the first side surface; the design mode can enable part of the wires positioned on the first surface and part of the wires positioned on the first side surface to be formed simultaneously, so that the process difficulty is reduced, and meanwhile, the probability of wire breakage is reduced; likewise, the second wiring layer continuously covers a part of the second surface adjacent to the first side surface and the first wiring layer positioned on the first side surface; the design mode can enable partial wires positioned on the second surface and partial wires positioned on the first side surface to be formed simultaneously, and reduces the process difficulty and the probability of wire breakage.
In addition, the first wiring layer comprises a first sub-wiring layer with low conductivity and good bonding force with the substrate, and the bonding force and continuity of the second sub-wiring layer on the first side face can be improved by the first sub-wiring layer, so that the fracture probability of the second sub-wiring layer is reduced. Further, the second wiring layer comprises a fourth sub-wiring layer with low conductivity and higher hardness, and the fourth sub-wiring layer can improve the wear resistance of the wiring so as to reduce the probability of side wiring wear caused by collision and the like in the splicing process.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic structural diagram of an embodiment of a display panel of the present application;
FIG. 2 is a schematic top view of an embodiment of the display panel of FIG. 1;
FIG. 3 is a schematic top view of another embodiment of the display panel of FIG. 1;
FIG. 4 is a schematic structural diagram of another embodiment of a display panel according to the present application;
FIG. 5 is a schematic view of another embodiment of a display panel according to the present application;
FIG. 6 is a schematic flow chart of an embodiment of a method for manufacturing a display panel according to the present disclosure;
fig. 7a is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 6;
fig. 7b is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 6;
fig. 7c is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 6.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1 and 2, fig. 1 is a schematic structural diagram of an embodiment of a display panel of the present application, and fig. 2 is a schematic top view of an embodiment of the display panel of fig. 1. The display panel may be a Micro LED display panel, an LCD display panel, an OLED display panel, etc., and specifically includes a substrate 10 and a plurality of wires 12 arranged at intervals.
The substrate 10 may be understood as an array substrate in which a plurality of pixel driving circuits may be disposed for driving light emitting units (not shown) in a display panel to emit light. The substrate 10 includes a first surface 100 and a second surface 102 disposed opposite each other, and a first side 104 connecting the first surface 100 and the second surface 102. The first surface 100 may be understood as a front surface, i.e. a side surface carrying a plurality of light emitting units; the second surface 102 may be understood as a backside. And generally, the number of the first sides 104 is plural (only one is shown in fig. 1); for example, when the substrate 10 has a cubic structure, the number of the first side surfaces 104 is four.
Preferably, the plurality of traces 12 may be concentrated and distributed on the same first side 104, and no trace 12 is disposed on the other first sides 104. For example, as shown in fig. 2, a plurality of leads on the first surface 100 of the substrate 10 may be led out to the same side edge of the first surface 100, a plurality of pads may be disposed at a side edge position of the first surface 100, a plurality of traces 12 may be arranged at the same first side 104 (as shown in fig. 2), and one pad may be in contact with and electrically connected to one trace 12.
Of course, in other embodiments, the plurality of traces 12 may also be distributed at different first sides 104, that is, at least two first sides 104 may be respectively provided with the plurality of traces 12. For example, as shown in fig. 3, fig. 3 is a schematic top view of another embodiment of the display panel in fig. 1. The plurality of leads on the first surface 100 of the substrate 10 may be led out to different side edges of the first surface 100, and at this time, the positions of different side edges of the first surface 100 may be respectively provided with a plurality of pads, the plurality of traces 12 may be arranged at intervals at different first side surfaces 104, and one pad may be in contact with and electrically connected to one trace 12. Taking fig. 3 as an example, fig. 3 schematically illustrates that two adjacent first sides 104 are respectively provided with a plurality of traces 12; it will be appreciated that in other embodiments, a plurality of traces 12, etc. may be provided at two first sides 104, respectively, that are disposed opposite each other. Each trace 12 is continuously disposed on a portion of the first surface 100, the first side 104, and a portion of the second surface 102 of the substrate 10, that is, from an edge of the first surface 100 to an edge of the second surface 102 through one of the first side 104. As shown in fig. 1, each trace 12 includes a first trace layer 120 and a second trace layer 122, the first trace layer 120 being disposed continuously and including a first portion 1204 covering a portion of the first surface 100 adjacent the first side 104 and a second portion 1206 completely covering the first side 104, and a thickness d1 of the first portion 1204 being greater than a thickness d2 of the second portion 1206. The design manner may enable the partial trace 12 located on the first surface 100 and the partial trace 12 located on the first side 104 to be formed simultaneously, for example, may be formed simultaneously by physical vapor deposition PVD, atomic layer deposition ALD, magnetron sputtering deposition MOCVD, and the like, so as to reduce the process difficulty and reduce the probability of breakage of the trace 12.
Similarly, the second trace layer 122 is disposed continuously and includes a third portion 1224 covering a portion of the second surface 102 adjacent the first side 104 and a fourth portion 1226 completely covering the second portion 1206 of the first trace layer 120 (i.e., the second trace layer 122 covers a surface of the first trace layer 120 disposed opposite the first side 104), and the thickness d3 of the third portion 1224 is greater than the thickness d4 of the fourth portion 1226.
The design manner enables the partial wiring 12 on the second surface 102 and the partial wiring 12 on the first side 104 to be formed simultaneously, for example, the partial wiring 12 can be formed simultaneously by physical vapor deposition PVD, atomic layer deposition ALD, magnetron sputtering deposition MOCVD and the like, so that the process difficulty is reduced and the probability of breakage of the wiring 12 is reduced.
In this embodiment, as shown in fig. 1, the first routing layer 120 may have a single-layer structure, and the material components at each position in the first routing layer 120 are the same; similarly, the second wiring layer 122 may have a single layer structure, and the material composition of each position in the second wiring layer 122 is the same. Optionally, the first trace layer 120 and the second trace layer 122 are made of the same material; for example, the first wiring layer 120 and the second wiring layer 122 are each composed of a diamond-like film and conductive particles doped in the diamond-like film, and the doping concentrations of the conductive particles in the first wiring layer 120 and the second wiring layer 122 are the same.
Of course, in other embodiments, the first routing layer 120 may also have a multi-layer structure. For example, fig. 4 is a schematic structural diagram of another embodiment of a display panel of the present application. As shown in fig. 4, the first routing layer 120 includes a first sub-routing layer 1200 and a second sub-routing layer 1202 that are stacked, and the first sub-routing layer 1200 is located between the substrate 10 and the second sub-routing layer 1202; wherein, the bonding force between the first sub-wiring layer 1200 and the substrate 10 is greater than the bonding force between the second sub-wiring layer 1202 and the substrate 10, and the conductivity of the first sub-wiring layer 1200 is less than the conductivity of the second sub-wiring layer 1202. The second sub-wiring layer 1202 mainly plays a role of conducting electricity, the first sub-wiring layer 1200 mainly plays a role of a buffer layer, and the first sub-wiring layer 1200 can improve the binding force and continuity of the second sub-wiring layer 1202 on the first side 104, so as to reduce the fracture probability of the second sub-wiring layer 1202. In this embodiment, the first wiring layer 120 has a double-layer structure, that is, the first portion 1204 and the second portion 1206 of the first wiring layer 120 have a double-layer structure, and each include a portion of the first sub-wiring layer 1200 and a portion of the second sub-wiring layer 1202.
Optionally, the material of the first sub-wiring layer 1200 includes at least one of titanium Ti and molybdenum Mo; the material of the second sub-trace layer 1202 includes at least one of aluminum Al, copper Cu, and silver Ag. The trace 12 on the first surface 100 may be Ti/Cu, mo/Cu, or the like. The materials of the first sub-trace layer 1200 and the second sub-trace layer 1202 are relatively easy to obtain.
Alternatively, the first sub-trace layer 1200 and the second sub-trace layer 1202 each include a diamond-like film and conductive particles doped in the diamond-like film, and the concentration of the conductive particles in the first sub-trace layer 1200 is less than the concentration of the conductive particles in the second sub-trace layer 1202. The diamond-like film is self-lubricating material, and can have controllable conductivity, internal stress and good wear resistance by doping conductive particles with a certain concentration, so that the probability of abrasion of the wiring 12 in the splicing process is reduced.
Referring to fig. 4 again, the second trace layer 122 has a single-layer structure, and the material of the second trace layer 122 is the same as that of the second sub-trace layer 1202. That is, the second trace layer 122 is made of a material with higher conductivity, and has a conductive function as the second sub-trace layer 1202. The material of the second wiring layer 122 may include at least one of aluminum Al, copper Cu and silver Ag; alternatively, the second trace layer 122 includes a diamond-like film and conductive particles doped in the diamond-like film. At this time, the trace 12 on the second surface 102 may be Cu, and the trace 12 on the first side 104 may be Ti/Cu, mo/Cu, and the like. The design of the second wiring layer 122 can reduce the complexity of the process.
Of course, in other embodiments, the second wiring layer 122 may also have a multi-layer structure. Referring to fig. 5, fig. 5 is a schematic structural diagram of another embodiment of a display panel of the present application. The second trace layer 122 includes a third sub-trace layer 1220 and a fourth sub-trace layer 1222 that are stacked; the fourth sub-trace layer 1222 is located on a side of the third sub-trace layer 1220 facing away from the substrate 10. In the present embodiment, the second wiring layer 122 has a dual-layer structure, that is, the third portion 1224 and the fourth portion 1226 of the second wiring layer 122 are both dual-layer structures, and each include a portion of the third sub-wiring layer 1220 and a portion of the fourth sub-wiring layer 1222.
In the present embodiment, the material of the third sub-trace layer 1220 is the same as the material of the second sub-trace layer 1202. That is, the third sub-trace layer 1220 is made of a material with higher conductivity, and has a conductive function as the second sub-trace layer 1202. The third sub-wiring layer 1220 may include at least one of aluminum Al, copper Cu and silver Ag; alternatively, the third sub-routing layer 1220 includes a diamond-like film and conductive particles doped in the diamond-like film. At this time, the trace 12 on the second surface 102 may be Cu, and the trace 12 on the first side 104 may be Ti/Cu, mo/Cu, and the like. The design of the third sub-routing layer 1220 can reduce the complexity of the process.
The fourth sub-trace layer 1222 has a hardness greater than that of the third sub-trace layer 1220, and the fourth sub-trace layer 1222 has a conductivity less than that of the third sub-trace layer 1220. The introduction of the fourth sub-trace layer 1222 described above may improve the wear resistance of the trace 12 to reduce the probability of wear of the side trace 12 due to collisions or the like during the splicing process. Optionally, the material of the fourth sub-wiring layer 1222 includes at least one of indium tin oxide ITO, indium zinc oxide IZO, and aluminum zinc oxide AZO. At this time, the trace 12 on the second surface 102 may be Cu/ITO, and the trace 12 on the first side 104 may be Ti/Cu/ITO, mo/Cu/ITO, and the like. Alternatively, the fourth sub-routing layer 1222 includes a diamond-like film, and a concentration of conductive particles in the diamond-like film in the fourth sub-routing layer 1222 is greater than or equal to 0. That is, the fourth sub-routing layer 1222 may be composed of only the diamond-like film, or the fourth sub-routing layer 1222 is composed of the diamond-like film and conductive particles doped in the diamond-like film, and the concentration of the conductive particles is less than that of the conductive particles doped in the diamond-like film of the third sub-routing layer 1220. The material of the fourth sub-trace layer 1222 is relatively easy to obtain.
In one application scenario, the thickness D1 of the first sub-trace layer 1200 at the position of the first side 104 is smaller than the sum D2 of the thicknesses of the second sub-trace layer 1202 and the third sub-trace layer 1220; and/or the thickness D3 of the fourth sub-trace layer 1222 is less than the sum D2 of the thicknesses of the second sub-trace layer 1202 and the third sub-trace layer 1220. For example, the thickness D1 of the first sub-trace layer 1200 at the location of the first side 104 is 10nm-100nm (e.g., 20nm, 50nm, 80nm, etc.), the sum D2 of the thicknesses of the second sub-trace layer 1202 and the third sub-trace layer 1220 at the location of the first side 104 is 500nm-5 microns (e.g., 1 micron, 2 microns, 3 microns, 4 microns, etc.), and the thickness D2 of the fourth sub-trace layer 1222 at the location of the first side 104 is 10nm-50nm (e.g., 20nm, 30nm, 40nm, etc.). Since the second sub-trace layer 1202 and the third sub-trace layer 1220 mainly play a role in electric conduction, the first sub-trace layer 1200 plays a role in bottom layer buffering, and the fourth sub-trace layer 1222 plays a role in surface layer abrasion resistance, the thicknesses of the first sub-trace layer 1200 and the fourth sub-trace layer 1222 are not required to be too thick so as to reduce cost.
In another application scenario, the thickness of the first sub-trace layer 1200 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the first sub-trace layer 1200 at the location of the first surface 100; the thickness of the second sub-trace layer 1202 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the second sub-trace layer 1202 at the location of the first surface 100. In general, the thickness of the first routing layer 120 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the first routing layer 120 at the location of the first surface 100.
Similarly, the thickness of the third sub-trace layer 1220 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the third sub-trace layer 1220 at the location of the second surface 102; the thickness of the fourth sub-trace layer 1222 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the fourth sub-trace layer 1222 at the location of the second surface 102. In general, the thickness of the second trace layer 122 at the location of the first side 104 is 30% -70% (e.g., 40%, 50%, 60%, etc.) of the thickness of the second trace layer 122 at the location of the second surface 102.
When the thickness of the trace 12 on the first surface 100 is the same as the thickness of the trace 12 on the second surface 102, the thickness of the trace 12 on the first side 104 is 0.6-1.4 times (e.g., 0.8 times, 1.0 times, 1.2 times, etc.) the thickness of the trace 12 on the first surface 100. The design may be such that the thickness of the trace 12 at the first side 104 differs less from the thickness of the trace 12 at the first surface 100 and the second surface 102.
It should be noted that, in the present application, the thickness of each sub-layer of the trace 12 and the trace 12 located on the first surface 100 and the second surface 102 refers to the thickness along the direction from the first surface 100 to the second surface 102; the thickness of each sub-layer in the trace 12 on the first side 104 refers to the thickness in a direction perpendicular to the first surface 100 to the second surface 102.
Referring to fig. 6, fig. 6 is a schematic flow chart of an embodiment of a method for manufacturing a display panel of the present application, where the method includes the following steps.
S101: a substrate 10 is provided, the substrate 10 comprising a first surface 100 and a second surface 102 disposed opposite each other, and a first side 104 connecting the first surface 100 and the second surface 102.
Specifically, referring to fig. 7a, fig. 7a is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 6. The first surface 100 of the substrate 10 may be regarded as a side surface carrying the light emitting units; and optionally, when the substrate 10 is provided in step S101, the first surface of the substrate 10 may be provided with light emitting units.
S102: the plating is performed from the first surface 100 side to form the first trace layer 120 on the first side 104 and the portion of the first surface 100 adjacent to the first side 104 at the same time.
Specifically, as shown in fig. 7b, fig. 7b is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 6. Before the coating in step S102, the first surface 100 may be protected by the removable first protective adhesive 20 where the coating is not required. At this time, if no trace needs to be formed on all the first side surfaces 104, the first side surfaces 104 on which no trace needs to be formed may be protected by the first protection glue 20 as well. For the second surface 102, since it contacts the coating base, the second surface 102 does not need to be provided with the first protective glue 20. When the plating is performed from the first surface 100 side in the step S102, since the adjacent portions of the first surface 100 and the first side 104 are exposed, the first wiring layer 120 may be formed on the exposed first side 104 and the adjacent portions of the first surface 100 of the exposed first side 104 at the same time; and the thickness d1 of the first trace layer 120 covering the first surface 100 is greater than the thickness d2 of the first trace layer 120 covering the first side 104.
As shown in fig. 7b, when the first trace layer 120 includes the first sub-trace layer 1200 and the second sub-trace layer 1202 that are stacked, the first sub-trace layer 1200 and the second sub-trace layer 1202 may be formed by plating films, respectively; at this time, the step S102 specifically includes: A. plating from the first surface 100 side to form a first sub-trace layer 1200 on the first side 104 and a portion of the first surface 100 adjacent to the first side 104; B. the plating is performed from the first surface 100 side to form the second sub-trace layer 1202 on the first sub-trace layer 1200 on the first surface 100 and the first sub-trace layer 1200 on the first side 104 at the same time.
Optionally, the thickness of the first sub-trace layer 1200 on the first side 104 is smaller than the thickness of the first sub-trace layer 1200 on the first surface 100. The thickness of the second sub-trace layer 1202 on the first side 104 is less than the thickness of the second sub-trace layer 1202 on the first surface 100.
In addition, since the side trace has a requirement for the sheet resistance of the trace, the thickness of the trace at the position of the first side 104 is generally relatively thick, and in order to reduce the temperature rise in the thick film plating process (especially in the magnetron sputtering process), at least one of the first sub-trace layer 1200 and the second sub-trace layer 1202 may be formed by adopting a step-by-step multiple film plating manner, and a cooling process is provided between two adjacent film plating processes. Generally, the second sub-wiring layer 1202 has a relatively thick thickness, so that the second sub-wiring layer 1202 can be formed by at least two film plating processes, only 200nm-500nm of the second sub-wiring layer 1202 is deposited on the first side 104 during each film plating, and an air cooling process such as nitrogen or argon is added between two adjacent film plating processes, and the air cooling time is 20 s-120 s.
Alternatively, at least one of the first sub-trace layer 1200 and the second sub-trace layer 1202 is formed by a plating method of low-speed deposition and high-speed deposition in sequence. Generally, the second sub-trace layer 1202 is thicker, so low-speed deposition and high-speed deposition processes can be used to form the second sub-trace layer 1202. Wherein, during low-speed deposition, the film forming rate can be controlled to be 2-6 nm/S, and the film forming thickness is controlled to be 200 nm-1 micron; the film forming rate can be controlled between 6 and 10nm/S during high-speed deposition. The part of the second sub-wiring layer 1202 formed by low-speed deposition can play a certain role in protection when the rest part of the second sub-wiring layer 1202 is deposited at high speed, so as to reduce the damage to the substrate 10, and be beneficial to reducing the temperature rise degree in the chamber and improving the stability of the device.
S103: plating is performed from the second surface 102 side to form the second wiring layer 122 on the first wiring layer 120 located on the first side 104 and the portion of the second surface 102 adjacent to the first side 104 at the same time.
Specifically, referring to fig. 7c, fig. 7c is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 6. Between steps S102 and S103, it may further include: A. firstly, removing the first protective adhesive 20 covering the first surface 100 in the previous step, and attaching the protective film 22 on one side of the first surface 100 of the substrate 10, wherein the protective film 22 covers one side of the first wiring layer 120 away from the first surface 100; alternatively, the protective film 22 may be a high temperature and plasma resistant film such as flexible polyimide PI, polyethylene terephthalate PET, or the like. Furthermore, the first protective glue 20 thereon may remain for the first side 104 where no traces need to be formed. B. Flipping the whole so that the second surface 102 faces upwards; C. the second protective paste 24 is provided on the second surface 102 at a position where the plating film is not required.
When the plating is performed from the second surface 102 side in the step S103, since part of the second surface 102 and the first wiring layer 120 are exposed, the second wiring layer 122 can be simultaneously formed on the exposed first wiring layer 120 and the part of the second surface 102 adjacent to the exposed first wiring layer 120; and the thickness d3 of the second trace layer 122 covering the second surface 102 is greater than the thickness d4 of the second trace layer 122 covering the first trace layer 120.
When the second trace layer 122 includes the third sub-trace layer 1220 and the fourth sub-trace layer 1222 that are stacked, the third sub-trace layer 1220 and the fourth sub-trace layer 1222 may be formed by plating films, respectively; at this time, the step S103 specifically includes: plating from the second surface 102 side to form a third sub-trace layer 1220 on the first trace layer 120 located on the first side 104 and a portion of the second surface 102 adjacent to the first side 104; plating is performed from the second surface 102 side to form a fourth sub-trace layer 1222 on the third sub-trace layer 1220 located on the second surface 102 and the third sub-trace layer 1220 located on the first side 104 at the same time. Optionally, the thickness of the third sub-trace layer 1220 on the first side 104 is smaller than the thickness of the third sub-trace layer 1220 on the second surface 102; the thickness of the fourth sub-trace layer 1222 on the first side 104 is less than the thickness of the fourth sub-trace layer 1222 on the second surface 102.
In addition, since the side trace has a requirement for the sheet resistance of the trace, the thickness of the trace at the position of the first side 104 is generally thicker, and in order to reduce the temperature rise in the thick film plating process (especially in the magnetron sputtering process), at least one of the third sub-trace layer 1220 and the fourth sub-trace layer 1222 may be formed by adopting a step-by-step multiple film plating method, and a cooling process is provided between two adjacent film plating processes. Generally, the thickness of the third sub-routing layer 1220 is thicker, so that the third sub-routing layer 1220 can be formed by adopting at least two coating processes, only 200nm-500nm of the third sub-routing layer 1220 is deposited on the first side 104 during each coating process, and an air cooling process such as nitrogen or argon is added between two adjacent coating processes, and the air cooling time is 20 s-120 s.
Alternatively, at least one of the third sub-trace layer 1220 and the fourth sub-trace layer 1222 is sequentially formed by a plating method of low-speed deposition and high-speed deposition. Generally, the third sub-trace layer 1220 is thicker, so that the third sub-trace layer 1220 can be formed by using low-speed deposition and high-speed deposition processes. Wherein, during low-speed deposition, the film forming rate can be controlled to be 2-6 nm/S, and the film forming thickness is controlled to be 200 nm-1 micron; the film forming rate can be controlled between 6 and 10nm/S during high-speed deposition. The part of the third sub-routing layer 1220 formed first by low-speed deposition can play a certain role in protecting the rest of the third sub-routing layer 1220 in the high-speed deposition process, so as to reduce the damage to the substrate 10, reduce the temperature rise degree in the chamber, and improve the stability of the device.
S104: the first trace layer 120 and the second trace layer 122 are etched to form a plurality of traces 12, and each trace 12 extends continuously from the first surface 100 to the second surface 102 via the first side 104.
Specifically, between the above-described step S103 and step S104, a step of removing the protective film 22, the second protective paste 24, and the first protective paste 20 located at the first side 104 where no wiring is required to be formed may be further included.
In addition, before the step S104, the first trace layer 120 and the second trace layer 122 are formed as whole conductive layers, and at this time, the plurality of traces 12 may be formed by laser etching or the like.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims (10)

1. A display panel, comprising:
a substrate including a first surface and a second surface disposed opposite to each other, and a first side connecting the first surface and the second surface;
the plurality of wirings are continuously arranged on part of the first surface, the first side surface and part of the second surface of the substrate; the first wiring layer is arranged continuously and comprises a first part covering the part of the first surface adjacent to the first side face and a second part completely covering the first side face, and the second wiring layer is arranged continuously and comprises a third part covering the part of the second surface adjacent to the first side face and a fourth part completely covering the second part of the first wiring layer.
2. The display panel of claim 1, wherein the display panel comprises,
the first wiring layer comprises a first sub-wiring layer and a second sub-wiring layer which are arranged in a stacked manner, and the first sub-wiring layer is positioned between the substrate and the second sub-wiring layer;
the bonding force between the first sub-wiring layer and the substrate is greater than the bonding force between the second sub-wiring layer and the substrate, and the conductivity of the first sub-wiring layer is smaller than that of the second sub-wiring layer.
3. The display panel of claim 2, wherein the display panel comprises,
the material of the first sub-wiring layer comprises at least one of titanium Ti and molybdenum Mo; the material of the second sub-wiring layer comprises at least one of aluminum Al, copper Cu and silver Ag;
or the first sub-wiring layer and the second sub-wiring layer respectively comprise a diamond-like film and conductive particles doped in the diamond-like film, and the concentration of the conductive particles in the first sub-wiring layer is smaller than that in the second sub-wiring layer.
4. The display panel of claim 2, wherein the display panel comprises,
the second wiring layer comprises a third sub-wiring layer, and the material of the third sub-wiring layer is the same as that of the second sub-wiring layer.
5. The display panel of claim 4, wherein the display panel comprises,
the second wiring layer further comprises a fourth sub-wiring layer, and the fourth sub-wiring layer is positioned on one side, away from the substrate, of the third sub-wiring layer; the hardness of the fourth sub-wiring layer is greater than that of the third sub-wiring layer, and the conductivity of the fourth sub-wiring layer is smaller than that of the third sub-wiring layer.
6. The display panel of claim 5, wherein the display panel comprises,
the material of the fourth sub-wiring layer comprises at least one of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO) and Aluminum Zinc Oxide (AZO);
or, the fourth sub-wiring layer comprises a diamond-like film, and the concentration of the conductive particles in the diamond-like film in the fourth sub-wiring layer is greater than or equal to 0.
7. The display panel of claim 5, wherein the display panel comprises,
the thickness of the first part of the first wiring layer is larger than that of the second part, and the thickness of the third part of the second wiring layer is larger than that of the fourth part; preferably, the thickness of the first sub-trace layer at the first side position is smaller than the sum of the thicknesses of the second sub-trace layer and the third sub-trace layer;
and/or the thickness of the fourth sub-wiring layer at the first side position is smaller than the sum of the thicknesses of the second sub-wiring layer and the third sub-wiring layer;
and/or the thickness of the first wiring layer covering the first side surface is 30% -70% of the thickness of the first wiring layer covering the first surface; the thickness of the second wiring layer covering the first wiring layer is 30% -70% of the thickness of the second wiring layer covering the second surface.
8. A method for manufacturing a display panel, comprising:
providing a substrate, wherein the substrate comprises a first surface and a second surface which are arranged oppositely, and a first side surface connecting the first surface and the second surface;
coating a film from one side of the first surface to form a first wiring layer on the first side surface and a part of the first surface adjacent to the first side surface at the same time;
coating a film from one side of the second surface to form a second wiring layer on the first wiring layer positioned on the first side surface and a part of the second surface adjacent to the first side surface at the same time;
the first and second trace layers are etched to form a plurality of traces, and each trace extends continuously from the first surface to the second surface through the first side.
9. The method according to claim 8, wherein,
the first wiring layer comprises a first sub-wiring layer and a second sub-wiring layer which are arranged in a stacked manner, and the second wiring layer comprises a third sub-wiring layer and a fourth sub-wiring layer which are arranged in a stacked manner;
at least one of the first sub-wiring layer, the second sub-wiring layer, the third sub-wiring layer and the fourth sub-wiring layer is formed in a step-by-step film plating mode, and a cooling process is arranged between two adjacent film plating processes; and/or the number of the groups of groups,
at least one of the first sub-wiring layer, the second sub-wiring layer, the third sub-wiring layer and the fourth sub-wiring layer is formed in a film plating mode of low-speed deposition and high-speed deposition in sequence.
10. The method according to claim 8, wherein,
the step of plating a film from the second surface side to form a second wiring layer on the first wiring layer located on the first side and a portion of the second surface adjacent to the first side simultaneously includes: attaching a protective film on one side of the first surface of the substrate, wherein the protective film covers one side of the first wiring layer, which is away from the first surface, of the first wiring layer;
the step of plating a film from the second surface side to form a second wiring layer on the first wiring layer located on the first side and a portion of the second surface adjacent to the first side at the same time includes: and removing the protective film.
CN202210100305.4A 2022-01-27 2022-01-27 Display panel and preparation method thereof Pending CN116564927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210100305.4A CN116564927A (en) 2022-01-27 2022-01-27 Display panel and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210100305.4A CN116564927A (en) 2022-01-27 2022-01-27 Display panel and preparation method thereof

Publications (1)

Publication Number Publication Date
CN116564927A true CN116564927A (en) 2023-08-08

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