CN110600528A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN110600528A CN110600528A CN201910950580.3A CN201910950580A CN110600528A CN 110600528 A CN110600528 A CN 110600528A CN 201910950580 A CN201910950580 A CN 201910950580A CN 110600528 A CN110600528 A CN 110600528A
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- thin film
- display panel
- transistor substrate
- display
- field effect
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/88—Dummy elements, i.e. elements having non-functional features
Abstract
The application provides a display panel and a display device. The display panel includes: the display device comprises a thin film field effect transistor substrate, wherein a first power supply wire is formed on the thin film field effect transistor substrate at least on the opposite side of a display area of a display panel; the packaging cover plate is arranged opposite to the thin film field effect transistor substrate, and a conductive medium layer is formed on one side, close to the thin film field effect transistor substrate, of the packaging cover plate; the conductive medium layer is abutted and contacted with the first power supply wire when the packaging cover plate and the thin film field effect transistor substrate are packaged. Therefore, the voltage division effect of the resistor on the first power supply wiring is reduced, the IR voltage drop of the power supply is reduced, and the problem of uneven display brightness of the existing display panel is solved. In addition, with the reduction of the IR voltage drop of the power supply, the anode potential of an OLED device in the display panel cannot be obviously increased, and the risk that the thin film field effect transistor works in a linear region under high gray scale is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Organic Light Emitting Diodes (OLEDs) have been widely used in various display devices due to their advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, nearly 180 ° viewing angle, and wide temperature range
At present, the traditional display device has the problem of uneven brightness, so that the visual effect of the display device is poor, and the visual experience of a user is seriously influenced.
In a conventional display device, ELVDD power traces are arranged in a grid pattern, and ELVSS power traces are connected to the cathode of the OLED device by peripheral metal wires, which may be equivalent to a mesh pattern. The drive current for driving the Thin Film Transistor (TFT) drives the OLED to emit light, and the drive current is derived from the positive voltage V of the power supplyVDDVoltage V flowing to negative pole of power supplyVSS. As the display panel of the display device is larger and larger, the cathode voltage V is transmittedVSSThe ELVSS power supply line has resistance voltage division, so that the power supply cathode voltage VVSSThe values of (a) may be different at the far end of the display panel and at the near end of the display panel. And when the driving current flows through the power supply cathode voltage VVSSWhen the ELVSS power supply is routed, an IR Drop (IR Drop) of the power supply is generated according to ohm's law, resulting in a negative voltage V of the power supply to be input to pixels (pixels) at different positions in the display panelVSSDifferent, the problem of uneven display brightness is caused, so that the visual effect of the display device is poor, and the visual experience of a user is seriously influenced.
Content of application
The application provides a display panel and a display device to solve the problem of uneven display brightness in the traditional display device.
In a first aspect, the present application provides a display panel comprising:
a thin film field effect transistor substrate, wherein a first power supply wire is formed on the thin film field effect transistor substrate at least at the opposite side of the display area of the display panel;
the packaging cover plate is arranged opposite to the thin film field effect transistor substrate, and a conductive medium layer is formed on one side, close to the thin film field effect transistor substrate, of the packaging cover plate; the conductive medium layer is abutted and contacted with the first power supply wire when the packaging cover plate and the thin film field effect transistor substrate are packaged.
Optionally, a first concave region is formed on the package cover plate corresponding to the display region;
and the conductive medium layer on the outer side of the edge of the first sunken area is abutted and contacted with the first power supply wire when the packaging cover plate is packaged with the thin film field effect transistor substrate.
Optionally, the package cover further includes: the display device comprises a glass substrate and an insulating covering layer, wherein the insulating covering layer is formed on one side, close to the thin film field effect transistor substrate, of the glass substrate, the conducting medium layer is formed on the insulating covering layer, and the first concave area is formed between the insulating covering layer and the conducting medium layer and corresponds to the display area.
Optionally, the insulating cover layer and the conductive medium layer are recessed in a position corresponding to the display region; or the conductive medium layer is concave corresponding to the display area.
Optionally, the package cover further includes: the conductive medium layer is formed on one side, close to the thin film field effect transistor substrate, of the glass substrate, and the first concave area is formed on the conductive medium layer corresponding to the display area.
Optionally, a second concave region is formed on the thin film transistor substrate corresponding to the display region, and the first power trace is disposed on an outer side of an edge of the second concave region.
Optionally, the first power trace is formed on the thin film transistor substrate on the opposite side of the display region.
Optionally, a continuous first power trace is formed on the thin film transistor substrate at three sides corresponding to the display region.
Optionally, the conductive medium layer is made of an indium tin oxide material or a metal mesh material.
Optionally, the method further comprises: the power supply integrated chip is positioned on one side of the opening of the first power supply wiring and is electrically connected with the first power supply wiring.
Optionally, the method further comprises: and the OLED device is arranged on the thin film field effect transistor substrate and is close to one side of the packaging cover plate.
Optionally, a cap layer is formed on the cathode of the OLED device, and a coverage of the cap layer is smaller than a coverage of the cathode of the OLED device, so that the first power trace is electrically connected to the cathode of the OLED device that is not covered with the cap layer.
In a second aspect, the present application provides a display device comprising: the display panel as shown in the first aspect and the embodiment of the first aspect.
The application provides a display panel and display device, through setting up first power line on thin film field effect transistor substrate at least at the opposite side of display area of display panel, thin film field effect transistor substrate corresponds to the edge of display area promptly. The conductive medium layer is arranged on the packaging cover plate and close to one side of the thin film field effect transistor substrate, so that when the packaging cover plate is packaged with the thin film field effect transistor substrate, the conductive medium layer and the first power supply wiring can be abutted to contact, the resistor on the conductive medium layer and the resistor on the first power supply wiring are connected in parallel, the voltage division effect of the resistor on the first power supply wiring is reduced, the IR voltage drop of the power supply is reduced, and the power supply negative electrode voltage V of the pixels at different positions in the display panel is input in the mannerVSSThe phase difference is small, the problem that the display brightness of the existing display panel is not uniform is solved, the visual effect of the display device comprising the display panel is improved, and the visual experience of a user is improved. In addition, with the reduction of the IR voltage drop of the power supply, the anode potential of an OLED device in the display panel cannot be obviously increased, and the risk that a thin film field effect transistor works in a linear region under high gray scale is avoided, so that the service life of the device is prolonged, the cost of the device is reduced, and the normal display of the display device is ensured.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1a is a schematic structural diagram of a display panel according to an embodiment of the present application;
FIG. 1b is an exploded view of the display panel of FIG. 1 a;
fig. 2 is a schematic view of a first power trace in a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic view of a first power trace in a display panel according to an embodiment of the present disclosure;
FIG. 4 is a cross-sectional view taken along the line a-a in FIG. 1 a;
FIG. 5 is a cross-sectional view taken along the line a-a in FIG. 1 a;
FIG. 6 is a cross-sectional view taken along the line a-a in FIG. 1 a;
FIG. 7 is a cross-sectional view taken along the line a-a in FIG. 1 a;
FIG. 8 is a cross-sectional view taken along line a-a of FIG. 1 a;
fig. 9 is a schematic structural diagram of a power supply ic in a display panel according to an embodiment of the present disclosure;
FIG. 10 is a cross-sectional view taken along line a-a of FIG. 1 a;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present application.
Reference numerals:
1-a display panel;
10-a thin film field effect transistor substrate; 20, packaging a cover plate;
a-direction; AA — display area;
an, a1, a2, A3 — a first power trace; bm — second power supply trace;
21-a conductive dielectric layer; 22-a glass substrate; 23-an insulating cover layer;
BB — first recessed area; CC — second recessed area;
30-power integrated chip; c1, C2, C3-connecting line;
40-an OLED device; 100-display device.
Detailed Description
To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a alone, b alone, or c alone, may represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b and c in combination, wherein a, b and c may be single or multiple.
In order to solve the problem of uneven display brightness in the conventional display device, the application provides a display panel and a display device, which can eliminate the voltage V of a power supply cathodeVSSImproving the negative voltage V of the power supplyVSSThe IR drop phenomenon of the first power supply wiring enables the brightness of the display panel to be displayed uniformly, and the actual requirement of high-quality visual effect is met.
Next, a specific structure of the display panel will be described in detail by way of specific examples.
Illustratively, the present application provides a display panel 1. Fig. 1a is a schematic structural diagram of a display panel 1 according to an embodiment of the present application, and fig. 1b is an exploded view of the display panel 1 in fig. 1 a. As shown in fig. 1a and 1b, the display panel 1 of the present application may include: a thin film transistor substrate 10 and a package cover 20. The package cover plate 20 is disposed opposite to the thin film transistor substrate 10. The thin film transistor substrate 10 has a first power trace An (i.e., An ELVSS power trace) formed on at least An opposite side of a display area (AA) of the display panel 1.
The first power trace An may include at least two sides corresponding to the display area AA along the length direction of the display area AA, or at least two sides corresponding to the display area AA along the width direction of the display area AA.
In the following, the first power trace An is exemplified by two possible implementation forms.
Fig. 2 and fig. 3 respectively show schematic diagrams of the first power trace An on the thin film transistor substrate 10. For convenience of illustration, the first power trace An in fig. 2 and 3 includes at least two sides corresponding to the display area AA along the length direction of the display area AA.
In one possible implementation form, as shown in fig. 2, the first power trace An, i.e., a1 and a2 in fig. 2, is optionally formed on the thin film transistor substrate 10 on the opposite side of the display area AA. For convenience of illustration, the first power trace An is illustrated in fig. 1b using a1 and a 2.
In another possible implementation form, as shown in fig. 3, the thin film transistor substrate 10 is optionally formed with continuous first power traces An, i.e., a1, a2, and A3 in fig. 3, on three sides corresponding to the display area AA.
In this application, a conductive medium layer 21 is formed on the package cover plate 20 near the thin film transistor substrate 10, that is, the conductive medium layer 21 is laid on the package cover plate 20. The specific material of the conductive medium layer 21 is not limited in this application. Optionally, the conductive medium layer 21 is made of Indium Tin Oxide (ITO) or metal mesh.
In addition, the coverage of the conductive medium layer 21 may be greater than or equal to the coverage corresponding to the display area AA, which is not limited in the present application. For convenience of illustration, in fig. 1b, the coverage of the conductive medium layer 21 may be larger than that of the display area AA.
When the package cover plate 20 is packaged with the thin film transistor substrate 10, the conductive dielectric layer 21 and the first power trace An may be in abutting contact, so that the resistor on the conductive dielectric layer 21 is connected in parallel with the resistor on the first power trace An.
As will be understood by those skilled in the art, the third resistor is a resistor formed by connecting the first resistor and the second resistor in parallel, and the resistance of the third resistor is smaller than that of the first resistor, and the resistance of the second resistor is also smaller than that of the second resistor. Therefore, the parallel resistance formed by the abutting contact between the conductive medium layer 21 and the first power trace An is smaller than the resistance on the first power trace An.
Compared with the resistor on the first power supply wiring An in the prior art, the voltage division of the resistor on the first power supply wiring An in the application is small, the IR voltage drop of the power supply is reduced, and the power supply cathode voltage V input to the pixels at different positions in the display panel 1 is enabled to be lowerVSSThe phase difference is small, the problem of uneven display brightness is solved, the visual effect of the display device 100 is improved, and the visual experience of a user is improved.
In addition, in the prior art, the voltage V of the negative electrode of the power supply is VVSSThe first power trace An of (a) will generate a larger IR drop of the power. In the present application, the voltage V of the negative electrode of the power supplyVSSThe first power trace An of (a) reduces the IR drop of the power. Therefore, compared with the positive voltage V of the power supply in the prior artVDDAnd the voltage V of the negative electrode of the power supplyVSSVoltage difference therebetween, the positive electrode voltage V of the power supply in this applicationVDDAnd the voltage V of the negative electrode of the power supplyVSSThe voltage difference between the two electrodes can be greatly reduced, so that the anode potential of the OLED device 40 can not be obviously increased, and the risk that the thin film field effect transistor works in a linear region under high gray scale is avoided.
The layout of the second power trace Bm may include various layouts. Optionally, as shown in fig. 2 and fig. 3, second power traces Bm are further formed on the thin film transistor substrate 10 in the display area AA corresponding to the display panel 1, and the second power traces Bm are arranged in a grid shape.
The application provides a display panel, through setting up first power line on the opposite side of display area at least at display panel's on the thin film field effect transistor substrate, thin film field effect transistor substrate corresponds to the edge of display area promptly. The conductive medium layer is arranged on the packaging cover plate and close to one side of the thin film field effect transistor substrate, so that when the packaging cover plate is packaged with the thin film field effect transistor substrate, the conductive medium layer and the first power supply wiring can be abutted to contact, the resistor on the conductive medium layer and the resistor on the first power supply wiring are connected in parallel, the voltage division effect of the resistor on the first power supply wiring is reduced, the IR voltage drop of the power supply is reduced, and the power supply negative electrode voltage V of the pixels at different positions in the display panel is input in the mannerVSSThe phase difference is small, the problem that the display brightness of the existing display panel is not uniform is solved, the visual effect of the display device comprising the display panel is improved, and the visual experience of a user is improved. In addition, with the reduction of the IR voltage drop of the power supply, the anode potential of an OLED device in the display panel cannot be obviously increased, and the risk that a thin film field effect transistor works in a linear region under high gray scale is avoided, so that the service life of the device is prolonged, the cost of the device is reduced, and the normal display of the display device is ensured.
On the basis of the embodiments shown in fig. 1a, 1b to 3, the display panel 1 of the present application includes various implementation forms. In the following, three possible implementations are adopted, and a specific structure of the display panel 1 of the present application is illustrated with reference to fig. 4 to 6, 7 and 8. Fig. 4 to 8 each show a schematic cross-sectional view of the display panel 1 of the present application.
In one possible implementation, as shown in fig. 4 to 6, the package cover 20 is formed with a first recess area BB corresponding to the display area AA. The conductive medium layer 21 on the outer side of the edge of the first recessed area BB is in abutting contact with the first power trace An when the package cover plate 20 is packaged with the thin film transistor substrate 10, so that the parallel connection between the resistor on the conductive medium layer 21 on the package cover plate 20 and the resistor on the first power trace An is realized.
The conductive medium layer 21 may be disposed on the package cover plate 20 by using various manufacturing processes. Two possible specific configurations of the package cover 20 of the present application are illustrated in conjunction with fig. 4-5 and fig. 6.
Fig. 4 and 5 show cross-sectional views in the direction a-a in fig. 1a, respectively. As shown in fig. 4 and 5, the package cover plate 20 may further include, in addition to the conductive medium layer 21: a glass substrate 22 and an insulating coating (OC) layer 23. The insulating cover layer 23 is formed on the glass substrate 22 on one side close to the thin film transistor substrate 10, the conductive medium layer 21 is formed on the insulating cover layer 23 through manufacturing processes such as sputtering or patch, and the first recess area BB is formed on the insulating cover layer 23 and the conductive medium layer 21 corresponding to the display area, so that the conductive medium layer 21 on the outer side of the edge of the first recess area BB can be abutted and contacted with the first power supply line An.
The insulating cover layer 23 is arranged to facilitate the adhesion of the conductive medium layer 21, and the material of the insulating cover layer 23 is not limited in the present application. The shape, area, depth, and other information of the first recessed area BB may be set according to actual situations, which is not limited in this application. The manufacturing process of the first recess area BB is not limited in the present application.
As shown in fig. 4, optionally, the insulating cover layer 23 and the conductive medium layer 21 are recessed corresponding to the display area AA, so that the conductive medium layer 21 is conveniently and directly laid on the insulating cover layer 23, the complexity of the manufacturing process is reduced, and the manufacturing is simple and feasible.
For example, in the present application, a layer of the insulating cover layer 23 may be laid on the glass substrate 22, and then the insulating cover layer 23 corresponding to the inner area of the display area AA is developed by using HTMASK, so that the area of the insulating cover layer 23 opposite to the display area AA is higher than the inner area corresponding to the display area AA, thereby forming the insulating cover layer 23 in a concave shape, and further increasing the transmittance of the glass substrate 22.
It should be noted that, in order to ensure the thickness of the package cover 20, the conductive medium layer 21 generally includes a conductive organic material.
As shown in fig. 5, optionally, the conductive medium layer 21 is recessed corresponding to the display area AA, so that the insulating cover layer 23 is directly laid on the glass substrate 22, and only the conductive medium layer 21 is made into a recessed shape, thereby saving the complexity of the manufacturing process and being simple and feasible to manufacture.
Fig. 6 shows a cross-section in the direction a-a in fig. 1 a. As shown in fig. 6, the package cover plate 20 may further include, in addition to the conductive medium layer 21: a glass substrate 22. The conductive medium layer 21 is formed on the glass substrate 22 near the thin film transistor substrate 10 by sputtering or surface mounting, and the like, and the conductive medium layer 21 is formed with the first recess area BB corresponding to the display area AA, that is, the conductive medium layer 21 is recessed, so that the conductive medium layer 21 on the outer side of the edge of the first recess area BB and the first power trace An can be abutted and contacted.
In another possible implementation, fig. 7 shows a cross-section in the direction a-a in fig. 1 a. As shown in fig. 7, the thin film transistor substrate 10 forms a second concave region CC corresponding to the display region AA, and the first power trace An is disposed on the outer side of the edge of the second concave region CC, so that the parallel connection between the resistor on the conductive dielectric layer 21 on the package cover plate 20 and the resistor on the first power trace An is realized.
For convenience of illustration, the package cover 20 in fig. 7 is illustrated as including a glass substrate 22, an insulating cover layer 23 and a conductive medium layer 21.
In another possible implementation, fig. 8 shows a cross-section in the direction a-a in fig. 1 a. As shown in fig. 8, in combination with the above two manners, not only the package cover plate 20 and the conductive medium layer 21 form a first recess area BB corresponding to the display area AA, but also the thin film transistor substrate 10 forms a second recess area CC corresponding to the display area AA, and the first power trace An is disposed on An outer side of An edge of the second recess area CC, so that when the package cover plate 20 and the thin film transistor substrate 10 are packaged, the conductive medium layer 21 on the outer side of the edge of the first recess area BB and the first power trace An disposed on the outer side of the edge of the second recess area CC can be in abutting contact, and a parallel connection between a resistance on the conductive medium layer 21 on the package cover plate 20 and a resistance on the first power trace An is realized.
For convenience of explanation, in fig. 8, the package cover 20 is illustrated by taking the package cover 20 in fig. 6 as an example, and the thin film transistor substrate 10 is illustrated by taking the thin film transistor substrate 10 in fig. 7 as an example.
On the basis of the embodiments shown in fig. 1a, 1b to 8, fig. 9 shows a schematic partial structure diagram of the display panel 1 of the present application. Alternatively, FIG. 9 shows a cross-sectional view in the direction a-a of FIG. 1 a. As shown in fig. 9, the display panel 1 of the present application may further include: a power integrated circuit chip (power integrated circuit chip)30, wherein the power integrated chip 30 is located at one side of the opening of the first power trace An, which is convenient for the power integrated chip 30 to be electrically connected with the first power trace An, so that the power integrated chip 30 can transmit power negative voltage V to the display panel 1 through the first power trace AnVSS. In addition, the power ic 30 is electrically connected to the second power trace Bm (ELVDD power trace), so that the power ic 30 can transmit the power positive voltage V to the display panel 1 through the first power trace AnVDD。
The position of the power integrated chip 30 on the thin film transistor substrate 10 is not limited in the present application. For convenience of explanation, fig. 9 illustrates a partial structure of the display panel 1 based on fig. 3. In fig. 9, the electrical connection between the power integrated chip 30 and the first power trace An is realized through C1 and C2. Through C3, an electrical connection between the power integrated chip 30 and the second power trace Bm is achieved.
In order to facilitate the power supply integrated chip 30 to be electrically connected to the first power supply trace An and the second power supply trace Bm respectively, optionally, in this application, a lower step is disposed on one side of the thin film transistor substrate 10 to place the power supply integrated chip 30, so that the power supply integrated chip 30 can input signals to the display panel 1 conveniently.
On the basis of the above described embodiments shown in fig. 1a, 1 b-9, fig. 10 shows a cross-sectional view in the direction a-a in fig. 1 a. Optionally, with reference to fig. 10, optionally, the display panel 1 of the present application may further include: and the OLED device 40 is arranged on the thin film field effect transistor substrate 10 and close to one side of the packaging cover plate 20. That is, the OLED device 40 is sandwiched between the thin film transistor substrate 10 and the encapsulation cover plate 20.
For convenience of explanation, in fig. 10, the package cover 20 is illustrated by taking the package cover 20 in fig. 6 as an example, and the thin film transistor substrate 10 is illustrated by taking the thin film transistor substrate 10 in fig. 7 as an example.
The specific structure of the OLED device 40 is not limited in this application. For example, the OLED device 40 includes an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and a cathode, which are sequentially formed on the thin film transistor substrate 10.
In addition, in order to protect the coverage of the cathode, a capping layer (CPL) is optionally formed on the cathode of the OLED device 40 (not illustrated in fig. 10). And the coverage range of the cap layer is smaller than that of the cathode of the OLED device 40, so that the cathode of the OLED device 40 leaves An area in contact with the first power trace An, and thus the first power trace An can be electrically connected with the cathode of the OLED device 40 which is not covered with the cap layer.
Illustratively, the present application also provides a display device 100. Fig. 11 is a schematic structural diagram of a display device provided in the present application. As shown in fig. 11, the display device 100 of the present application may include: such as the display panel 1 shown in the embodiment of fig. 1a, 1 b-10.
The display device 100 includes, but is not limited to, a display, a mobile phone (mobile phone), a tablet computer (Pad), a computer, a Virtual Reality (VR) terminal, an Augmented Reality (AR) terminal, and the like, and is not limited herein.
The display device provided by the application comprises the display panel as described above, and the first power supply wiring is arranged on the thin film field effect transistor substrate at least at the opposite side of the display area of the display panel, namely the thin film field effect transistor substrate corresponds to the edge of the display area. The conductive medium layer is arranged on the packaging cover plate and close to one side of the thin film field effect transistor substrate, so that when the packaging cover plate is packaged with the thin film field effect transistor substrate, the conductive medium layer and the first power supply wiring can be abutted to contact, the resistor on the conductive medium layer and the resistor on the first power supply wiring are connected in parallel, the voltage division effect of the resistor on the first power supply wiring is reduced, the IR voltage drop of the power supply is reduced, and the power supply negative electrode voltage V of the pixels at different positions in the display panel is input in the mannerVSSThe phase difference is small, the problem that the display brightness of the existing display panel is not uniform is solved, the visual effect of the display device comprising the display panel is improved, and the visual experience of a user is improved. In addition, with the reduction of the IR voltage drop of the power supply, the anode potential of an OLED device in the display panel cannot be obviously increased, and the risk that a thin film field effect transistor works in a linear region under high gray scale is avoided, so that the service life of the device is prolonged, the cost of the device is reduced, and the normal display of the display device is ensured.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (13)
1. A display panel, comprising:
a thin film field effect transistor substrate, wherein a first power supply wire is formed on the thin film field effect transistor substrate at least at the opposite side of the display area of the display panel;
the packaging cover plate is arranged opposite to the thin film field effect transistor substrate, and a conductive medium layer is formed on one side, close to the thin film field effect transistor substrate, of the packaging cover plate; the conductive medium layer is abutted and contacted with the first power supply wire when the packaging cover plate and the thin film field effect transistor substrate are packaged.
2. The display panel according to claim 1, wherein the package cover plate is formed with a first recess region corresponding to the display region;
and the conductive medium layer on the outer side of the edge of the first sunken area is abutted and contacted with the first power supply wire when the packaging cover plate is packaged with the thin film field effect transistor substrate.
3. The display panel of claim 2, wherein the encapsulating cover further comprises: the display device comprises a glass substrate and an insulating covering layer, wherein the insulating covering layer is formed on one side, close to the thin film field effect transistor substrate, of the glass substrate, the conducting medium layer is formed on the insulating covering layer, and the first concave area is formed between the insulating covering layer and the conducting medium layer and corresponds to the display area.
4. The display panel according to claim 3, wherein the insulating cover layer and the conductive medium layer are recessed in a direction corresponding to the display region; or the conductive medium layer is concave corresponding to the display area.
5. The display panel of claim 2, wherein the encapsulating cover further comprises: the conductive medium layer is formed on one side, close to the thin film field effect transistor substrate, of the glass substrate, and the first concave area is formed on the conductive medium layer corresponding to the display area.
6. The display panel of claim 1, wherein the thin film transistor substrate forms a second recessed region corresponding to the display region, and the first power trace is disposed on an outer side of an edge of the second recessed region.
7. The display panel of claim 1, wherein the first power trace is formed on the thin film transistor substrate on an opposite side of the display area.
8. The display panel of claim 1, wherein the thin film transistor substrate has a continuous first power trace formed on three sides corresponding to the display area.
9. The display panel according to any of claims 1-8, wherein the conductive medium layer is an indium tin oxide material or a metal mesh material.
10. The display panel according to any one of claims 1 to 8, further comprising: the power supply integrated chip is positioned on one side of the opening of the first power supply wiring and is electrically connected with the first power supply wiring.
11. The display panel according to any one of claims 1 to 8, further comprising: and the OLED device is arranged on the thin film field effect transistor substrate and is close to one side of the packaging cover plate.
12. The display panel of claim 11, wherein a cap layer is formed on the cathode of the OLED device, and a coverage of the cap layer is smaller than a coverage of the cathode of the OLED device, so that the first power trace is electrically connected to the cathode of the OLED device that is not covered by the cap layer.
13. A display device, comprising: the display panel of any one of claims 1-12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910950580.3A CN110600528A (en) | 2019-10-08 | 2019-10-08 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910950580.3A CN110600528A (en) | 2019-10-08 | 2019-10-08 | Display panel and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110600528A true CN110600528A (en) | 2019-12-20 |
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Application publication date: 20191220 |