CN116564916A - Bump packaging structure of drive IC and preparation method thereof - Google Patents
Bump packaging structure of drive IC and preparation method thereof Download PDFInfo
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- CN116564916A CN116564916A CN202310337921.6A CN202310337921A CN116564916A CN 116564916 A CN116564916 A CN 116564916A CN 202310337921 A CN202310337921 A CN 202310337921A CN 116564916 A CN116564916 A CN 116564916A
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- electrode welding
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract description 36
- 239000010931 gold Substances 0.000 claims abstract description 35
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052737 gold Inorganic materials 0.000 claims abstract description 29
- 238000003466 welding Methods 0.000 claims abstract description 27
- 239000010936 titanium Substances 0.000 claims abstract description 25
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims abstract description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 17
- 238000004544 sputter deposition Methods 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000013077 target material Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001709 polysilazane Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/13166—Titanium [Ti] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to the technical field of semiconductor packaging, and discloses a bump packaging structure of a drive IC and a preparation method thereof, wherein the bump packaging structure comprises an electrode welding pad arranged on one side surface of a wafer; the passivation layer is arranged on the surface of the electrode welding pad and covers the periphery of the electrode welding pad, and the passivation layer is provided with a passivation opening exposing the top surface of the electrode welding pad part; the UBM layer covers the surface of the passivation layer and the top surface of the electrode bonding pad which is partially exposed; the gold bump is arranged on the surface of the UBM layer and used for packaging a wafer; wherein, the UBM layer is sequentially provided with a titanium layer, a titanium tungsten layer and a gold layer from the near to the far from the electrode welding pad. According to the invention, under the condition of not affecting conduction, the Ti layer is increased by changing the UBM layer structure, the thickness of the TiW layer is reduced, the binding force of the bump is increased, and meanwhile, the surface stress of the wafer is ensured to be in a negative state, so that the bump at the output end can be ensured to be thinner and thinner.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a bump packaging structure of a driving IC and a preparation method thereof.
Background
With the rapid growth of the industry of display panels in China, the industries of advanced packaging of driving chips, wafer manufacturing of driving ICs, and driving chip design of the corresponding industry in China have been rapidly developed in recent years. In the driving IC packaging stage, since the panel driving is high current, the bumps of the input and output, especially the bumps of the output end are more, and the finer the smaller the bumps (as shown in fig. 1: a complete driving IC chip), the smaller the CD is to 10 micrometers (um) if etching is performed, and the lower limit may be close to 8um, and if the bonding force is not very firm, the bumps are easy to drop (as shown in the virtual coil in fig. 1) or warp (as shown in fig. 2) after high-pressure cleaning, polishing, and the like.
The sputtering layers of the current industry mainstream drive IC gold bump package are TiW (titanium tungsten) and Au (gold), wherein the TiW sputtering thickness is larger than 3000A, and the Au sputtering thickness is 800-1000A. As in fig. 3. (North China PVD purchased by several driving IC packaging factories in China is TiW+Au cavity configuration), as the bumps become thinner, and particularly below 12 um, the PVD layer bonding force of the structure becomes weaker, and the process risk point becomes higher.
Disclosure of Invention
The invention aims to: aiming at the problems in the prior art, the invention provides a bump packaging structure of a drive IC and a preparation method thereof, wherein a UBM layer in the bump packaging structure consists of a titanium layer, a titanium tungsten layer and a gold layer.
The technical scheme is as follows: the invention provides a bump packaging structure of a drive IC, wherein an electrode welding pad is arranged on one side surface of a wafer; the passivation layer is arranged on the surface of the electrode welding pad and covers the periphery of the electrode welding pad, and the passivation layer is provided with a passivation opening exposing the top surface of the electrode welding pad part; the UBM layer covers the surface of the passivation layer and the top surface of the electrode bonding pad which is partially exposed; the gold bump is arranged on the surface of the UBM layer and used for packaging a wafer; wherein, the UBM layer is sequentially provided with a titanium layer, a titanium tungsten layer and a gold layer from the near to the far from the electrode welding pad; wherein the thickness of the titanium layer is below 100A, the thickness of the titanium tungsten layer is below 2000A, and the thickness of the gold layer is 950-1050A.
Further, the height h of the gold bump is 9-10 um, and the minimum width w is 12-um.
Further, the electrode pad is made of Al.
The invention also provides a preparation method of the bump packaging structure, which comprises the following steps:
step one, forming an electrode welding pad on one side surface of a wafer; forming a passivation layer on the surface of the electrode welding pad, wherein a passivation opening is formed in the passivation layer, and the passivation opening exposes the top surface of the electrode welding pad;
bombarding a metal target by using high-speed ions, sputtering a titanium layer on the surface of the passivation layer and the surface of part of the electrode welding pad, sputtering a titanium tungsten layer on the surface of the titanium layer, and finally sputtering a gold layer on the surface of the titanium tungsten layer;
and thirdly, coating photoresist on the surface of the UBM layer, exposing and developing, and windowing the position of the preset bump on the photoresist.
And fourthly, forming a gold bump at the windowed part through electroplating, and then removing the photoresist to obtain the bump packaging structure.
The beneficial effects are that: according to the invention, through a new UBM layer design, under the condition of not affecting conduction, the UBM layer structure is changed: the Ti+TiW+Au drive IC wafer level packaging UBM layer has the advantages that the thickness of each layer is controlled specifically, the current is distributed better conveniently, the binding force of the bumps is greatly increased, the surface stress of the wafer is ensured to be in a negative state, the size of a chip is reduced, the unit output port is improved, the bumps at the output end can be thinner and thinner, and the thickness of the bumps at the output end can be less than 10 um.
Drawings
FIG. 1 is a schematic diagram of a photograph of a conventional driver IC microscope at 50 times;
FIG. 2 is a schematic diagram of a conventional driving IC with a poor bonding force, which is a photo of a skewed head after subsequent grinding;
FIG. 3 is a schematic diagram of a conventional bump package structure of a driving IC;
fig. 4 is a schematic diagram of a bump package structure of a driving IC prepared in embodiment 1;
fig. 5 is a graph showing the comparison of sheet resistances of the bump package structure (left) of the driving IC prepared in embodiment 1 and the bump package structure (right) of the conventional driving IC;
fig. 6 is a graph showing front thrust data and a thrust breaking layer comparison after respective operations of the bump package structure (left) of the driving IC having the same thickness, the bump package structure (middle) of the driving IC prepared in embodiment 1, and the bump package structure (right) of the driving IC which is the main stream in the industry;
fig. 7 is a graph showing the comparison of the thrust data and the thrust breaking layer of the rear side of the driving IC with the same thickness (left), the driving IC prepared in embodiment 1 (middle), and the driving IC of the main stream in the industry (right);
illustration of: 1, a wafer; 2 electrode pads; 3, passivation layer; a 4UBM layer; 5 gold bumps; a layer of 41 titanium; 42 titanium tungsten layer; and 43 gold layer.
Detailed Description
The present invention will be described in detail with reference to the accompanying drawings.
Embodiment 1:
the embodiment provides a bump package structure of a driving IC, which comprises an electrode pad 2 positioned on one side surface of a wafer 1; the passivation layer 3 is positioned on the surface of the electrode welding pad 2, a passivation opening is formed in the passivation layer, and the passivation opening exposes the top surface of the electrode welding pad 2; UBM layer 4 located on the surface of passivation layer 3 and part of electrode pad 2; and gold bumps 5 for wafer packaging provided on the surface of the UBM layer 4.
The wafer 1 may comprise a wide variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the wafer 1 may also be made of an electrically non-conductive material, such as glass, plastic, or sapphire wafer.
The passivation layer 3 is formed of at least one of insulating layers such as silicon oxide, silicon nitride, silicon oxynitride, polysilazane, polyvinyl phenol, polyimide, and siloxane.
The UBM layer 4 is sequentially a titanium layer 41, a titanium tungsten layer 42 and a gold layer 43 from the near to the far from the electrode pad 2; wherein the titanium layer 41 has a thickness of 50 a; the titanium tungsten layer 42 has a thickness of 1950 a; the gold layer 43 has a thickness of 1000 a.
The present embodiment also provides a method for manufacturing a bump package structure of a driving IC, including the steps of:
step one, forming an electrode welding pad 2 on one side surface of a wafer 1; forming a passivation layer 3 on the surface of the electrode bonding pad 2, wherein a passivation opening is formed in the passivation layer 3, and the passivation opening exposes the top surface of the electrode bonding pad 2;
secondly, bombarding a metal target material by using high-speed ions, sputtering a titanium layer 41 on the surface of the passivation layer 3 and the surface of part of the electrode welding pad 2, sputtering a titanium tungsten layer 42 on the surface of the titanium layer 41, and finally sputtering a gold layer 43 on the surface of the titanium tungsten layer 42 to form a UBM layer 4;
and thirdly, coating photoresist on the surface of the UBM layer 4, exposing and developing, and windowing the position of the preset bump on the photoresist.
And fourthly, forming a gold bump 5 at the windowing part, and then removing the photoresist to obtain a bump packaging structure.
In the first step, the passivation layer 3 may be formed by deposition methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., or by droplet discharging, printing or spin coating, or by stacking these films to form the passivation layer 3.
In the third and fourth steps, the gold bump 5 is manufactured by uniformly coating the photoresist on the UBM layer 4 by spin coating using a coater, performing soft baking and shaping to form a film by using a hot plate, removing the unexposed area by using a developing solution in an exposure-developing manner to expose the predetermined bump position, i.e. the window opening position, and preparing the gold bump 5 by at least one process selected from a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), sputtering, electroplating, electroless plating, or ball plating, and removing the residual photoresist and organic contamination on the surface of the gold bump 5.
Embodiment 2:
the present embodiment is substantially the same as embodiment 1, except that in UBM layer 4 in the present embodiment, titanium layer 41 has a thickness of 70 a; titanium tungsten layer 42 thickness 1700 a; except that the thickness of the gold layer 43 is 1000 a, the present embodiment is identical to embodiment 1, and will not be described here.
Embodiment 3:
the present embodiment is substantially the same as embodiment 1, except that in UBM layer 4 in the present embodiment, titanium layer 41 has a thickness of 90 a; titanium tungsten layer 42 is 1500 a thick; except that the thickness of the gold layer 43 is 1000 a, the present embodiment is identical to embodiment 1, and will not be described here.
The performance of the bump package structure of the driving IC prepared in embodiment 1 was compared with that of a conventional one (Tiw +au for UBM layer) as follows:
as shown in fig. 5, the comparison of square resistances of the conventional bump package structure (right) of the driving IC and the bump package structure (left) of the driving IC prepared in embodiment 1, the resistance of the ti+tiw+au UBM layer provided by the present invention is equivalent to the resistance of the industry standard Tiw +au UBM layer in the thickness range (thickness is 100 a or less) of the Ti layer defined by the present invention by comparing the square resistances of the ti+tiw+au UBM layer with the industry standard Tiw +au UBM layer in the present invention.
The bump package structure (Ti 50 a+tiw1950 a+au 1000 a) of the driver IC prepared in embodiment 1, the bump package structure (tiw2000 a+au 1000 a) of the driver IC having the same thickness, and the bump package structure (Tiw 3350 a+au 850 a) of the driver IC which is the main current in the industry were subjected to the comparison of the driver IC package operation with the bump critical dimension of 12 um:
comparing the bump bonding force with the shearmode thrust fracture layer diagram (tested by DAGE 4000), the UBM layer of Ti 50 A+TiW 1950 A+Au 1000A is compared with the UBM layer of TiW 2000 A+Au 1000A: the Ti+TiW+Au UBM layer structure designed by the invention has higher bonding force under the same thickness; ti 50 a+tiw 1950 a+au 1000 a and Tiw 3350 a+au 850 a (thickness of the mainstream UBM layer in industry): compared with the mainstream thickness structure in industry, the Ti+TiW+Au UBM layer structure designed by the invention has higher bonding force. The bonding force of the bump packaging structure of the driving IC designed by the invention is greatly improved, and meanwhile, the shearmode thrust breaking layer diagram of the Ti+TiW+Au UBM layer designed by the invention completely accords with the uniform push-out non-breaking (see the front thrust data and thrust breaking layer diagram of FIG. 6 and the side thrust data and thrust breaking layer diagram of FIG. 7).
The foregoing embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and to implement the same, not to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (4)
1. The bump packaging structure of the drive IC is characterized in that an electrode welding pad (2) is arranged on one side surface of a wafer (1); the passivation layer is arranged on the surface of the electrode welding pad (2) and covers the periphery of the electrode welding pad, and the passivation layer (3) is provided with a passivation opening exposing part of the top surface of the electrode welding pad (2); a UBM layer (4) covers the surface of the passivation layer (3) and the top surface of the electrode pad (2) which is partially exposed; the gold bump (5) is arranged on the surface of the UBM layer (4) and used for packaging a wafer; wherein, the UBM layer (4) is sequentially provided with a titanium layer (41), a titanium tungsten layer (42) and a gold layer (43) from the near to the far from the electrode welding pad (2); wherein the thickness of the titanium layer (41) is below 100A, the thickness of the titanium tungsten layer (42) is below 2000A, and the thickness of the gold layer (43) is 950-1050A.
2. The bump package structure of the driving IC according to claim 1, wherein the gold bump (5) has a height h of 9-10 um and a minimum width w of 12 um.
3. The bump package structure of the driver IC according to claim 1, wherein the electrode pad (2) is made of Al.
4. A method of manufacturing the bump package of any one of claims 1 to 3, comprising the steps of:
step one, forming an electrode welding pad (2) on one side surface of a wafer (1); forming a passivation layer (3) on the surface of the electrode welding pad (2), wherein a passivation opening is formed in the passivation layer (3), and the passivation opening exposes the top surface of the electrode welding pad (2);
secondly, bombarding the metal target material by using high-speed ions, firstly sputtering a titanium layer (41) on the surface of the passivation layer (3) and the surface of part of the electrode welding pad (2), then sputtering a titanium tungsten layer (42) on the surface of the titanium layer (41), and finally sputtering a gold layer (43) on the surface of the titanium tungsten layer (42);
coating photoresist on the surface of the UBM layer (4), exposing and developing, and windowing the position of a preset bump on the photoresist;
and fourthly, forming a gold bump (5) at the windowing part through electroplating, and then removing the photoresist to obtain the bump packaging structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310337921.6A CN116564916A (en) | 2023-03-31 | 2023-03-31 | Bump packaging structure of drive IC and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310337921.6A CN116564916A (en) | 2023-03-31 | 2023-03-31 | Bump packaging structure of drive IC and preparation method thereof |
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| CN116564916A true CN116564916A (en) | 2023-08-08 |
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| CN202310337921.6A Pending CN116564916A (en) | 2023-03-31 | 2023-03-31 | Bump packaging structure of drive IC and preparation method thereof |
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| CN1600495A (en) * | 2004-10-27 | 2005-03-30 | 新磊微制造股份有限公司 | structure of stannum-gold solder in method for joining conductors and application |
| JP2006237278A (en) * | 2005-02-25 | 2006-09-07 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| US20080136019A1 (en) * | 2006-12-11 | 2008-06-12 | Johnson Michael E | Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications |
| US20160308100A1 (en) * | 2015-04-17 | 2016-10-20 | Chipmos Technologies Inc | Semiconductor package and method of manufacturing thereof |
| CN115527926A (en) * | 2021-08-27 | 2022-12-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
-
2023
- 2023-03-31 CN CN202310337921.6A patent/CN116564916A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1600495A (en) * | 2004-10-27 | 2005-03-30 | 新磊微制造股份有限公司 | structure of stannum-gold solder in method for joining conductors and application |
| JP2006237278A (en) * | 2005-02-25 | 2006-09-07 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
| US20080136019A1 (en) * | 2006-12-11 | 2008-06-12 | Johnson Michael E | Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications |
| US20160308100A1 (en) * | 2015-04-17 | 2016-10-20 | Chipmos Technologies Inc | Semiconductor package and method of manufacturing thereof |
| CN115527926A (en) * | 2021-08-27 | 2022-12-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of manufacturing semiconductor device |
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