TWI450363B - Improving the formation for tsv backside interconnects by modifying carrier wafers - Google Patents

Improving the formation for tsv backside interconnects by modifying carrier wafers Download PDF

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Publication number
TWI450363B
TWI450363B TW099119021A TW99119021A TWI450363B TW I450363 B TWI450363 B TW I450363B TW 099119021 A TW099119021 A TW 099119021A TW 99119021 A TW99119021 A TW 99119021A TW I450363 B TWI450363 B TW I450363B
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Taiwan
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wafer
semiconductor
semiconductor wafer
score
carrier
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TW099119021A
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Chinese (zh)
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TW201101429A (en
Inventor
黃宏麟
蕭景文
許國經
陳承先
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台灣積體電路製造股份有限公司
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Description

積體電路結構的形成方法Method for forming integrated circuit structure

本發明係有關於積體電路結構，且特別是有關於穿矽導電插塞(through-silicon vias)，且更有關於於晶圓之背面上形成內連線結構，並連接至穿矽導電插塞。The present invention relates to an integrated circuit structure, and more particularly to through-silicon vias, and more particularly to forming an interconnect structure on the back side of the wafer, and connecting to the via conductive plug Plug.

自從積體電路發明，半導體工業已經歷持續的快速成長，這是由於各種電子元件(即，電晶體、二極體、電阻器、電容器等)之整合密度的持續增進。佔最大原因地，此整合密度之增進來自於最小特徵尺寸(minimum feature size)的一再縮小化，允許了更多元件整合至所給予之晶片面積中。Since the invention of the integrated circuit, the semiconductor industry has experienced continuous rapid growth due to the continuous increase in the integrated density of various electronic components (ie, transistors, diodes, resistors, capacitors, etc.). For the most part, this increase in integration density comes from the repeated miniaturization of the minimum feature size, allowing more components to be integrated into the given wafer area.

這些整合增進實際上為實質二維的，其中所整合之元件所佔的體積實質於半導體晶圓之表面上。雖然，微影製程之顯著的增進已於二維積體電路製作中造成相當大的進步，但在二維中所能達到的密度有著物理限制。這些限制其中之一為製造這些元件所需之最小尺寸。並且，當更多的元件放進一晶片中時，需要更多複雜的設計。These integration enhancements are actually two-dimensional in nature, where the integrated components occupy a volume that is substantially on the surface of the semiconductor wafer. Although the significant enhancement of the lithography process has made considerable progress in the fabrication of two-dimensional integrated circuits, the density that can be achieved in two dimensions has physical limitations. One of these limitations is the minimum size required to make these components. Also, when more components are placed in a wafer, more complex designs are needed.

另一附加限制來自於隨著元件數目之增加，元件間內連線之數目與長度隨之顯著增加。當內連線之長度與數目增加時，電路之RC延遲與功率損耗(power consumption)亦增加。Another additional limitation comes from the fact that as the number of components increases, the number and length of interconnects between components increases significantly. As the length and number of interconnects increase, the RC delay and power consumption of the circuit also increases.

為解決上述限制，常使用的方法包括使用三維積體電路(3DICs)及堆疊晶粒(stacked dies)。穿矽導電插塞(through-silicon vias，TSVs)因而用於三維積體電路及堆疊晶粒之中。在此情形下，穿矽導電插塞常用以將一晶粒上之積體電路連接至該晶粒之背面。此外，穿矽導電插塞還用以透過晶粒之背面提供積體電路接地之短接地路徑(short grounding path)，晶粒之背面可能覆蓋有接地金屬薄膜(grounded metallic film)。To solve the above limitations, commonly used methods include the use of three-dimensional integrated circuits (3DICs) and stacked dies. Through-silicon vias (TSVs) are used in three-dimensional integrated circuits and stacked dies. In this case, the via conductive plug is commonly used to connect an integrated circuit on a die to the back side of the die. In addition, the through-hole conductive plug is also used to provide a short grounding path of the integrated circuit ground through the back surface of the die, and the back surface of the die may be covered with a grounded metallic film.

背面穿矽導電插塞線路之傳統製程遭遇一些阻礙。請參照第1圖，其顯示製作背面內連線結構之中間階段的剖面圖，矽晶圓100包括穿矽導電插塞102。矽晶圓100透過膠106設置於承載晶圓104之上。凸塊下金屬層(UBM)108係沉積於矽晶圓100之上。承載晶圓104一般大於矽晶圓100，凸塊下金屬層108因而亦沉積於承載晶圓之上。既然承載晶圓104具有斜面區(beveled areas)110，凸塊下金屬層108將包括沉積於斜面區110上之部分，而凸塊下金屬層108之這些部分易於刮傷(scratching)與脫層(peeling)。在製程中，顯示於第1圖中之結構可藉由自動控制裝置(robots)而鉗緊或轉移。當凸塊下金屬層108位於斜面區110上之部分被鉗子或自動控制裝置鉗緊或接觸時，顆粒可能脫離並汙染晶圓。The traditional process of wearing a conductive plug line on the back encounters some obstacles. Referring to FIG. 1, a cross-sectional view showing an intermediate stage of fabricating a backside interconnect structure includes a via conductive plug 102. The germanium wafer 100 is disposed over the carrier wafer 104 via the glue 106. An under bump metallurgy (UBM) 108 is deposited over the germanium wafer 100. The carrier wafer 104 is generally larger than the germanium wafer 100, and the under bump metal layer 108 is thus deposited over the carrier wafer. Since the carrier wafer 104 has beveled areas 110, the under bump metal layer 108 will include portions deposited on the bevel region 110, and portions of the under bump metal layer 108 are susceptible to scratching and delamination. (peeling). In the process, the structures shown in Figure 1 can be clamped or transferred by robots. When the portion of the under bump metallization 108 on the beveled region 110 is clamped or contacted by pliers or an automatic control device, the particles may detach and contaminate the wafer.

另一問題是尋找刻痕(notch)上之困難。第2A圖顯示第1圖所示結構之上視圖。刻痕112係為了對準之目的而形成於矽晶圓100中。第2B圖顯示第2A圖所示結構之剖面圖，其中剖面圖係顯示沿著第2A圖中之切線2B-2B之切面。可發現凸塊下金屬層108亦沉積於承載晶圓104透過刻痕112而露出之部分上。既然凸塊下金屬層108非透明的，例如是光學步進機(photo steppers)之儀器常無法找到刻痕112，因而無法進行後續製程所需之對準。Another problem is the difficulty of finding a notch. Figure 2A shows a top view of the structure shown in Figure 1. The score 112 is formed in the germanium wafer 100 for the purpose of alignment. Fig. 2B is a cross-sectional view showing the structure shown in Fig. 2A, wherein the cross-sectional view shows the section along the tangent 2B-2B in Fig. 2A. It can be seen that the under bump metal layer 108 is also deposited on the portion of the carrier wafer 104 that is exposed through the scribes 112. Since the under bump metal layer 108 is non-transparent, an instrument such as a photo stepper often cannot find the score 112, and thus the alignment required for subsequent processes cannot be performed.

為了形成背面穿矽導電插塞連接(backside TSV connection)，顯示於第1圖之結構需放置於反應室中，並由靜電吸盤(electrostatic chuck，ESC或E-chuck)固定。然而，承載晶圓104一般由玻璃製成而無法穩固地固定於靜電吸盤之上。這部分是因為玻璃中之可移動離子不充足。因此，業界亟需能克服或減輕上述問題之背面內連線結構及製造方法。In order to form a backside TSV connection, the structure shown in Fig. 1 needs to be placed in the reaction chamber and fixed by an electrostatic chuck (ESC or E-chuck). However, the carrier wafer 104 is typically made of glass and cannot be securely attached to the electrostatic chuck. This is partly because there are not enough mobile ions in the glass. Therefore, there is a need in the industry for a backside interconnect structure and a manufacturing method that can overcome or alleviate the above problems.

本發明一實施例提供一種積體電路結構的形成方法，包括：提供一半導體晶圓，包括一第一刻痕，自該半導體晶圓之一邊緣延伸進入該半導體晶圓；以及將一承載晶圓設置於該半導體晶圓之上，其中該承載晶圓包括一第二刻痕，位於該承載晶圓之中，且其中將該承載晶圓之設置步驟包括使至少一部分的該第一刻痕與至少一部分的該第二刻痕重疊。An embodiment of the present invention provides a method for forming an integrated circuit structure, including: providing a semiconductor wafer including a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer; and a carrier crystal a circular array disposed on the semiconductor wafer, wherein the carrier wafer includes a second scribe, located in the carrier wafer, and wherein the step of placing the carrier wafer includes at least a portion of the first scribe Overlaid with at least a portion of the second score.

本發明一實施例提供一種積體電路結構的形成方法，包括：提供一半導體晶圓；以及將一承載晶圓設置於該半導體晶圓之上，其中該承載晶圓面對該半導體晶圓之一側面與該承載晶圓之一邊緣形成一銳角。An embodiment of the present invention provides a method for forming an integrated circuit structure, including: providing a semiconductor wafer; and disposing a carrier wafer on the semiconductor wafer, wherein the carrier wafer faces the semiconductor wafer One side forms an acute angle with one of the edges of the carrier wafer.

本發明一實施例提供一種基底電路結構的形成方法，包括：提供一半導體晶圓；以及將一承載晶圓設置於該半導體晶圓之上，其中該承載晶圓具有一電阻率，小於約1x108 Ohm-cm。An embodiment of the present invention provides a method for forming a substrate circuit structure, including: providing a semiconductor wafer; and disposing a carrier wafer on the semiconductor wafer, wherein the carrier wafer has a resistivity of less than about 1×10 8 Ohm-cm.

亦討論其他實施例。Other embodiments are also discussed.

以下，將詳細討論本發明實施例之形成與使用方式。然應注意的是，實施例提供許多可應用於廣泛應用面之發明特點。所討論之特定實施例僅為舉例說明製作與使用本發明實施例之特定方式，不可用以限制本發明實施例之範圍。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。Hereinafter, the formation and use of the embodiments of the present invention will be discussed in detail. It should be noted, however, that the embodiments provide a number of inventive features that can be applied to a wide range of applications. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the invention, and are not intended to limit the scope of the embodiments. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

本發明實施例提供用以形成一新穎的連接至穿矽導電插塞(TSV，或可為穿半導體導電插塞(through-semiconductor vias))背面內連線結構之方法。將說明一實施例之製作流程，並討論實施例之變化。在各圖式及實施例的說明中，相似的標號將用以標示相似的元件。Embodiments of the present invention provide a method for forming a novel backside interconnect structure that is connected to a via conductive plug (TSV, or may be a through-semiconductor vias). The production flow of an embodiment will be explained, and variations of the embodiment will be discussed. In the description of the drawings and the embodiments, like reference numerals will

請參照第3A圖，提供晶圓2，其包括基底10。適合的基底10可為半導體基底，例如塊材矽基底(bulk silicon substrate)，然而基底10可包括其他的半導體材料，例如三族、四族、及/或五族之元素。例如是電晶體之積體電路元件(以方塊4顯示)可形成在基底10之前表面(即，第3A圖中朝上之表面)。內連線結構(interconnect structure)12係形成於基底10之上，且可連接至積體電路元件，其中內連線結構12包括形成於其中之金屬線路及插塞(未顯示)。金屬線路及插塞可由銅或銅合金製成，且可使用所週知的鑲嵌製程形成。內連線結構12可包括一般常見之層間介電層(ILDs)及金屬間介電層(IMDs)。Referring to FIG. 3A, a wafer 2 is provided that includes a substrate 10. Suitable substrate 10 can be a semiconductor substrate, such as a bulk silicon substrate, although substrate 10 can include other semiconductor materials, such as tri-, tetra-, and/or five-element elements. For example, an integrated circuit component of the transistor (shown as block 4) can be formed on the front surface of the substrate 10 (i.e., the upwardly facing surface in Figure 3A). An interconnect structure 12 is formed over the substrate 10 and is connectable to the integrated circuit component, wherein the interconnect structure 12 includes metal lines and plugs (not shown) formed therein. The metal lines and plugs can be made of copper or a copper alloy and can be formed using well-known damascene processes. The interconnect structure 12 can include generally common interlayer dielectric layers (ILDs) and inter-metal dielectric layers (IMDs).

穿矽導電插塞20係形成於基底10之中，並自基底10之前表面(第3A圖中朝上之表面)延伸進入基底10之中。在一第一實施例中，如第3A圖所示，穿矽導電插塞20係使用先插塞方法(via-first approach)而形成，且係於底部金屬化層(bottom metallization layer，即所知之M1)形成之前形成。因此，穿矽導電插塞20穿過基底10及內連線結構12。絕緣層22係形成於穿矽導電插塞20之側壁上，且電性隔離穿矽導電插塞20與基底10。絕緣層22可由常用之介電材料形成，例如氮化矽、氧化矽(例如，TEOS氧化物)、及其相似物。A through conductive plug 20 is formed in the substrate 10 and extends into the substrate 10 from the front surface of the substrate 10 (the upward facing surface in FIG. 3A). In a first embodiment, as shown in FIG. 3A, the via conductive plug 20 is formed using a via-first approach and is attached to a bottom metallization layer (bottom metallization layer). Known as M1) formed before formation. Therefore, the conductive plug 20 is passed through the substrate 10 and the interconnect structure 12. The insulating layer 22 is formed on the sidewall of the through-hole conductive plug 20 and electrically isolates the conductive plug 20 from the substrate 10. The insulating layer 22 may be formed of a common dielectric material such as tantalum nitride, hafnium oxide (e.g., TEOS oxide), and the like.

第3B圖顯示晶圓2之上視圖，其顯示形成於晶圓2中之刻痕15。刻痕15可自晶圓2之一表面朝相反之表面延伸(兩表面皆為平坦表面)。並且，刻痕15自晶圓2之一邊緣延伸進入晶圓2。在一實施例中，刻痕15在上視圖中具有一三角形。在其他實施例中，刻痕15在上視圖中可具有其他的形狀，例如是矩形。FIG. 3B shows a top view of wafer 2 showing the score 15 formed in wafer 2. The score 15 may extend from one surface of the wafer 2 toward the opposite surface (both surfaces are flat surfaces). Also, the score 15 extends from one edge of the wafer 2 into the wafer 2. In an embodiment, the score 15 has a triangle in the top view. In other embodiments, the score 15 can have other shapes in the top view, such as a rectangle.

第4A圖顯示承載晶圓16(有時亦稱之為承載基底)之上視圖。承載晶圓16可由玻璃、矽、陶瓷玻璃、或其相似物形成。在一實施例中，承載晶圓16具有低於約1x108 Ohm-cm之電阻率。電阻率亦可低於約1x106 Ohm-cm，或甚至低於約1x103 Ohm-cm。這點可例如藉由於製造承載晶圓16時摻雜更為可移動之離子至適當的濃度而達到，例如可摻雜Na、K、Al、或其相似物。藉著減低承載晶圓16之電阻率，承載晶圓16在後續製程中可更為可靠地固定於靜電吸盤上。Figure 4A shows a top view of carrier wafer 16 (sometimes referred to as a carrier substrate). Carrier wafer 16 may be formed from glass, tantalum, ceramic glass, or the like. In one embodiment, the carrier wafer 16 having a resistivity less than about 1x10 8 Ohm-cm it. May resistivity of less than about 1x10 6 Ohm-cm, or even less than about 1x10 3 Ohm-cm. This can be achieved, for example, by doping the more mobile ions to a suitable concentration when fabricating the carrier wafer 16, such as Na, K, Al, or the like. By reducing the resistivity of the carrier wafer 16, the carrier wafer 16 can be more reliably secured to the electrostatic chuck in subsequent processes.

承載晶圓16亦包括刻痕17，其亦自承載晶圓16之一表面朝相反表面延伸(兩表面皆為平坦表面)。在一實施例中，承載晶圓16之直徑D2大於晶圓2之直徑D1。再者，自承載晶圓16之中心C2至刻痕17之距離S2小於晶圓2之半徑R1(參照第3B圖)。距離S2亦可大於、等於、或小於自晶圓2之中心C1到刻痕15之最接近點的距離S1。The carrier wafer 16 also includes a score 17 that also extends from one surface of the carrier wafer 16 toward the opposite surface (both surfaces are flat surfaces). In one embodiment, the diameter D2 of the carrier wafer 16 is greater than the diameter D1 of the wafer 2. Furthermore, the distance S2 from the center C2 of the carrier wafer 16 to the score 17 is smaller than the radius R1 of the wafer 2 (see FIG. 3B). The distance S2 may also be greater than, equal to, or less than the distance S1 from the center C1 of the wafer 2 to the closest point of the score 15.

第4B圖顯示承載晶圓16之剖面圖。較佳地，頂角落19(在面向後續將接合之晶圓2一側上，其以虛線顯示)具有尖銳的輪廓而不具斜面區。換言之，承載晶圓16之側面與承載晶圓16之邊緣形成一尖銳角(例如，90度)。FIG. 4B shows a cross-sectional view of the carrier wafer 16. Preferably, the top corner 19 (shown in phantom on the side facing the wafer 2 to be subsequently bonded) has a sharp outline without a beveled area. In other words, the side of the carrier wafer 16 forms a sharp angle (eg, 90 degrees) with the edge of the carrier wafer 16.

請參照第5A圖，接墊14係形成在晶圓2之前表面(第5A圖中朝上之表面)上，且接墊14凸出於前表面。接著，透過黏著層18將晶圓2設置於承載晶圓16上。在接合之後，所結合之包含晶圓2與承載晶圓16之結構的翹曲(warpage)W(見第5E及5F圖)較佳小於約20μm，或甚至小於約1μm。第5E圖顯示翹曲W之第一例子。可瞭解的是翹曲W亦可能為相反之方向，如第5F圖所示。翹曲W之縮減可藉由玻璃平坦度或膠之控制而達到。Referring to FIG. 5A, the pads 14 are formed on the front surface of the wafer 2 (the upward facing surface in FIG. 5A), and the pads 14 protrude from the front surface. Next, the wafer 2 is placed on the carrier wafer 16 through the adhesive layer 18. After bonding, the warpage W (see Figures 5E and 5F) of the structure comprising the wafer 2 and the carrier wafer 16 is preferably less than about 20 μm, or even less than about 1 μm. Fig. 5E shows a first example of warpage W. It can be understood that the warpage W may also be in the opposite direction, as shown in Fig. 5F. The reduction of warpage W can be achieved by the control of glass flatness or glue.

第5B圖顯示第5A圖所示之結構的上視圖。在一實施例中，如第5B圖所示，部分的刻痕17與整個刻痕15重疊，且可延伸於晶圓2之下。在另一實施例中，如第5C圖所示，刻痕17之邊緣與刻痕15之邊緣對準。在又一實施例中，如第5D圖所示，刻痕17之整體僅與部分的刻痕15重疊。Fig. 5B is a top view showing the structure shown in Fig. 5A. In one embodiment, as shown in FIG. 5B, a portion of the score 17 overlaps the entire score 15 and may extend below the wafer 2. In another embodiment, as shown in FIG. 5C, the edge of the score 17 is aligned with the edge of the score 15. In still another embodiment, as shown in FIG. 5D, the entirety of the score 17 overlaps only a portion of the score 15.

在第6圖中，進行背面研磨(backside grinding)以移除基底10之多餘的部分。對晶圓2之背面進行化學機械研磨(CMP)而使穿矽導電插塞20露出。形成背面絕緣層24以覆蓋基底10之背面。在一實施例中，背面絕緣層24之形成包括對基底10之背面進行回蝕刻、毯覆式形成背面絕緣層24、以及進行輕微的化學機械研磨以移除背面絕緣層24之直接位於穿矽導電插塞20上的部分。因此，穿矽導電插塞20透過在背面絕緣層24中之開口而露出。在另一實施例中，背面絕緣層24中之開口(穿矽導電插塞20透過該開口而露出)藉由蝕刻而形成。由於晶圓2可包括複數個穿矽導電插塞(TSVs)，翹曲之減少可造成晶圓2中之穿矽導電插塞均勻露出，而不是部份的穿矽導電插塞未露出，但另一部分之穿矽導電插塞露出。In Fig. 6, backside grinding is performed to remove excess portions of the substrate 10. Chemical mechanical polishing (CMP) is performed on the back surface of the wafer 2 to expose the through-hole conductive plug 20. A back insulating layer 24 is formed to cover the back surface of the substrate 10. In one embodiment, the formation of the backside insulating layer 24 includes etch backing the back side of the substrate 10, blanket forming the backside insulating layer 24, and performing a slight chemical mechanical polishing to remove the backside insulating layer 24 directly from the through A portion of the conductive plug 20. Therefore, the through conductive plug 20 is exposed through the opening in the back insulating layer 24. In another embodiment, the opening in the backside insulating layer 24 (the through-via conductive plug 20 is exposed through the opening) is formed by etching. Since the wafer 2 can include a plurality of through-hole conductive plugs (TSVs), the reduction in warpage can cause the through-hole conductive plugs in the wafer 2 to be uniformly exposed, instead of the partial through-hole conductive plugs not being exposed, but Another portion of the through-hole conductive plug is exposed.

請參照第7A圖，於背面絕緣層24及穿矽導電插塞20上形成薄晶種層26(亦為凸塊下金屬層，UBM)。凸塊下金屬層26可藉著濺鍍或其他可應用方法而形成。凸塊下金屬層26之可用材料包括銅或銅合金。然而，亦可包括其他金屬，例如銀、金、鋁、或前述之組合。Referring to FIG. 7A, a thin seed layer 26 (also referred to as a sub-bump metal layer, UBM) is formed on the back insulating layer 24 and the via conductive plug 20. The under bump metal layer 26 can be formed by sputtering or other applicable methods. Useful materials for the under bump metal layer 26 include copper or copper alloys. However, other metals may also be included, such as silver, gold, aluminum, or combinations of the foregoing.

第7B圖顯示第7A圖所示之結構的邊緣部份。為了簡化，僅顯示凸塊下金屬層26、晶圓2、黏著層18、及承載晶圓16，其他元件則不顯示。可發現由於承載晶圓16中之刻痕17形成在晶圓2中之刻痕15之下，沒有凸塊下金屬層26會沉積於承載晶圓16之上而透過刻痕15露出。因此，用以進行後續製程步驟之儀器(例如，光學步進機)可輕易地找到刻痕15，導致更為可靠之製程。Fig. 7B shows the edge portion of the structure shown in Fig. 7A. For simplicity, only the under bump metal layer 26, the wafer 2, the adhesion layer 18, and the carrier wafer 16 are shown, and other components are not shown. It can be seen that since the score 17 in the carrier wafer 16 is formed under the score 15 in the wafer 2, no under bump metal layer 26 is deposited over the carrier wafer 16 and exposed through the score 15. Therefore, the instrument for performing subsequent processing steps (for example, an optical stepper) can easily find the score 15, resulting in a more reliable process.

第7A圖還顯示遮罩(mask)46之形成。在一實施例中，遮罩46為一光阻。或者，遮罩46係由乾膜(dry film)製成，其可包括有機材料，例如是日本Ajinomoto公司所供應的增層膜(Ajinimoto buildup film，ABF)。接著，將遮罩46圖案化以於遮罩46中形成開口50，其中穿矽導電插塞20(及凸塊下金屬層26之覆蓋部分)透過開口50而露出。既然承載晶圓16刻有刻痕，可在遮罩46之圖案化中進行更為準確的對準。Figure 7A also shows the formation of a mask 46. In an embodiment, the mask 46 is a photoresist. Alternatively, the mask 46 is made of a dry film, which may include an organic material such as an Ajinimoto buildup film (ABF) supplied by Ajinomoto, Japan. Next, the mask 46 is patterned to form an opening 50 in the mask 46, wherein the through-via conductive plug 20 (and the covered portion of the under bump metal layer 26) is exposed through the opening 50. Since the carrier wafer 16 is scored, more accurate alignment can be achieved in the patterning of the mask 46.

在第8圖中，如第7A圖所示之開口50被選擇性填充以金屬材料，而於開口50中形成重佈線路(redistribution line，RDL)52。在較佳實施例中，填充材料包括銅或銅合金，然而亦可使用其他金屬，例如鋁、銀、金、或前述之組合。形成方法可包括電化學電鍍(ECP)、無電鍍(electroless plating)、或其他常用的沉積方法，例如濺鍍、印刷(printing)、及化學氣相沉積(CVD)。接著，移除遮罩46。因此，露出了凸塊下金屬層26位於遮罩46下之部分。In Fig. 8, the opening 50 as shown in Fig. 7A is selectively filled with a metal material, and a redistribution line (RDL) 52 is formed in the opening 50. In a preferred embodiment, the filler material comprises copper or a copper alloy, although other metals such as aluminum, silver, gold, or combinations of the foregoing may also be used. The formation methods may include electrochemical plating (ECP), electroless plating, or other conventional deposition methods such as sputtering, printing, and chemical vapor deposition (CVD). Next, the mask 46 is removed. Therefore, the portion of the under bump metal layer 26 under the mask 46 is exposed.

請參照第9圖，藉由快速蝕刻(flash etching)移除凸塊下金屬層26之露出部分。所留下之重佈線路52可包括重佈線路條(RDL strip)521 (亦稱之為redistribution trace)，其包括直接位於穿矽導電插塞20之上且與之連接的部分，以及重佈線路52可選擇性包括與重佈線路條521 連結之墊(pad)522 。在第9圖及後續之圖式中，將不顯示凸塊下金屬層26，這是由於凸塊下金屬層26一般係由與重佈線路52相似之材質形成，因而與重佈線路52合併顯示。由於快速蝕刻，亦移除重佈線路52之一薄層。然而，重佈線路52所移除之部分與其整體厚度相比是可忽略的。Referring to FIG. 9, the exposed portion of the under bump metal layer 26 is removed by flash etching. The remaining redistribution line 52 may include a redistribution strip (RDL strip) 52 1 (also referred to as a redistribution trace) that includes a portion directly over and connected to the via conductive plug 20, and The cloth line 52 can optionally include a pad 52 2 that is coupled to the redistribution line strip 52 1 . In the ninth and subsequent figures, the under bump metal layer 26 will not be shown because the under bump metal layer 26 is typically formed of a material similar to the redistribution trace 52 and thus merges with the redistribution trace 52. display. A thin layer of the redistribution line 52 is also removed due to the rapid etch. However, the portion of the redistribution line 52 that is removed is negligible compared to its overall thickness.

接著，如第10圖所示，毯覆式形成保護層(passivation layer)56，並將之圖案化以形成開口58。保護層56可由氮化物、氧化物、聚醯亞胺(polyimide)、或其相似物所形成。塗佈光阻60並將之顯影以定義出開口58之圖案。部分的墊522 透過保護層56中之開口58而露出。開口58可佔據墊522 之中心部分。重佈線路條521 可繼續被保護層56覆蓋。Next, as shown in FIG. 10, a passivation layer 56 is formed in a blanket pattern and patterned to form openings 58. The protective layer 56 may be formed of a nitride, an oxide, a polyimide, or the like. The photoresist 60 is coated and developed to define the pattern of openings 58. A portion of the pad 52 2 is exposed through the opening 58 in the protective layer 56. The opening 58 can occupy a central portion of the pad 52 2 . The redistribution line strip 52 1 may continue to be covered by the protective layer 56.

接著，如第11圖所示，移除光阻60，並形成接墊(bonding pad)，其包括銅柱(copper pillar)64及緩衝層(barrier layer)66。在一實施例中，形成光阻63。光阻63較佳厚於光阻60。在一實施例中，光阻63厚了約20μm或甚至厚了約60μm。將光阻63圖案化以形成開口65，透過開口65露出了墊522 。接著，藉著電鍍自開口65開始形成銅柱64。銅柱64可包括銅及/或其他金屬，例如銀、金、鎢、鋁、或前述之組合。可於銅柱64上形成緩衝層66，其例如由鎳所形成，且可於緩衝層66上形成焊料(solder)68。Next, as shown in FIG. 11, the photoresist 60 is removed and a bonding pad is formed, which includes a copper pillar 64 and a barrier layer 66. In an embodiment, a photoresist 63 is formed. The photoresist 63 is preferably thicker than the photoresist 60. In one embodiment, the photoresist 63 is about 20 μm thick or even thicker by about 60 μm. The photoresist 63 is patterned to form an opening 65 through which the pad 52 2 is exposed. Next, a copper pillar 64 is formed from the opening 65 by electroplating. Copper pillars 64 may comprise copper and/or other metals such as silver, gold, tungsten, aluminum, or combinations of the foregoing. A buffer layer 66 may be formed on the copper pillars 64, which is formed, for example, of nickel, and a solder 68 may be formed on the buffer layer 66.

請參照第12圖，移除光阻63。承載晶圓16可接著自晶圓2取下。顯示於第10圖之結構可接合至其他晶片或晶圓，例如晶片/晶圓80。在一實施例中，晶片/晶圓80在其前表面上具有銅柱(copper post)86及緩衝層84，其中可迴焊(reflow)焊料68以接合晶圓2與晶片/晶圓80。可於晶圓2與晶片/晶圓80之間填充底膠(underfill)90。在另一實施例中，在接合至其他晶片/晶圓之前，可將晶圓2分切成數個晶片。在另一實施例中，承載晶圓16之取下可在晶圓2接合至晶片/晶圓80之後才進行。Please refer to Figure 12 to remove the photoresist 63. The carrier wafer 16 can then be removed from the wafer 2. The structure shown in FIG. 10 can be bonded to other wafers or wafers, such as wafer/wafer 80. In one embodiment, the wafer/wafer 80 has a copper post 86 and a buffer layer 84 on its front surface, wherein the solder 68 is reflowed to bond the wafer 2 to the wafer/wafer 80. An underfill 90 can be filled between the wafer 2 and the wafer/wafer 80. In another embodiment, wafer 2 can be diced into several wafers prior to bonding to other wafers/wafers. In another embodiment, the removal of the carrier wafer 16 can be performed after the wafer 2 is bonded to the wafer/wafer 80.

以上所討論之實施例中，穿矽導電插塞之背面內連線結構係用作解釋本發明實施例之例子。應注意的是，本發明實施例亦可用於其他涉及承載晶圓之製程，例如晶圓-晶圓接合製程(wafer-to-wafer bonding processes)。In the embodiments discussed above, the back interconnect structure of the conductive via plug is used as an example to explain embodiments of the present invention. It should be noted that the embodiments of the present invention can also be applied to other processes involving wafer-bearing, such as wafer-to-wafer bonding processes.

本發明實施例具有許多優點。藉由於承載晶圓中形成刻痕，無凸塊下金屬層會形成於承載晶圓之透過半導體晶圓中之刻痕所露出的部分。因此，可進行更可靠的對準。由於承載晶圓之角落不具有斜面區，可減少凸塊下金屬層之脫層。再者，由於承載晶圓之電阻率被減低，承載晶圓可更可靠地固定於靜電吸盤上。Embodiments of the invention have a number of advantages. By forming a nick in the carrier wafer, the under bumpless metal layer is formed in the portion of the wafer that is exposed through the scribes in the semiconductor wafer. Therefore, a more reliable alignment can be performed. Since the corners of the carrier wafer do not have a beveled area, delamination of the underlying metal layer of the bump can be reduced. Moreover, since the resistivity of the carrier wafer is reduced, the carrier wafer can be more reliably fixed to the electrostatic chuck.

雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and any one of ordinary skill in the art can make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

2．．．晶圓2. . . Wafer

4．．．積體電路元件4. . . Integrated circuit component

10．．．基底10. . . Base

12．．．內連線結構12. . . Inline structure

14．．．接墊14. . . Pad

15、17．．．刻痕15, 17. . . Scotch

16．．．承載晶圓16. . . Carrier wafer

18．．．黏著層18. . . Adhesive layer

20．．．穿矽導電插塞20. . . Through the conductive plug

22、24．．．絕緣層22, 24. . . Insulation

26．．．晶種層(或凸塊下金屬層)26. . . Seed layer (or under bump metal layer)

46．．．遮罩46. . . Mask

50、58、65．．．開口50, 58, 65. . . Opening

52．．．重佈線路52. . . Redistributed line

521 ．．．重佈線路條52 1 . . . Redistribution line

522 ．．．墊52 2 . . . pad

56．．．保護層56. . . The protective layer

60、63．．．光阻60, 63. . . Photoresist

64、86．．．銅柱64, 86. . . Copper column

66、84．．．緩衝層66, 84. . . The buffer layer

68．．．焊料68. . . solder

80．．．晶片/晶圓80. . . Wafer/wafer

90．．．底膠90. . . Primer

100．．．矽晶圓100. . . Silicon wafer

102．．．穿矽導電插塞102. . . Through the conductive plug

104．．．承載晶圓104. . . Carrier wafer

106．．．膠106. . . gum

108．．．凸塊下金屬層108. . . Under bump metal layer

110．．．斜面區110. . . Bevel area

112．．．刻痕112. . . Scotch

C1、C2．．．中心C1, C2. . . center

D1、D2．．．直徑D1, D2. . . diameter

R1．．．半徑R1. . . radius

S1、S2．．．距離S1, S2. . . distance

W．．．翹曲W. . . Warpage

第1圖顯示製作穿矽導電插塞背面連接時之中間製程階段的剖面圖，其中承載晶圓之斜面區上沉積有凸塊下金屬層。Figure 1 shows a cross-sectional view of the intermediate process stage in the fabrication of the backside connection of the conductive via plug, in which the underlying metal layer of the bump is deposited on the beveled region of the carrier wafer.

第2A圖顯示設置於承載晶圓上之矽晶圓的上視圖，其中矽晶圓中形成有刻痕。Figure 2A shows a top view of a germanium wafer disposed on a carrier wafer with a score formed in the germanium wafer.

第2B圖顯示第2A圖所示之結構的剖面圖。Fig. 2B is a cross-sectional view showing the structure shown in Fig. 2A.

第3A、3B、4A、4B、5A~5F、6、7A、7B、8~12圖顯示根據一實施例製作內連線結構之製程上視圖及剖面圖。3A, 3B, 4A, 4B, 5A-5F, 6, 7A, 7B, 8-12 show a top view and a cross-sectional view of a process for fabricating an interconnect structure in accordance with an embodiment.

2．．．晶圓2. . . Wafer

15、17．．．刻痕15, 17. . . Scotch

16．．．承載晶圓16. . . Carrier wafer

Claims (11)

一種積體電路結構的形成方法，包括：提供一半導體晶圓，包括一第一刻痕，自該半導體晶圓之一邊緣延伸進入該半導體晶圓，其中該半導體晶圓包括一穿半導體導電插塞，延伸進入該半導體晶圓；將一承載晶圓設置於該半導體晶圓之上，其中該承載晶圓包括一第二刻痕，位於該承載晶圓之中，且其中將該承載晶圓之設置步驟包括使至少一部分的該第一刻痕與至少一部分的該第二刻痕重疊；在設置該承載晶圓之步驟之後，研磨該半導體晶圓之一背面以露出該穿半導體導電插塞；以及於該半導體晶圓之該背面上沉積一導電層，該導電層電性連接該穿半導體導電插塞。 A method of forming an integrated circuit structure, comprising: providing a semiconductor wafer, including a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer, wherein the semiconductor wafer includes a semiconductor conductive plug a plug is extended into the semiconductor wafer; a carrier wafer is disposed on the semiconductor wafer, wherein the carrier wafer includes a second notch located in the carrier wafer, and wherein the carrier wafer is The step of disposing includes overlapping at least a portion of the first indentation with at least a portion of the second indentation; after the step of placing the carrier wafer, grinding a back side of the semiconductor wafer to expose the through-semiconductor conductive plug And depositing a conductive layer on the back surface of the semiconductor wafer, the conductive layer being electrically connected to the through semiconductor conductive plug. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中該第二刻痕自該承載晶圓之一邊緣延伸進入該承載晶圓。 The method of forming an integrated circuit structure as described in claim 1, wherein the second notch extends from an edge of the carrier wafer into the carrier wafer. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中設置該承載晶圓之步驟包括使該第二刻痕之邊緣對準該第一刻痕之邊緣。 The method of forming an integrated circuit structure according to claim 1, wherein the step of disposing the carrier wafer comprises aligning an edge of the second notch with an edge of the first notch. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中少於該第二刻痕之一整體的一部分的該第二刻痕與該第一刻痕之一整體重疊。 The method of forming an integrated circuit structure according to claim 1, wherein the second score less than a portion of the entirety of the second score overlaps integrally with one of the first scores. 如申請專利範圍第1項所述之積體電路結構的形成方法，其中少於該第一刻痕之一整體的一部分的該第一刻痕與該第二刻痕之一整體重疊。 The method of forming an integrated circuit structure according to claim 1, wherein the first score less than a portion of the entirety of the first score is integrally overlapped with one of the second scores. 一種積體電路結構的形成方法，包括：提供一半導體晶圓，其中該半導體晶圓包括一半導體基底以及一穿半導體導電插塞，延伸進入該半導體基底；將一承載晶圓設置於該半導體晶圓之上，其中該承載晶圓面對該半導體晶圓之一側面與該承載晶圓之一邊緣形成一銳角；於該半導體基底之一側面上形成一凸塊下金屬層，該凸塊下金屬層電性連接該穿半導體導電插塞；以及在形成凸塊下金屬層的步驟之後，將該承載晶圓自該半導體晶圓取下。 A method for forming an integrated circuit structure, comprising: providing a semiconductor wafer, wherein the semiconductor wafer comprises a semiconductor substrate and a semiconductor conductive plug extending into the semiconductor substrate; and a carrier wafer is disposed on the semiconductor crystal Above the circle, wherein the carrier wafer faces an edge of the semiconductor wafer to form an acute angle with an edge of the carrier wafer; and a bump under metal layer is formed on one side of the semiconductor substrate, the bump is under the bump The metal layer is electrically connected to the through semiconductor conductive plug; and after the step of forming the under bump metal layer, the carrier wafer is removed from the semiconductor wafer. 如申請專利範圍第6項所述之積體電路結構的形成方法，其中包括該承載晶圓與該半導體晶圓之一聯合結構具有一翹曲，小於約20μm。 The method for forming an integrated circuit structure according to claim 6, wherein the carrier structure and the semiconductor wafer have a warp structure of less than about 20 μm. 如申請專利範圍第6項所述之積體電路結構的形成方法，其中該半導體晶圓包括一第一刻痕，自該半導體晶圓之一邊緣延伸進入該半導體晶圓，且該承載晶圓包括一第二刻痕，其中設置該承載晶圓之步驟包括對準該第二刻痕而使該第二刻痕與至少一部分的該第一刻痕重疊。 The method for forming an integrated circuit structure according to claim 6, wherein the semiconductor wafer includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer, and the carrier wafer A second score is included, wherein the step of placing the carrier wafer includes aligning the second score to overlap the second score with at least a portion of the first score. 一種基底電路結構的形成方法，包括：提供一半導體晶圓，其中該半導體晶圓包括一半導體基底以及一穿半導體導電插塞，延伸進入該半導體基底；將一承載晶圓設置於該半導體晶圓之上，其中該承 載晶圓具有一電阻率，小於約1x108 Ohm-cm；在設置該承載晶圓之步驟之後，研磨該半導體晶圓之一背面以露出該穿半導體導電插塞；以及於該半導體晶圓之該背面上沉積一導電層，該導電層電性連接該穿半導體導電插塞。A method of forming a substrate circuit structure includes: providing a semiconductor wafer, wherein the semiconductor wafer includes a semiconductor substrate and a semiconductor conductive plug extending into the semiconductor substrate; and placing a carrier wafer on the semiconductor wafer Above, wherein the carrier wafer has a resistivity of less than about 1×10 8 Ohm-cm; after the step of placing the carrier wafer, grinding one back surface of the semiconductor wafer to expose the through semiconductor conductive plug; A conductive layer is deposited on the back surface of the semiconductor wafer, and the conductive layer is electrically connected to the through semiconductor conductive plug. 如申請專利範圍第9項所述之積體電路結構的形成方法，其中該承載晶圓面對該半導體晶圓之一側面上之大抵所有的角落具有一尖銳的輪廓，該輪廓具有一90度角。 The method for forming an integrated circuit structure according to claim 9, wherein the carrier wafer has a sharp outline facing substantially all corners on one side of the semiconductor wafer, the contour having a 90 degree angle. 如申請專利範圍第9項所述之積體電路結構的形成方法，其中該半導體晶圓包括一第一刻痕，自該半導體晶圓之一邊緣延伸進入該半導體晶圓，且該承載晶圓包括一第二刻痕，其中設置該承載晶圓之步驟包括對準該第二刻痕而使該第二刻痕與至少一部分的該第一刻痕重疊。 The method for forming an integrated circuit structure according to claim 9, wherein the semiconductor wafer includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer, and the carrier wafer A second score is included, wherein the step of placing the carrier wafer includes aligning the second score to overlap the second score with at least a portion of the first score.
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Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8435802B2 (en) * 2006-05-22 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Conductor layout technique to reduce stress-induced void formations
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8859424B2 (en) 2009-08-14 2014-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer carrier and method of manufacturing
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US8174124B2 (en) 2010-04-08 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy pattern in wafer backside routing
US9142533B2 (en) 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
KR20120090417A (en) * 2011-02-08 2012-08-17 삼성전자주식회사 Semiconductor device and method of manufacturing a semiconductor device
US8610285B2 (en) 2011-05-30 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3D IC packaging structures and methods with a metal pillar
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8570514B2 (en) * 2011-06-20 2013-10-29 Kla-Tencor Corporation Optical system polarizer calibration
US8525168B2 (en) * 2011-07-11 2013-09-03 International Business Machines Corporation Integrated circuit (IC) test probe
US9053989B2 (en) * 2011-09-08 2015-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated bump structure in semiconductor device
US8318579B1 (en) * 2011-12-01 2012-11-27 United Microelectronics Corp. Method for fabricating semiconductor device
JP2013131652A (en) 2011-12-21 2013-07-04 Fujitsu Semiconductor Ltd Semiconductor device manufacturing method, semiconductor wafer processing method, and semiconductor wafer
KR101916225B1 (en) 2012-04-09 2018-11-07 삼성전자 주식회사 Semiconductor chip comprising TSV(Through Silicon Via), and method for fabricating the same chip
US9646923B2 (en) 2012-04-17 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices
US9425136B2 (en) 2012-04-17 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Conical-shaped or tier-shaped pillar connections
US9299674B2 (en) 2012-04-18 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bump-on-trace interconnect
KR101931115B1 (en) 2012-07-05 2018-12-20 삼성전자주식회사 Semiconductor device and method of forming the same
US9646899B2 (en) 2012-09-13 2017-05-09 Micron Technology, Inc. Interconnect assemblies with probed bond pads
US9111817B2 (en) 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
KR20140073163A (en) * 2012-12-06 2014-06-16 삼성전자주식회사 Semiconductor device and method of forming the same
KR20140090462A (en) 2013-01-09 2014-07-17 삼성전자주식회사 Semiconductor device and method for fabricating the same
US20150115461A1 (en) * 2013-10-30 2015-04-30 United Microelectronics Corp. Semiconductor structure and method for forming the same
US9768147B2 (en) 2014-02-03 2017-09-19 Micron Technology, Inc. Thermal pads between stacked semiconductor dies and associated systems and methods
US9666523B2 (en) 2015-07-24 2017-05-30 Nxp Usa, Inc. Semiconductor wafers with through substrate vias and back metal, and methods of fabrication thereof
US10147682B2 (en) 2015-11-30 2018-12-04 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for stacked logic performance improvement
US9935079B1 (en) 2016-12-08 2018-04-03 Nxp Usa, Inc. Laser sintered interconnections between die
US10643951B2 (en) * 2017-07-14 2020-05-05 Taiwan Semiconductor Manufacturing Co., Ltd. Mini identification mark in die-less region of semiconductor wafer
US11037873B2 (en) 2019-06-03 2021-06-15 Marvell Government Solutions, Llc. Hermetic barrier for semiconductor device
KR20240027704A (en) * 2021-06-24 2024-03-04 미쓰이금속광업주식회사 Manufacturing method of wiring board
WO2023189176A1 (en) * 2022-03-31 2023-10-05 日本碍子株式会社 Temporary fixed substrate, method of manufacturing temporary fixed substrate, and temporary fixing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897362A (en) * 1998-04-17 1999-04-27 Lucent Technologies Inc. Bonding silicon wafers
US20040151917A1 (en) * 2003-01-31 2004-08-05 Taiwan Semiconductor Manufacturing Company Bonded soi wafer with <100> device layer and <110> substrate for performance improvement
US6924551B2 (en) * 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package
US6962867B2 (en) * 2002-07-31 2005-11-08 Microntechnology, Inc. Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461357A (en) 1967-09-15 1969-08-12 Ibm Multilevel terminal metallurgy for semiconductor devices
JPH05211239A (en) 1991-09-12 1993-08-20 Texas Instr Inc <Ti> Interconnection structure of integrated circuit and method for formation of it
DE4314907C1 (en) 1993-05-05 1994-08-25 Siemens Ag Method for producing semiconductor components making electrically conducting contact with one another vertically
US5391917A (en) 1993-05-10 1995-02-21 International Business Machines Corporation Multiprocessor module packaging
US6461357B1 (en) * 1997-02-12 2002-10-08 Oratec Interventions, Inc. Electrode for electrosurgical ablation of tissue
EP2270845A3 (en) 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
JPH1171508A (en) 1997-08-29 1999-03-16 Teijin Ltd Silicon wafer carrier
US6037822A (en) 1997-09-30 2000-03-14 Intel Corporation Method and apparatus for distributing a clock on the silicon backside of an integrated circuit
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
JP4063944B2 (en) * 1998-03-13 2008-03-19 独立行政法人科学技術振興機構 Manufacturing method of three-dimensional semiconductor integrated circuit device
JPH11274020A (en) * 1998-03-20 1999-10-08 Asahi Chem Ind Co Ltd Semiconductor substrate and semiconductor device
JP2000223683A (en) * 1999-02-02 2000-08-11 Canon Inc Composite member and its isolation method, laminated substrate and its isolation method, relocation method of relocation layer, and method for manufacturing soi substrate
JP3532788B2 (en) 1999-04-13 2004-05-31 唯知 須賀 Semiconductor device and manufacturing method thereof
US6322903B1 (en) 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
KR20050044643A (en) * 2001-12-04 2005-05-12 신에쯔 한도타이 가부시키가이샤 Pasted wafer and method for producing pasted wafer
US6599778B2 (en) 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
WO2003063242A1 (en) 2002-01-16 2003-07-31 Alfred E. Mann Foundation For Scientific Research Space-saving packaging of electronic circuits
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
JP2004119943A (en) * 2002-09-30 2004-04-15 Renesas Technology Corp Semiconductor wafer and manufacturing method therefor
US7030481B2 (en) 2002-12-09 2006-04-18 Internation Business Machines Corporation High density chip carrier with integrated passive devices
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US7111149B2 (en) 2003-07-07 2006-09-19 Intel Corporation Method and apparatus for generating a device ID for stacked devices
US6897125B2 (en) 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
TWI251313B (en) 2003-09-26 2006-03-11 Seiko Epson Corp Intermediate chip module, semiconductor device, circuit board, and electronic device
US7335972B2 (en) 2003-11-13 2008-02-26 Sandia Corporation Heterogeneously integrated microsystem-on-a-chip
US7049170B2 (en) 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
JP4467318B2 (en) 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 Semiconductor device, chip alignment method for multi-chip semiconductor device, and method for manufacturing chip for multi-chip semiconductor device
DE102004018250A1 (en) * 2004-04-15 2005-11-03 Infineon Technologies Ag Wafer stabilization device and method for its production
WO2006017252A1 (en) * 2004-07-12 2006-02-16 The Regents Of The University Of California Electron microscope phase enhancement
DE102004041378B4 (en) * 2004-08-26 2010-07-08 Siltronic Ag Semiconductor wafer with a layered structure with low warp and bow and process for its production
US7262495B2 (en) 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7297574B2 (en) 2005-06-17 2007-11-20 Infineon Technologies Ag Multi-chip device and method for producing a multi-chip device
US7371663B2 (en) * 2005-07-06 2008-05-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional IC device and alignment methods of IC device substrates
US7544947B2 (en) * 2006-03-08 2009-06-09 Aeroflex Colorado Springs Inc. Cross-talk and back side shielding in a front side illuminated photo detector diode array
US20080057678A1 (en) * 2006-08-31 2008-03-06 Kishor Purushottam Gadkaree Semiconductor on glass insulator made using improved hydrogen reduction process
KR100800161B1 (en) 2006-09-30 2008-02-01 주식회사 하이닉스반도체 Method for forming through silicon via
DE602007004173D1 (en) * 2006-12-01 2010-02-25 Siltronic Ag Silicon wafer and its method of production
JP4468427B2 (en) * 2007-09-27 2010-05-26 株式会社東芝 Manufacturing method of semiconductor device
US7786584B2 (en) 2007-11-26 2010-08-31 Infineon Technologies Ag Through substrate via semiconductor components
US7691747B2 (en) 2007-11-29 2010-04-06 STATS ChipPAC, Ltd Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures
US7842607B2 (en) 2008-07-15 2010-11-30 Stats Chippac, Ltd. Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via
US7727781B2 (en) 2008-07-22 2010-06-01 Agere Systems Inc. Manufacture of devices including solder bumps
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US7956442B2 (en) 2008-10-09 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Backside connection to TSVs having redistribution lines
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8759949B2 (en) 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
US8294261B2 (en) 2010-01-29 2012-10-23 Texas Instruments Incorporated Protruding TSV tips for enhanced heat dissipation for IC devices
US20110193235A1 (en) 2010-02-05 2011-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Architecture with Die Inside Interposer
US8587121B2 (en) 2010-03-24 2013-11-19 International Business Machines Corporation Backside dummy plugs for 3D integration

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5897362A (en) * 1998-04-17 1999-04-27 Lucent Technologies Inc. Bonding silicon wafers
US6962867B2 (en) * 2002-07-31 2005-11-08 Microntechnology, Inc. Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof
US20040151917A1 (en) * 2003-01-31 2004-08-05 Taiwan Semiconductor Manufacturing Company Bonded soi wafer with <100> device layer and <110> substrate for performance improvement
US6924551B2 (en) * 2003-05-28 2005-08-02 Intel Corporation Through silicon via, folded flex microelectronic package

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