CN116564396A - Memory controller capable of calibrating clock, clock calibration method and device - Google Patents

Memory controller capable of calibrating clock, clock calibration method and device Download PDF

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Publication number
CN116564396A
CN116564396A CN202310628611.XA CN202310628611A CN116564396A CN 116564396 A CN116564396 A CN 116564396A CN 202310628611 A CN202310628611 A CN 202310628611A CN 116564396 A CN116564396 A CN 116564396A
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China
Prior art keywords
clock
instruction
module
target
control word
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CN202310628611.XA
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Chinese (zh)
Inventor
温佳强
赖鼐
龚晖
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Zhuhai Miaocun Technology Co ltd
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Zhuhai Miaocun Technology Co ltd
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Priority to CN202310628611.XA priority Critical patent/CN116564396A/en
Publication of CN116564396A publication Critical patent/CN116564396A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention discloses a memory controller capable of calibrating a clock, a clock calibration method and a clock calibration device, wherein the memory controller comprises a clock module, and the clock module is used for providing a clock for a chip; the clock module comprises a clock source module, a clock control module and a clock detection module; the clock source module is used for generating a target clock with required frequency according to the received clock control word; the clock detection module is used for generating a program instruction according to the sizes of the target clock and the reference clock; the clock control module is used for updating the clock control word according to the program instruction; the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero. The memory controller in the embodiment of the invention can realize the calibration of the clock without participation of a crystal oscillator module, is beneficial to reducing the parts of the memory controller and the packaging difficulty, thereby improving the reliability of the memory controller and being widely applied to the technical field of chip memory controllers.

Description

Memory controller capable of calibrating clock, clock calibration method and device
Technical Field
The invention relates to the technical field of chip memory controllers, in particular to a memory controller capable of calibrating clocks, a clock calibration method and a clock calibration device.
Background
In embedded storage application, the storage controller and the flash memory particles are packaged into a chip through a packaging technology, and the less components are involved in the packaging process, the less difficulty is in packaging, and the higher reliability is. However, in the related art, the memory controller involves more components or devices, and has the problems of greater packaging difficulty and poor reliability.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art to a certain extent.
Therefore, the invention aims to provide a memory controller which is easy to package and reliable and can calibrate clocks, a clock calibration method and a clock calibration device.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention comprises the following steps:
in one aspect, an embodiment of the present invention provides a memory controller capable of calibrating a clock, including:
the memory controller capable of calibrating the clock comprises a clock module, wherein the clock module is used for providing a clock for a chip; the clock module comprises a clock source module, a clock control module and a clock detection module; the clock source module is used for generating a target clock with required frequency according to the received clock control word; the clock detection module is used for generating program instructions according to the sizes of the target clock and the reference clock, and the program instructions are used for representing the direction and the amplitude for adjusting the target clock; the clock control module is used for updating the clock control word according to the program instruction; the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero. According to the embodiment of the invention, clock calibration is realized through the clock module; the clock detection module and the clock control module are mutually adjusted to update the clock control word, so that clock calibration is realized. The memory controller in the embodiment of the invention can realize the calibration of the clock without participation of the crystal oscillator module, is beneficial to reducing the components of the memory controller and the packaging difficulty, thereby improving the reliability of the memory controller.
In addition, the memory controller capable of calibrating clocks according to the above embodiment of the present invention may further have the following additional technical features:
further, the memory controller capable of calibrating a clock according to the embodiment of the present invention, the reference clock is acquired by a first device, the program instructions include a first instruction and a second instruction, the first instruction is used for characterizing that the frequency of the target clock is increased or decreased and adjusted in a chip test stage, and the second instruction is used for characterizing that the amplitude of the adjustment of the target clock is recorded as a first deviation; the updated clock control word comprises a third instruction, wherein the third instruction is used for representing the adjustment amplitude of the clock control word; the third instruction is obtained according to the first deviation and a fourth instruction, the fourth instruction is used for representing a first amplitude caused by single-step adjustment of a clock control word, and the first amplitude is used for representing the variation amplitude of clock frequency; the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero, where the clock source module includes: the clock source module is further configured to generate a calibrated target clock if the third instruction is zero.
Further, in an embodiment of the present invention, the clock source module is connected to an oscilloscope, where the oscilloscope is configured to receive the target clock output by the clock source module during a chip test stage, and compare a frequency of the target clock with a frequency of a reference clock; the clock control module is connected with a second device, and the second device is used for generating a program instruction according to the comparison result; and the clock source module is also used for generating a calibrated target clock if the comparison results are the same.
Further, in one embodiment of the present invention, the chip includes a first clock module and a second clock module; the reference clock of the first clock module is a target clock of the second clock module, and the first clock module is used for generating a first clock by taking the target clock of the second clock module as a reference in a chip use stage; the first clock is used to characterize the new clock requirement.
Further, in one embodiment of the present invention, the memory controller further comprises a power-on control circuit and a nonvolatile memory; the nonvolatile storage is used for storing a first control word, and the first control word is used for representing a clock control word corresponding to the calibrated target clock; the power-on control circuit is used for acquiring the first control word from the nonvolatile storage; the clock control module is used for sending the first control word to the clock source module; the clock source module is also used for generating a calibrated target clock according to the first control word when power is on.
On the other hand, an embodiment of the present invention provides a clock calibration method applied to the memory controller capable of calibrating a clock, where the method includes:
acquiring a reference clock;
generating a target clock according to the clock control word;
generating program instructions according to the reference clock and the target clock; the program instructions are for characterizing a direction and an amplitude of adjustment of the target clock;
and updating the clock control word according to the program instruction, returning to the step of generating the target clock according to the clock control word until the amplitude of the program instruction is zero, and generating the calibrated target clock.
Further, in the clock calibration method of the embodiment of the present invention, the reference clock is acquired by the first device; the program instructions include a first instruction and a second instruction, and the step of updating the clock control word according to the program instructions includes:
generating a first instruction and a second instruction according to the frequency of the reference clock and the frequency of the target clock; the first instruction is used for representing that the frequency of the target clock is increased or decreased and adjusted in a chip test stage, and the second instruction is used for representing the amplitude of the adjustment of the target clock and is marked as a first deviation;
generating a third instruction according to the first deviation and the fourth instruction; the fourth instruction is used for representing a first amplitude brought by single-step adjustment of the clock control word, and the first amplitude is used for representing the variation amplitude of the clock frequency; the third instruction is used for representing the adjustment amplitude of the clock control word;
and updating the clock control word according to the third instruction.
Further, the clock calibration method according to the embodiment of the invention further comprises the following steps:
in the chip test stage, the target clock is connected to an oscilloscope;
according to the oscilloscope, comparing the frequency of the target clock with the frequency of the reference clock;
and generating a program instruction according to the comparison result, and returning to the step of updating the clock control word according to the program instruction.
In another aspect, an embodiment of the present invention provides a clock calibration apparatus, including:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement the clock calibration method described above.
In another aspect, an embodiment of the present invention provides a storage medium in which a processor-executable program is stored, which when executed by a processor is configured to implement the above-described clock calibration method.
According to the embodiment of the invention, clock calibration is realized through the clock module; the clock detection module and the clock control module are mutually adjusted to update the clock control word, so that clock calibration is realized. The memory controller in the embodiment of the invention can realize the calibration of the clock without participation of the crystal oscillator module, is beneficial to reducing the components of the memory controller and the packaging difficulty, thereby improving the reliability of the memory controller.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made with reference to the accompanying drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and other drawings may be obtained according to these drawings without the need of inventive labor for those skilled in the art.
FIG. 1 is a schematic diagram of one embodiment of a memory controller in the related art;
FIG. 2 is a schematic diagram illustrating an embodiment of a memory controller capable of calibrating clocks according to the present invention;
FIG. 3 is a schematic diagram of an embodiment of a clock module according to the present invention;
FIG. 4 is a schematic diagram illustrating a configuration of an embodiment of a power-on startup calibration provided by the present invention;
FIG. 5 is a flowchart illustrating an embodiment of a clock calibration method according to the present invention;
fig. 6 is a schematic structural diagram of an embodiment of a clock calibration device according to the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. The step numbers in the following embodiments are set for convenience of illustration only, and the order between the steps is not limited in any way, and the execution order of the steps in the embodiments may be adaptively adjusted according to the understanding of those skilled in the art.
The clock is the basis of enabling the chip system to work, and generally, referring to fig. 1, the clock of the controller chip is all from an external crystal oscillator module and is matched with the internal driving circuit module of the chip to provide the clock for the system to work. However, in the embedded storage application, the memory controller Die and the flash memory particle Die are packaged into a chip through a packaging technology, and the fewer components involved in the packaging process, the smaller the packaging difficulty and the higher the reliability. Therefore, if the crystal oscillator can be removed, the reliability of the packaging system is very beneficial to being improved.
Based on the above, the embodiment of the invention provides a memory controller capable of calibrating a clock, so as to reduce the packaging difficulty of a chip and improve the reliability.
A memory controller and an implementation method for a calibratable clock according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings, and first, a memory controller for a calibratable clock according to an embodiment of the present invention is described with reference to the accompanying drawings.
FIG. 2 is a schematic diagram of a memory controller capable of calibrating a clock according to one embodiment of the invention, the memory controller including a clock module for providing a clock to a chip;
the clock module comprises a clock source module, a clock control module and a clock detection module; the clock source module is used for generating a target clock with required frequency according to the received clock control word; the clock detection module is used for generating program instructions according to the sizes of the target clock and the reference clock, and the program instructions are used for representing the direction and the amplitude for adjusting the target clock; the clock control module is used for updating the clock control word according to the program instruction;
the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero.
As shown in fig. 3, the clock management module in the embodiment of the present application provides a clock source for the entire chip system and supports clock calibration. The clock source module mainly comprises an oscillating circuit, a related oscillating circuit, a frequency control conversion circuit and the like. And after power-on, oscillation can be generated, and a clock is output. The output clock frequency is within a certain frequency range, and changing the input clock control word CTRLx < n:0> can change the output clock frequency until the clock frequency reaches a desired value, i.e., the target clock is generated. Because the process parameters in the chip production process fluctuate, the frequency of each chip output under the same clock control word may also be different, so that the detection and adjustment of the target clock need to be performed on each chip, and the generated clock reaches the basically same frequency value.
It will be appreciated that the clock detection module comprises two timing circuits, by which the frequencies of the two input clocks (i.e. the target clock and the reference clock) are compared. The module inputs the target clock and the reference clock, compares the frequencies of the two clocks, and outputs the comparison result (program instruction) to the clock control module and the internal register. The detection result comprises: the frequency of the target clock is compared with the frequency of the reference clock (i.e., the direction of adjustment) and the degree of the height (i.e., the amplitude). Illustratively, the program instructions may be represented as DIFFx < dir, val >, where:
dir=1, indicating that the target clock frequency is lower than the reference clock frequency, the frequency of the target clock needs to be raised by the clock control word;
dir=0, indicating that the frequency of the target clock is higher than the reference clock frequency, requiring the frequency of the target clock to be reduced by the clock control word;
val, representing the degree of frequency deviation between the frequency of the target clock and the frequency of the reference clock, may be converted into a frequency deviation Fx (i.e., a first deviation).
The clock control module inputs the detection result of the clock detection module, namely the program instruction DIFFx < dir, val >, converts the detection result based on the current clock control word and generates a new clock control word CTRLx < n:0>, and the new clock control word CTRLx < n:0> is used for adjusting the frequency of the target clock output by the clock source module. It will be appreciated that the range of values characterized by the clock control word CTRLx < n:0> corresponds to the range of frequencies of the target clock generated by the clock source module. The frequency of the target clock of the clock source module increases substantially linearly with the range of values represented by the clock control word ctrl < n:0> over the range of frequencies. Thus, the clock control word ctrl < n:0> is incremented or decremented by 1 resulting frequency change f0 (i.e., the fourth instruction) by the frequency range divided by the value range represented by the clock control word ctrl < n:0 >. The three modules are mutually matched, and after multiple detection and adjustment, the clock module can provide a clock source meeting accuracy requirements for a chip system.
Optionally, in the memory controller capable of calibrating a clock in the embodiment of the present invention, the reference clock is acquired by a first device, the program instruction includes a first instruction and a second instruction, the first instruction is used for characterizing that the frequency of the target clock is increased or decreased and adjusted in a chip test stage, and the second instruction is used for characterizing that the amplitude of the adjustment of the target clock is recorded as a first deviation; the updated clock control word comprises a third instruction, wherein the third instruction is used for representing the adjustment amplitude of the clock control word; the third instruction is obtained according to the first deviation and a fourth instruction, the fourth instruction is used for representing a first amplitude caused by single-step adjustment of the clock control word, and the first amplitude is used for representing the variation amplitude of the clock frequency;
the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero, where the clock source module includes: the clock source module is further configured to generate a calibrated target clock if the third instruction is zero.
In some possible implementations, the clock detection module outputs a precise reference clock calibration during the chip test phase. Specifically, the calibration procedure is as follows:
and S11, powering up the system, and outputting and generating a clock by a clock source module.
In step S12, the clock detection module detects a difference between the generated clock (i.e. the target clock) and the target frequency (i.e. the frequency of the reference clock), so as to obtain a first detected difference DIFF1. For example, DIFF1<1, val > indicates that the generation timing frequency is low and the rise frequency is required.
In step S13, the clock controller module records the current clock control word CTRL0< n:0>, converts val in DIFF1<1, val > into frequency deviation, the first deviation is F1, the third instruction is F1/F0, and confirms the new clock control word CTRL1< n:0> = CTRL0< n:0> + F1/F0. If the difference obtained in step 12 is DIFF1<0, val >, the new clock control word CTRL1< n:0> = ctrl0< n:0> -F1/F0.
And S14, adjusting the frequency by the clock source module to generate a new generated clock.
And step S15, repeating the steps S12 to S14 until the generated clock is detected to meet the accuracy requirement in the step S12.
Optionally, in the embodiment of the present invention, the clock source module is connected to an oscilloscope, where the oscilloscope is configured to receive, in a chip test stage, the target clock output by the clock source module, and compare a frequency of the target clock with a frequency of a reference clock;
the clock control module is connected with a second device, and the second device is used for generating a program instruction according to the comparison result;
and the clock source module is also used for generating a calibrated target clock if the comparison results are the same.
In some possible embodiments, the storage controller further supports outputting the generated clock to the outside of the chip, and the clock can be measured by using a measuring device such as an oscilloscope, so as to realize the related functions of the clock detection module. Specifically, in the chip test stage, a clock is generated through measurement of an external oscilloscope of the chip system, and the calibration steps are as follows:
and S21, powering up the system, and outputting and generating a clock by a clock source module.
Step S22, the oscilloscope measures the frequency value of the generated clock.
Step S23, if the frequency is higher than the expected frequency value, modifying the clock control word to reduce the clock frequency; if the clock frequency value is lower than the expected frequency value, modifying the clock control word to raise the clock frequency; if the frequency meets the expectations, the calibration is stopped.
And S24, adjusting the frequency by the clock source module to generate a new generated clock.
Step S25, repeating step S22-step S24 until the exit condition of step S23 is satisfied.
Based on the above steps, in order to improve the calibration efficiency and reduce the manual participation, the storage controller can be connected with the oscilloscope through a custom protocol, a calibration program is executed on the storage controller, the clock frequency value measured and output by the oscilloscope is received, the deviation from the target frequency is calculated, and the clock control word is converted.
Optionally, in the embodiment of the present invention, the memory controller capable of calibrating a clock, the chip includes a first clock module and a second clock module;
the reference clock of the first clock module is a target clock of the second clock module, and the first clock module is used for generating the first clock by taking the target clock of the second clock module as a reference in the chip use stage; the first clock is used to characterize the new clock requirement.
In some possible embodiments, the memory controller may also be used to calibrate all clock sources within the controller chip, and after an accurate clock is output, the system has new clock requirements to meet during normal use. In the normal use stage, the conditions of inputting the accurate reference clock and connecting the oscilloscope measurement are no longer provided. The memory controller is supported to be separated from an external accurate reference clock or measuring equipment, so that the clock sources can be mutually and dynamically adjusted in frequency, and the frequency modulation requirement in application is met.
In particular, the reference clock is replaced with the target clock of the internal calibrated clock source. The method can be used in system operation, and the clock sources are separated from external accurate reference clocks or measuring equipment to dynamically adjust the clock source frequencies mutually, so that the frequency modulation requirement in application is met.
Optionally, in the embodiment of the present invention, the memory controller capable of calibrating the clock further includes a power-on control circuit and a nonvolatile memory; the nonvolatile storage is used for storing a first control word, and the first control word is used for representing a clock control word corresponding to the calibrated target clock; the power-on control circuit is used for acquiring a first control word from nonvolatile storage; the clock control module is used for sending the first control word to the clock source module; the clock source module is also used for generating a calibrated target clock according to the first control word when power is on.
In some possible embodiments, referring to fig. 4, the memory controller is also used for the saving of calibration results and power-on initiated calibration. The clock control word controls the frequency of the clock generated by the clock source, so that after the clock source is calibrated, the clock control word is stored, and the stored clock control word is directly configured after the next power-on, so that the expected clock source can be quickly obtained. The clock source calibration can be carried out in the chip factory testing stage, and after the calibration is finished, clock control words are stored in a nonvolatile memory module in the chip. The chip system is internally provided with a power-on control circuit, and a clock control word is automatically loaded from a nonvolatile memory to a clock source module after power-on to obtain a desired clock source.
According to the embodiment of the invention, clock calibration is realized through the clock module; the clock detection module and the clock control module are mutually adjusted to update the clock control word, so that clock calibration is realized. The memory controller in the embodiment of the invention can realize the calibration of the clock without participation of the crystal oscillator module, is beneficial to reducing the components of the memory controller and the packaging difficulty, thereby improving the reliability of the memory controller.
Next, a clock calibration method proposed according to an embodiment of the present invention will be described with reference to the accompanying drawings.
Referring to fig. 5, a clock calibration method is provided in an embodiment of the present invention, and the clock calibration method in the embodiment of the present invention may be applied to a terminal, or may be applied to a server, or may be software running in the terminal or the server, or the like. The terminal may be, but is not limited to, a tablet computer, a notebook computer, a desktop computer, etc. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, basic cloud computing services such as big data and artificial intelligent platforms. The clock calibration method in the embodiment of the invention is applied to the memory controller capable of calibrating clocks, and mainly comprises the following steps:
s100: acquiring a reference clock;
s200: generating a target clock according to the clock control word;
s300: generating a program instruction according to the reference clock and the target clock; program instructions for characterizing the direction and magnitude of adjustments made to the target clock;
s400: and updating the clock control word according to the program instruction, and returning to the step of generating the target clock according to the clock control word until the amplitude of the program instruction is zero, so as to generate the calibrated target clock.
In some possible implementations, the clock detection module obtains a reference clock; the clock control module generates a target clock according to the clock control word; the clock detection module generates a program instruction according to the reference clock and the target clock; program instructions for characterizing the direction and magnitude of adjustments made to the target clock; the clock control module updates the clock control word according to the program instruction, and returns to the step of generating the target clock according to the clock control word until the amplitude of the program instruction is zero, and the calibrated target clock is generated.
Optionally, in the clock calibration method in the embodiment of the present invention, the reference clock is acquired by the first device; the program instruction comprises a first instruction and a second instruction, and the step of updating the clock control word according to the program instruction comprises the following steps:
generating a first instruction and a second instruction according to the frequency of the reference clock and the frequency of the target clock; the first instruction is used for representing that the frequency of the target clock is increased or decreased and adjusted in the chip test stage, and the second instruction is used for representing the amplitude of the adjustment of the target clock and is marked as a first deviation;
generating a third instruction according to the first deviation and the fourth instruction; the fourth instruction is used for representing a first amplitude brought by single-step adjustment of the clock control word, and the first amplitude is used for representing the variation amplitude of the clock frequency; the third instruction is used for representing the adjustment amplitude of the clock control word;
according to the third instruction, the clock control word is updated.
In some possible implementations, the clock detection module generates the first instruction and the second instruction according to the frequency magnitudes of the reference clock and the target clock; the clock control module generates a third instruction according to the first deviation and the fourth instruction; according to the third instruction, the clock control word is updated.
Optionally, the clock calibration method in the embodiment of the present invention further includes:
in the chip test stage, a target clock is connected to an oscilloscope;
according to the oscilloscope, comparing the frequency of the target clock with the frequency of the reference clock;
and generating a program instruction according to the comparison result, and returning to the step of updating the clock control word according to the program instruction.
In some possible embodiments, the storage controller further supports outputting the generated clock to the outside of the chip, and the clock can be measured by using a measuring device such as an oscilloscope, so as to realize the related functions of the clock detection module.
Optionally, the clock calibration method provided by the embodiment of the present invention further includes:
acquiring a target clock of the second clock as a reference clock of the first clock;
a clock detection module of a first clock receives a target clock of the second clock and a target clock of the first clock;
comparing the target clock of the second clock with the target clock of the first clock to obtain a fifth instruction;
comparing the required clock frequency with the frequency of the target clock of the second clock to obtain a sixth instruction;
obtaining a program instruction of a first clock according to the fifth instruction and the sixth instruction;
and updating the clock control word of the first clock according to the program instruction of the first clock.
Specifically, the embodiment of the invention obtains the fifth instruction by comparing the target clock of the second clock with the target clock of the first clock, and the fifth instruction is used for correcting the target clock of the first clock. Meanwhile, if the first clock is required to generate a new required target clock, comparing the frequency of the required target clock with the frequency of the target clock of the second clock to obtain the amount required to be increased or decreased, and generating the program instruction of the first clock.
Optionally, the embodiment of the present application further includes the following steps:
writing the clock control word into nonvolatile storage;
if a power-on program is carried out, acquiring the clock control word;
and sending the clock control word to a clock source module.
In summary, the embodiment of the invention provides a clock calibration method for externally selecting a reference clock, a clock calibration method based on external clock measurement equipment, a clock frequency adjustment method based on an internal clock source of a chip system, and a method and a flow for powering up an automatic calibration clock source. It can be seen that, the content in the above system embodiment is applicable to the method embodiment, and the functions specifically implemented by the method embodiment are the same as those of the system embodiment, and the beneficial effects achieved by the system embodiment are the same as those achieved by the system embodiment.
Referring to fig. 6, an embodiment of the present invention provides a clock calibration apparatus, including:
at least one processor 610;
at least one memory 620 for storing at least one program;
the at least one program, when executed by the at least one processor 610, causes the at least one processor 610 to implement the clock calibration method.
Similarly, the content in the above method embodiment is applicable to the embodiment of the present device, and the functions specifically implemented by the embodiment of the present device are the same as those of the embodiment of the above method, and the beneficial effects achieved by the embodiment of the above method are the same as those achieved by the embodiment of the above method.
The embodiment of the present invention also provides a computer-readable storage medium in which a processor-executable program is stored, which when executed by a processor is configured to perform the above-described clock calibration method.
Similarly, the content in the above method embodiment is applicable to the present storage medium embodiment, and the specific functions of the present storage medium embodiment are the same as those of the above method embodiment, and the achieved beneficial effects are the same as those of the above method embodiment.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present invention are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the invention is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the functions and/or features may be integrated in a single physical device and/or software module or may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present invention. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the invention as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the invention, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, including several programs for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable programs for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with a program execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the programs from the program execution system, apparatus, or device and execute the programs. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the program execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the embodiments described above, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.

Claims (10)

1. A memory controller capable of calibrating a clock, wherein the memory controller comprises a clock module for providing a clock to a chip;
the clock module comprises a clock source module, a clock control module and a clock detection module; the clock source module is used for generating a target clock with required frequency according to the received clock control word; the clock detection module is used for generating program instructions according to the sizes of the target clock and the reference clock, and the program instructions are used for representing the direction and the amplitude for adjusting the target clock; the clock control module is used for updating the clock control word according to the program instruction;
the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero.
2. The memory controller of claim 1, wherein the reference clock is obtained by a first device, the program instructions comprising first instructions for characterizing an increase or decrease adjustment of the frequency of the target clock during a chip test phase and second instructions for characterizing an amplitude of the adjustment of the target clock, denoted as a first deviation; the updated clock control word comprises a third instruction, wherein the third instruction is used for representing the adjustment amplitude of the clock control word; the third instruction is obtained according to the first deviation and a fourth instruction, the fourth instruction is used for representing a first amplitude caused by single-step adjustment of a clock control word, and the first amplitude is used for representing the variation amplitude of clock frequency;
the clock source module is further configured to generate a calibrated target clock if the amplitude of the program instruction is zero, where the clock source module includes: the clock source module is further configured to generate a calibrated target clock if the third instruction is zero.
3. The memory controller of claim 1, wherein the clock source module is connected to an oscilloscope, the oscilloscope is configured to receive the target clock output by the clock source module during a chip test stage, and compare a frequency of the target clock with a frequency of a reference clock;
the clock control module is connected with a second device, and the second device is used for generating a program instruction according to the comparison result;
and the clock source module is also used for generating a calibrated target clock if the comparison results are the same.
4. The memory controller of claim 1, wherein the chip comprises a first clock module and a second clock module;
the reference clock of the first clock module is a target clock of the second clock module, and the first clock module is used for generating a first clock by taking the target clock of the second clock module as a reference in a chip use stage; the first clock is used to characterize the new clock requirement.
5. The memory controller of claim 1, further comprising a power-on control circuit and a nonvolatile memory; the nonvolatile storage is used for storing a first control word, and the first control word is used for representing a clock control word corresponding to the calibrated target clock; the power-on control circuit is used for acquiring the first control word from the nonvolatile storage; the clock control module is used for sending the first control word to the clock source module; the clock source module is also used for generating a calibrated target clock according to the first control word when power is on.
6. A clock calibration method applied to the memory controller of the calibratable clock of claim 1, the method comprising:
acquiring a reference clock;
generating a target clock according to the clock control word;
generating program instructions according to the reference clock and the target clock; the program instructions are for characterizing a direction and an amplitude of adjustment of the target clock;
and updating the clock control word according to the program instruction, returning to the step of generating the target clock according to the clock control word until the amplitude of the program instruction is zero, and generating the calibrated target clock.
7. The method of clock calibration of claim 6, wherein the reference clock is obtained by a first device; the program instructions include a first instruction and a second instruction, and the step of updating the clock control word according to the program instructions includes:
generating a first instruction and a second instruction according to the frequency of the reference clock and the frequency of the target clock; the first instruction is used for representing that the frequency of the target clock is increased or decreased and adjusted in a chip test stage, and the second instruction is used for representing the amplitude of the adjustment of the target clock and is marked as a first deviation;
generating a third instruction according to the first deviation and the fourth instruction; the fourth instruction is used for representing a first amplitude brought by single-step adjustment of the clock control word, and the first amplitude is used for representing the variation amplitude of the clock frequency; the third instruction is used for representing the adjustment amplitude of the clock control word;
and updating the clock control word according to the third instruction.
8. The method of clock calibration according to claim 6, further comprising the step of updating the clock control word during a chip test phase, comprising:
the target clock is connected to an oscilloscope;
according to the oscilloscope, comparing the frequency of the target clock with the frequency of the reference clock;
and generating a program instruction according to the comparison result, and returning to the step of updating the clock control word according to the program instruction.
9. A clock calibration device, comprising:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement the clock calibration method of any one of claims 6-8.
10. A computer readable storage medium, in which a processor executable program is stored, characterized in that the processor executable program is for implementing the clock calibration method according to any of claims 6-8 when being executed by a processor.
CN202310628611.XA 2023-05-30 2023-05-30 Memory controller capable of calibrating clock, clock calibration method and device Pending CN116564396A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106130547A (en) * 2016-06-20 2016-11-16 大唐微电子技术有限公司 A kind of clock frequency calibration steps and device
CN114285409A (en) * 2020-09-28 2022-04-05 深圳英集芯科技股份有限公司 Method and related device for automatically calibrating clock frequency in chip

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106130547A (en) * 2016-06-20 2016-11-16 大唐微电子技术有限公司 A kind of clock frequency calibration steps and device
CN114285409A (en) * 2020-09-28 2022-04-05 深圳英集芯科技股份有限公司 Method and related device for automatically calibrating clock frequency in chip

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