CN116563089B - Memory management method, device and equipment of graphic processor and storage medium - Google Patents
Memory management method, device and equipment of graphic processor and storage medium Download PDFInfo
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Abstract
The embodiment discloses a memory management method, a device, equipment and a storage medium of a graphics processor. The method comprises the following steps: acquiring the physical page size and the required virtual address segment supported by hardware in memory management of the GPU; determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment; acquiring the memory space capacity required by GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in memory management according to the memory space capacity and the physical page size; and configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table. The method can dynamically determine the proper size of the memory management page table according to the required memory space capacity, and improves the memory data access performance.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for managing a memory of a graphics processor.
Background
With the development of computer technology, more and more electronic devices use graphics processors (Graphics Processing Unit, GPU) to perform operations, and put higher performance demands on GPU functions. For example, in electronic gaming applications, it is desirable to render large resolution, high complexity game visuals. If the GPU accesses the memory at a low data rate and at a high access frequency, the game screen is blocked.
The GPU memory data access performance is generally improved by upgrading the hardware configuration, but the cost is increased by improving the hardware configuration. In the limited cost range, the fixed page table size is adopted to perform GPU memory management, and the memory data access performance cannot be improved. For example, GPU memory management with larger page table sizes is common, which can lead to waste of memory resources; and the GPU memory management with a smaller page table size results in high memory access frequency and low access efficiency.
Disclosure of Invention
The invention provides a memory management method, a device, equipment and a storage medium of a graphics processor, which are used for dynamically determining the size of a memory management page table according to the memory space capacity and improving the memory data access performance.
According to an aspect of the present invention, there is provided a memory management method of a graphics processor, the method comprising:
acquiring a physical page size and a required virtual address segment supported by hardware in memory management of a Graphics Processor (GPU);
determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment;
acquiring the memory space capacity required by GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in memory management according to the memory space capacity and the physical page size;
and configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table.
According to another aspect of the present invention, there is provided a memory management apparatus of a graphic processor, the apparatus comprising:
the virtual address information acquisition module is used for acquiring the physical page size and the required virtual address segment supported by hardware in the memory management of the graphic processor GPU;
The virtual address management page determining module is used for determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment;
the physical address management page determining module is used for obtaining the memory space capacity required by the GPU calculation and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the physical page size;
and the memory management page table configuration module is used for configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table.
According to another aspect of the present invention, there is provided an electronic apparatus including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the memory management method of the graphics processor according to any one of the embodiments of the present invention.
According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement a memory management method of a graphics processor according to any one of the embodiments of the present invention when executed.
According to the technical scheme, the physical page size supported by hardware in memory management of the GPU and the required virtual address segment are obtained; determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment; acquiring the memory space capacity required by GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in memory management according to the memory space capacity and the physical page size; according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number, the GPU memory management page table is configured to access memory data according to the memory management page table, so that the problem of poor memory data access performance of the GPU is solved, the memory management page table size can be dynamically determined according to the memory space capacity, and the memory data access performance is improved; specifically, memory resource waste caused by oversized page table can be avoided; and the situations of high memory access frequency, low memory data access efficiency and low throughput caused by undersize page tables can be avoided.
It should be understood that the description in this section is not intended to identify key or critical features of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of GPU memory management with fixed page table size;
FIG. 2 is a schematic diagram of a configuration of MMU page tables;
FIG. 3 is a flowchart of a memory management method of a graphics processor according to a first embodiment of the present invention;
FIG. 4 is a flowchart of a memory management method of a graphics processor according to a second embodiment of the present invention;
FIG. 5 is a flow chart of a physical address management page allocation provided in accordance with a second embodiment of the present invention;
FIG. 6 is a schematic diagram of a memory management device of a graphics processor according to a third embodiment of the present invention;
Fig. 7 is a schematic structural diagram of an electronic device implementing a memory management method of a graphics processor according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In order to make the technical solution of the embodiment of the present invention clearer, the step of performing page table management by the GPU-driven memory management unit (Memory Management Unit, MMU) is described. FIG. 1 is a flow chart of GPU memory management with fixed page table sizes. In GPU memory management, as shown in fig. 1, first, consecutive virtual address segments with a Size not smaller than a desired space capacity are allocated according to a fixed page table Size, such as 4KB, and Size needs to be aligned to 4KB, where Size is the required memory space capacity; thereafter, physical address pages are allocated according to the fixed page table Size, which may be contiguous or non-contiguous, such as (size+4KB-1)/4KB pages; and finally, configuring an MMU page table according to the allocated virtual address and physical address, so that the MMU can translate and search the final physical address when accessing the virtual address, and access the data in the physical address memory.
FIG. 2 is a schematic diagram of the configuration of an MMU page table. As shown in FIG. 2, MMU page table configuration specification is performed with a page table size of 4 KB. Assuming that the MMU hardware supports three-level page tables and the virtual address is 40bits, the virtual address can be split into four segments as shown in FIG. 2. Bits [39,32] of the virtual address are used to index an entry in the level 0 page table (L0), and the physical page address of the next page table, i.e., level 1 page table (L1), is stored in the L0 entry. Bits 31,22 of the virtual address are used to index an entry in L1, and the physical page address of the next page table, i.e., the 2 nd page table (L2), is stored in the L1 entry. Bits 21,12 of the virtual address are used to index the entry in L2, and the entry in L2 is the address of the real physical memory to be accessed finally. bits [11,0] represent the address offset (offset) in the physical page to be accessed. The configuration principle corresponding to other page table sizes is similar. For example, if managed in a 64K page table size, bits [15,0] represent the offset of the access page, bits [21,16] are used to index the entry in L2, the bits corresponding to L0 and L1 remain unchanged, other page sizes, and so on.
Example 1
Fig. 3 is a flowchart of a memory management method of a graphics processor according to an embodiment of the present invention, where the method may be performed by a memory management device of the graphics processor, where the memory management device of the graphics processor may be implemented in hardware and/or software, and the memory management device of the graphics processor may be configured in an electronic device such as a GPU, where the MMU of the GPU performs memory physical page configuration to improve memory access performance. As shown in fig. 3, the method includes:
step 110, obtaining the physical page size and the required virtual address segment supported by the hardware in the memory management of the GPU.
In this step, the physical page size is the page table size supported by the MMU of the GPU. Exemplary physical page sizes include 4 Kilobytes (KB), 64KB, 2MB, 4MB, and so forth. The required virtual address field is the address space size that is set when the physical page is configured. The virtual address field is, for example, 40 bytes (bytes).
Step 120, determining the size of the virtual address management page and the number of virtual address management pages when the virtual address is allocated in the memory management according to the physical page size and the virtual address segment.
Wherein the virtual address management page size is determined based on the virtual address field and is aligned with one of the physical page sizes. The virtual address management page number can be the page number of the page table corresponding to the virtual address section when the virtual address section is realized by distributing according to the determined size of the virtual address management page. For example, when the virtual address field is 80bytes and the virtual address management page size is determined to be 4KB, the number of virtual address management pages is 1.
In an optional implementation manner of the embodiment of the present invention, determining, according to a physical page size and a virtual address field, a virtual address management page size and a virtual address management page number when a virtual address is allocated in memory management includes: determining the upper limit of a virtual address space in GPU memory management according to the width of the address bus; determining the virtual address management page size when the virtual address is distributed in the memory management according to the upper limit of the virtual address space and the physical page size; and determining the virtual address management page number according to the virtual address management page size and the virtual address segment.
Optionally, the virtual address space upper limit is 2 n N is the address bus width. The virtual address management page size is determined based on a comparison between the virtual address space upper bound and the physical page size. Illustratively, if the upper limit of the virtual address space is greater than all of the physical page sizes, then selecting any of the physical page sizes as the virtual address management page size; such as selecting the largest size of the physical page sizes as the virtual address management page size. Still further exemplary, the virtual address space upper bound is greater than only a partial page size of the physical page sizes, and then the virtual address management page size is determined in the partial page size where the virtual address space upper bound is greater than the partial page size; the maximum size in the partial size is managed as a virtual address.
In an alternative implementation of the embodiment of the present invention, in the physical page size, a maximum size that is less than or equal to an upper limit of the virtual address space is determined as the virtual address management page size. I.e. in an embodiment of the invention, a maximum size is determined that meets the virtual address space upper limit requirement and that is aligned with the physical page size, as the virtual address management page size.
The advantage of this is: first, the virtual address space available to each process in the GPU is sufficiently large, and specifically, the process can use the virtual address space for interval [0,2 ] n ) N is the address bus width. Therefore, the waste of the virtual address space has little influence on the resources, and thus it is possible to determine the maximum size that satisfies the virtual address space upper limit requirement as the virtual address management page size. Second, the virtual address management page size is aligned with the physical page size, which may facilitate mapping of the GPU virtual address to the physical page, i.e., may support the physical page size. Finally, the resource binding in the virtual address management interface (e.g. the spark resource in vulkan, opengl) may randomly map the GPU virtual address space to the memory with unknown physical page size, such as any one of 4KB, 64KB, 2MB, and 4MB, and in the embodiment of the present invention, the maximum size of the virtual address space is smaller than or equal to the upper limit of the virtual address space, which is used as the virtual address management page size, so that the virtual address management page can support more physical page alignment as much as possible.
Illustratively, when the address bus width is large enough, i.e., the virtual address space upper limit is large enough, the virtual address management page size is the largest size, e.g., 4MB, of the physical page sizes. And the memory allocation and management are carried out by taking 4MB as the virtual address management page size, so that the alignment requirements of all supported physical page sizes can be met. In an application, if the required virtual address segment is a 4KB GPU virtual address space, the 4MB virtual address segment can be directly split. If the desired virtual address segment is a 6MB GPU virtual address space, an 8MB virtual address segment may be split.
Step 130, obtaining the memory space capacity required by the GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the physical page size.
The memory space capacity is the memory space size required by the GPU in actual operation. In this step, the size of the memory space allocated according to the physical address management page size and the physical address management page number needs to be equal to or larger than the capacity of the memory space. The physical address management page size and the physical address management page number are determined according to the memory space capacity and the physical page size, and the dynamic physical page size distribution is realized.
Specifically, there are various ways to determine the physical address management page size and the physical address management page number according to the memory space capacity and the physical page size. Optionally, a page size closest to the memory space capacity is determined among the physical page sizes as the physical address management page size, and thus the physical address management page number is determined.
Alternatively, the page size closest to the memory space is determined from among the physical page sizes, and physical address management page allocation is performed first according to the closest page size. When there is a physical address management page of an incomplete page in the allocation, a page size smaller than the closest page size can be determined in the physical page sizes for the remaining space capacity corresponding to the physical address management page of the incomplete page, so as to avoid waste of memory resources.
Or, each page size in the physical page sizes is used as an allocation basis, and the corresponding required page number and the wasted memory size are respectively determined. And generating an allocation scheme discrimination factor according to the required page number and the wasted memory size. And comparing the multiple allocation schemes according to the discrimination factors, wherein the allocation scheme with the best certainty can be found out to be a balanced scheme between the required number of pages and the size of the wasted memory. The determination mode of the discrimination factors can be various. For example, weights may be set for the number of pages needed and the size of memory wasted, respectively, and the discrimination factor may be determined according to the specific number of pages, size of memory, and weights.
In order to make the size of the physical address management page more reasonable, in an alternative implementation of the embodiment of the present invention, determining the size of the physical address management page and the number of physical address management pages when the physical address is allocated in the memory management according to the memory space capacity and the size of the physical page includes: determining a first target physical size closest to the capacity size of the memory space in the physical page sizes, wherein the first target physical size is used as a first target management page size when physical addresses are allocated in memory management; and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the first target management page size.
Optionally, determining the physical address management page size and the physical address management page number according to the memory space capacity and the first target management page size directly uses the first target management page size as the physical address management page size, and allocates the physical address management page according to the first target management page size, so that the allocated physical address management page number can meet the memory space capacity. That is, the product of the size of the first target management page and the number of physical address management pages is greater than or equal to the capacity of the memory space.
Or determining the physical address management page size and the physical address management page number according to the memory space capacity and the first target management page size, wherein the first target management page number and the residual space capacity are determined by firstly distributing according to the first target management page size. The product of the first target management page size and the first target management page number is added to the residual space capacity to be equal to the memory space capacity. The remaining space capacity is less than the first target management page size. Optionally, the remaining space capacity is allocated by adopting a physical page size smaller than the first target management page size, so that waste of memory resources caused by directly allocating the remaining space capacity by adopting the first target management page size is avoided. Further, the physical address management page size and the physical address management page number can be determined based on the page size and the corresponding page number employed in the physical address management page allocation.
In order to avoid wasting memory resources, in an alternative implementation manner of the embodiment of the present invention, determining, from among physical page sizes, a first target physical size closest to a size of a memory space capacity, as a first target management page size when physical addresses are allocated in memory management, includes: and determining a first target physical size closest to the capacity size of the memory space in the physical page size by adopting a downward alignment mode, wherein the first target physical size is used as a first target management page size when the physical address is allocated in the memory management.
Alternatively, in determining the first target physical dimension, a downward alignment or an upward alignment is used. However, in order to avoid wasting memory resources, the first target physical size is determined in a downward alignment manner. Optionally, a downward alignment mode is adopted, and a first target physical size closest to the memory space capacity size is determined in the physical page sizes, and is used as a first target management page size when the physical address is allocated in the memory management, wherein the first target physical size closest to the memory space capacity size and smaller than the memory space capacity is determined in the physical page sizes, and is used as a first target management page size when the physical address is allocated in the memory management.
For example, when the memory space capacity is equal to or greater than 4MB, 4MB is determined as the first target physical size, which is the first target management page size. When the memory space capacity is greater than or equal to 2MB and less than 4MB, the 2MB is determined as a first target physical size, and the first target physical size is used as a first target management page size. When the memory space capacity is greater than or equal to 64KB and less than 2MB, the 64KB is determined as a first target physical size, and the first target physical size is used as a first target management page size. When the memory space capacity is smaller than 64KB, determining 4KB as a first target physical size which is used as a first target management page size.
And 140, configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table.
Wherein reference may be made to the principles shown in fig. 2 in configuring GPU memory management page tables. However, in the embodiment of the present invention, since the physical address management page size is dynamic, when configuring the GPU memory management page table, additional information needs to be added in the entry to specify the physical address management page size pointed to by the hardware.
Specifically, in an optional implementation manner of the embodiment of the present invention, configuring the GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size, and the physical address management page number includes: and configuring physical address information and corresponding physical address management page sizes in the current GPU memory management page table according to the virtual address management page sizes, the virtual address management page numbers, the physical address management page sizes and the physical address management page numbers.
That is, in addition to filling in the physical address of the next stage page table in the entry of each stage page table, additional information needs to be added to inform the MMU of the corresponding physical page size of the next stage page table. Illustratively, the present embodiment hardware supports 4 physical page sizes (4 MB, 2MB, 64KB, 4 KB). Two bits may be occupied in the entry to distinguish physical page sizes. Such as the lower 2 bits of the entry. For example, 0b00 represents a physical address management page of 4KB, 0b01 represents a physical address management page of 64KB, 0b10 represents a physical address management page of 2MB, and 0b11 represents a physical address management page of 4 MB.
According to the technical scheme, the physical page size supported by hardware in memory management of the GPU and the required virtual address segment are obtained; determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment; acquiring the memory space capacity required by GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in memory management according to the memory space capacity and the physical page size; according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number, the GPU memory management page table is configured to access memory data according to the memory management page table, so that the problem of poor memory data access performance of the GPU is solved, the memory management page table size can be dynamically determined according to the memory space capacity, and the memory data access performance is improved; specifically, memory resource waste caused by oversized page table can be avoided; and the situations of high memory access frequency, low memory data access efficiency and low throughput caused by undersize page tables can be avoided.
Example two
Fig. 4 is a flowchart of a memory management method of a graphics processor according to a second embodiment of the present invention, where the technical solution is further refined, and the technical solution in this embodiment may be combined with each of the alternatives in one or more embodiments. As shown in fig. 4, the method includes:
Step 210, obtaining the physical page size and the required virtual address segment supported by the hardware in the memory management.
Step 220, determining the virtual address management page size and the virtual address management page number when the virtual address is allocated in the memory management according to the physical page size and the virtual address segment.
In an optional implementation manner of the embodiment of the present invention, determining, according to a physical page size and a virtual address field, a virtual address management page size and a virtual address management page number when a virtual address is allocated in memory management includes: determining the upper limit of a virtual address space in GPU memory management according to the width of the address bus; determining the virtual address management page size when the virtual address is distributed in the memory management according to the upper limit of the virtual address space and the physical page size; and determining the virtual address management page number according to the virtual address management page size and the virtual address segment.
In an optional implementation manner of the embodiment of the present invention, determining a virtual address management page size when a virtual address is allocated in memory management according to a virtual address space upper limit and a physical page size includes: among the physical page sizes, a maximum size equal to or smaller than the upper limit of the virtual address space is determined as the virtual address management page size.
Step 230, obtain the memory space capacity required by GPU calculation, and determine the first target physical size closest to the memory space capacity size in the physical page sizes, as the first target management page size when the physical address is allocated in the memory management.
In an optional implementation manner of the embodiment of the present invention, determining, from among the physical page sizes, a first target physical size closest to the memory space capacity size as a first target management page size when allocating physical addresses in memory management includes: and determining a first target physical size closest to the capacity size of the memory space in the physical page size by adopting a downward alignment mode, wherein the first target physical size is used as a first target management page size when the physical address is allocated in the memory management.
Step 240, determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the first target management page size.
In an optional implementation manner of the embodiment of the present invention, determining, according to the memory space capacity and the target management page size, the physical address management page size and the physical address management page number when the physical address is allocated in the memory management includes: determining a first target management page number and a residual space capacity required by taking the first target management page size as an allocation basis according to the memory space capacity; determining a second target physical size closest to the residual space capacity size in the physical page sizes as a second target management page size when physical addresses are allocated in memory management; and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the first target management page size, the first target management page number, the residual space capacity and the second target management page size.
The product of the first target management page size and the first target management page number is added to the residual space capacity to be equal to the memory space capacity. The remaining space capacity is less than the first target management page size. Optionally, the remaining space capacity is allocated by adopting a physical page size smaller than the first target management page size, so that waste of memory resources caused by directly allocating the remaining space capacity by adopting the first target management page size is avoided.
The second target physical size is smaller than the first target management page size. A second target physical size closest to the remaining space capacity size may be determined among the physical page sizes in a downward aligned manner as a second target management page size when physical addresses are allocated in memory management.
Fig. 5 is a flowchart of a physical address management page allocation according to a second embodiment of the present invention. As shown in fig. 5, the allocation physical address management page may specifically be: physical address management page allocation is first performed according to a first target management page size. For example, the first target number of management pages is obtained using the formula Size/page_size1; where Size is the memory space capacity, page_size1 is the first target management page Size, "/" indicates the quotient. The remaining space capacity is obtained using the formula Size% page_size1. Wherein "%" represents taking the remainder. And then, physical address management page allocation is carried out according to the second target management page size. For example, the second target number of pages is obtained using the formula Size2/page_size 2; where Size2 is the remaining space capacity and page_size2 is the second target management page Size. The remaining space capacity is updated using the formula Size 2% page_size2. And returning to the step of determining the second target management page Size according to the remaining space capacity update until the Size 2% page_Size2 is not 0 but is smaller than the minimum physical page Size, or the Size 2% page_Size2 is 0. When the Size 2% page_size2 is not 0 but smaller than the minimum physical page Size, a physical address management page is directly allocated with the minimum physical page Size.
Specifically, the physical address management page size is a first target management page size and all second target management page sizes used in performing physical address management page allocation. The physical address management page number is a first target management page number corresponding to the first target management page size, and each second target management page number corresponding to each second target management page size. When Size 2% page_size2 is not 0 but is less than the minimum physical page Size, the physical address management page Size also includes the minimum physical page Size; the number of physical address management pages further includes one physical address management page corresponding to the smallest physical page size.
By the method, the physical address management page number can be controlled while the memory space is saved, the cache hit error rate introduced by the too small physical address management page during memory data access can be avoided as much as possible through a dynamic allocation mechanism, the memory can still be normally separated when the memory resource is broken, and the problem of memory waste during allocation of the too large physical address management page is avoided.
Step 250, configuring the GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size, and the physical address management page number, so as to access the memory data according to the memory management page table.
In an alternative implementation of the embodiment of the present invention, configuring the GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size, and the physical address management page number includes: and configuring physical address information and corresponding physical address management page sizes in the current GPU memory management page table according to the virtual address management page sizes, the virtual address management page numbers, the physical address management page sizes and the physical address management page numbers.
According to the technical scheme, the physical page size supported by hardware in memory management of the graphic processor and the required virtual address segment are obtained; determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment; acquiring the memory space capacity required by GPU calculation, and determining a first target physical size closest to the memory space capacity size in the physical page sizes, wherein the first target physical size is used as a first target management page size when physical addresses are allocated in memory management; determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the first target management page size; according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number, the GPU memory management page table is configured so as to access the memory data according to the memory management page table, so that the problem of poor memory data access performance of the GPU is solved, the memory management page table size can be dynamically determined according to the memory space capacity, and the memory data access performance is improved; specifically, memory resource waste caused by oversized page table can be avoided; and the situations of high memory access frequency, low memory data access efficiency and low throughput caused by undersize page tables can be avoided.
Example III
Fig. 6 is a schematic diagram of a memory management device of a graphics processor according to a third embodiment of the present invention. As shown in fig. 6, the apparatus includes: a virtual address information acquisition module 610, a virtual address management page determination module 620, a physical address management page determination module 630, and a memory management page table configuration module 640. Wherein:
a virtual address information obtaining module 610, configured to obtain a physical page size and a required virtual address segment supported by hardware in the graphics processor in memory management;
the virtual address management page determining module 620 is configured to determine, according to the physical page size and the virtual address segment, a virtual address management page size and a virtual address management page number when a virtual address is allocated in memory management;
the physical address management page determining module 630 is configured to obtain a memory space capacity required by the GPU calculation, and determine a physical address management page size and a physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the physical page size;
the memory management page table configuration module 640 is configured to configure the GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size, and the physical address management page number, so as to access the memory data according to the memory management page table.
Optionally, the virtual address management page determination module 620 includes:
the virtual address space upper limit determining unit is used for determining the virtual address space upper limit in the GPU memory management according to the address bus width;
the virtual address management page size determining unit is used for determining the virtual address management page size when the virtual address is allocated in the memory management according to the upper limit of the virtual address space and the physical page size;
and the virtual address management page number determining unit is used for determining the virtual address management page number according to the virtual address management page size and the virtual address segment.
Optionally, the virtual address management page size determining unit is specifically configured to:
among the physical page sizes, a maximum size equal to or smaller than the upper limit of the virtual address space is determined as the virtual address management page size.
Optionally, the physical address management page determining module 630 includes:
a first target management page size determining unit configured to determine, among the physical page sizes, a first target physical size closest to the memory space capacity size as a first target management page size when a physical address is allocated in memory management;
and the physical address management page determining unit is used for determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the first target management page size.
Optionally, the physical address management page determining unit is specifically configured to:
determining a first target management page number and a residual space capacity required by taking the first target management page size as an allocation basis according to the memory space capacity;
determining a second target physical size closest to the residual space capacity size in the physical page sizes as a second target management page size when physical addresses are allocated in memory management;
and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the first target management page size, the first target management page number, the residual space capacity and the second target management page size.
Optionally, the first target management page size determining unit is specifically configured to:
and determining a first target physical size closest to the capacity size of the memory space in the physical page size by adopting a downward alignment mode, wherein the first target physical size is used as a first target management page size when the physical address is allocated in the memory management.
Optionally, the memory management page table configuration module 640 includes:
and configuring physical address information and corresponding physical address management page sizes in the current GPU memory management page table according to the virtual address management page sizes, the virtual address management page numbers, the physical address management page sizes and the physical address management page numbers.
The memory management device of the graphic processor provided by the embodiment of the invention can execute the memory management method of the graphic processor provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.
Example IV
Fig. 7 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 7, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the memory management method of a graphics processor.
In some embodiments, the memory management method of the graphics processor may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the memory management method of the graphics processor described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the memory management method of the graphics processor in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (9)
1. A memory management method for a graphics processor, comprising:
acquiring a physical page size and a required virtual address segment supported by hardware in memory management of a Graphics Processor (GPU);
determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment;
acquiring the memory space capacity required by GPU calculation, and determining the physical address management page size and the physical address management page number when the physical address is allocated in memory management according to the memory space capacity and the physical page size;
Configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table;
wherein determining the virtual address management page size and the virtual address management page number when the virtual address is allocated in the memory management according to the physical page size and the virtual address segment comprises:
determining the upper limit of a virtual address space in GPU memory management according to the width of the address bus;
determining the virtual address management page size when virtual addresses are allocated in memory management according to the virtual address space upper limit and the physical page size;
and determining the virtual address management page number according to the virtual address management page size and the virtual address segment.
2. The method of claim 1, wherein determining a virtual address management page size in memory management when virtual addresses are allocated based on the virtual address space upper bound and the physical page size comprises:
and in the physical page size, determining the maximum size which is smaller than or equal to the upper limit of the virtual address space as the virtual address management page size.
3. The method of claim 1, wherein determining the physical address management page size and the physical address management page number for the allocation of physical addresses in memory management based on the memory space capacity and the physical page size comprises:
determining a first target physical size closest to the memory space capacity size in the physical page sizes as a first target management page size when physical addresses are allocated in memory management;
and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the first target management page size.
4. The method of claim 3 wherein determining the physical address management page size and the physical address management page number for the allocation of physical addresses in memory management based on the memory space capacity and the target management page size comprises:
determining a first target management page number and a residual space capacity required by taking the first target management page size as an allocation basis according to the memory space capacity;
determining a second target physical size closest to the residual space capacity size from the physical page sizes as a second target management page size when physical addresses are allocated in memory management;
And determining a physical address management page size and a physical address management page number when the physical address is allocated in memory management according to the first target management page size, the first target management page number, the residual space capacity and the second target management page size.
5. The method of claim 3, wherein determining a first target physical size closest to the memory space capacity size among the physical page sizes as a first target management page size when allocating physical addresses in memory management, comprises:
and determining a first target physical size closest to the capacity size of the memory space in the physical page size by adopting a downward alignment mode, wherein the first target physical size is used as a first target management page size when physical addresses are allocated in memory management.
6. The method of claim 1, wherein configuring a GPU memory management page table based on the virtual address management page size, the virtual address management page number, the physical address management page size, and the physical address management page number, comprises:
and configuring physical address information and corresponding physical address management page sizes in a current GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number.
7. A memory management device for a graphics processor, comprising:
the virtual address information acquisition module is used for acquiring the physical page size and the required virtual address segment supported by hardware in the memory management of the graphic processor GPU;
the virtual address management page determining module is used for determining the size of a virtual address management page and the number of virtual address management pages when virtual addresses are allocated in memory management according to the physical page size and the virtual address segment;
the physical address management page determining module is used for obtaining the memory space capacity required by the GPU calculation and determining the physical address management page size and the physical address management page number when the physical address is allocated in the memory management according to the memory space capacity and the physical page size;
the memory management page table configuration module is used for configuring a GPU memory management page table according to the virtual address management page size, the virtual address management page number, the physical address management page size and the physical address management page number so as to access memory data according to the memory management page table;
wherein, the virtual address management page determining module includes:
the virtual address space upper limit determining unit is used for determining the virtual address space upper limit in the GPU memory management according to the address bus width;
The virtual address management page size determining unit is used for determining the virtual address management page size when the virtual address is allocated in the memory management according to the upper limit of the virtual address space and the physical page size;
and the virtual address management page number determining unit is used for determining the virtual address management page number according to the virtual address management page size and the virtual address segment.
8. An electronic device, the electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the memory management method of the graphics processor of any one of claims 1-6.
9. A computer readable storage medium storing computer instructions for causing a processor to perform the memory management method of a graphics processor according to any one of claims 1-6.
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