CN103793331A - Method and device for managing physical memories - Google Patents

Method and device for managing physical memories Download PDF

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CN103793331A
CN103793331A CN201210429334.1A CN201210429334A CN103793331A CN 103793331 A CN103793331 A CN 103793331A CN 201210429334 A CN201210429334 A CN 201210429334A CN 103793331 A CN103793331 A CN 103793331A
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page table
page
physical
table entry
virtual address
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CN103793331B (en
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梁雄
王国添
胡胜发
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Guangzhou Ankai Microelectronics Co.,Ltd.
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Anyka Guangzhou Microelectronics Technology Co Ltd
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Abstract

An embodiment of the invention discloses a method and a device for managing physical memories. The method and the device are used for optimizing storage structures of resident physical memories. The method in the embodiment of the invention includes initializing page table entries of MMU (memory management unit) conversion page tables of memory management units when a system is started; writing physical page addresses in physical page index tables into data bits of the corresponding page table entries of the MMU conversion page tables; unloading a physical page address stored in a corresponding page table entry of a virtual address page and storing the physical page address in a temporary list when the unmapped optional virtual address page needs to be mapped to a physical memory; writing a corresponding physical page address in the temporary list into data bits of a corresponding page entry of a virtual address page when the optional mapped virtual address page does not need to be mapped to a physical memory. The page table entries of the MMU conversion page tables contain identification bits and the data bits. According to the scheme, the method and the device have the advantages that all or partial physical page index tables can be stored in the MMU conversion page tables according to actual requirements, and accordingly the overhead of the resident physical memories and the overhead of the integral physical memories can be saved.

Description

A kind of physical memory management method and device
Technical field
The present invention relates to physical memory technical field, relate in particular to a kind of physical memory management method and device.
Background technology
At present a lot of terminals are used virtual memory technology to realize little physical memory operation large program.This technology mainly utilizes MMU (Memory Management Unit, memory management unit) that virtual address map is arrived to physical memory addresses, the corresponding program code of virtual address space, and program code actual storage is in physical storage.
Refer to Fig. 1, MMU conversion page table and Physical Page concordance list need to be set, MMU conversion page table is for recording the mapping relations of virtual address to physical memory addresses, and Physical Page concordance list is for recording the corresponding relation of physical memory address to virtual address.The page table entry of MMU conversion page table can use two-stage page table, and page table has three kinds: large page, little page and minimum page, and wherein large page space is 64KB, and little page space is 4KB, and minimum page space is 1KB.Page table entry claims again descriptor, and descriptor has stored physical address and access rights flag.Physical address is the base address of one section of virtual address correspondence in physical memory, and it is a start address, and little page descriptor is the start address of the physical address of 4KB length.
Physical memory is divided into resident part and nonresident portion, and MMU conversion page table and Physical Page concordance list are kept in resident physical memory.The array length of MMU conversion page table and Physical Page concordance list is all directly proportional to the address size of virtual memory.When MMU work, according to the address size of virtual memory and actual mapping relations, will MMU conversion page table and the Physical Page concordance list of corresponding corresponding array length be set, and be stored in resident physical memory.
But setting simultaneously store M MU conversion page table and Physical Page concordance list take a large amount of resident physical memories, increase the expense of overall physical memory.
Summary of the invention
In order to address the above problem, the embodiment of the present invention provides a kind of physical memory management method and device, for optimizing the storage organization of resident physical memory, by implementing the present invention program, can all or part of Physical Page concordance list be saved in MMU conversion page table according to reality, save the expense of resident physical memory, thus the expense of having saved overall physical memory.
A kind of physical memory management method, comprising:
In the time that system starts, the page table entry of initialization memory management unit MMU conversion page table, described page table entry comprises flag and data bit, and described flag is used to indicate the virtual address paging that described page table entry is corresponding and whether is mapped to physical memory, and described data bit is used for storing data;
Physical page address in Physical Page concordance list is write to the data bit of the corresponding page table entry of described MMU conversion page table;
In the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of described virtual address paging is dumped to interim list;
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, physical page address corresponding in described interim list is write to the data bit of the corresponding page table entry of described virtual address paging.
Preferably, describedly further comprise after dumping to interim list being stored in physical page address in the corresponding page table entry of described virtual address paging: revise the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication be mapped to physical memory; Physical memory addresses corresponding to described virtual address paging write to the data bit of described corresponding page table entry.
Preferably, before the described corresponding page table entry that physical page address corresponding in described interim list is write to described virtual address paging, further comprise: revise the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication not be mapped to physical memory; The data bit of corresponding page table entry described in initialization.
Preferably, the page table entry quantity of described MMU conversion page table is identical with the quantity of described virtual address paging; The physical page address quantity of described Physical Page concordance list is identical with the quantity of described virtual address paging.
Preferably, the low level that described flag is described page table entry, is 12; Described data bit is a high position for described page table entry, is 20; Physical page address in described Physical Page concordance list is 16.
Preferably, described MMU conversion page table and described interim list are arranged in resident physical memory.
A kind of physical memory management devices, comprising:
Initialization unit, for in the time that system starts, the page table entry of initialization memory management unit MMU conversion page table, described page table entry comprises flag and data bit, described flag is used to indicate the virtual address paging that described page table entry is corresponding and whether is mapped to physical memory, and described data bit is used for storing data;
The first writing unit, for writing the physical page address of Physical Page concordance list the data bit of the corresponding page table entry of described MMU conversion page table;
Unloading unit, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, dumps to interim list by the physical page address being stored in the corresponding page table entry of described virtual address paging;
The second writing unit, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, writes physical page address corresponding in described interim list the data bit of the corresponding page table entry of described virtual address paging.
Preferably, described physical memory management devices further comprises: revise unit, for revising the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication be mapped to physical memory; Described modification unit, also for revising the flag of described corresponding page table entry, makes virtual address paging corresponding to its described corresponding page table entry of indication not be mapped to physical memory; The 3rd writing unit, for writing physical memory addresses corresponding to described virtual address paging the data bit of described corresponding page table entry; Described initialization unit, also for the data bit of corresponding page table entry described in initialization.
As can be seen from the above technical solutions, the embodiment of the present invention has the following advantages:
In the time that system starts, initialization memory management unit MMU changes the page table entry of page table, Physical Page concordance list is write to the invalid data position of MMU conversion page table, in the time that generation virtual address is switched, part Physical Page concordance list is dumped to interim list.Because Physical Page index table stores in prior art is at resident physical memory, by implementing the present invention program, can save the expense of resident physical memory, thus the expense of having saved overall physical memory.
Accompanying drawing explanation
Fig. 1 is the virtual memory technology schematic diagram of prior art;
Fig. 2 is the physical memory management method process flow diagram of first embodiment of the invention;
Fig. 3 is the virtual memory technology schematic diagram of first embodiment of the invention;
Fig. 4 is the physical memory management method process flow diagram of second embodiment of the invention;
Fig. 5 is the physical memory management devices structural drawing of third embodiment of the invention;
Fig. 6 is the physical memory management devices structural drawing of fourth embodiment of the invention.
Embodiment
Below in conjunction with the Figure of description in the present invention, the technical scheme in invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of physical memory management method, for optimizing the storage organization of resident physical memory, by implementing the inventive method, can all or part of Physical Page concordance list be saved in MMU conversion page table according to reality, save the expense of resident physical memory, thus the expense of having saved overall physical memory.The embodiment of the present invention also provides corresponding physical memory management devices, below will be described in detail respectively.
First embodiment of the invention will be elaborated to a kind of physical memory management method, and physical memory management method idiographic flow refers to Fig. 2 described in the embodiment of the present invention, comprises step:
201, in the time that system starts, the page table entry of initialization MMU conversion page table.
In virtual memory technology, virtual address is evenly divided into paging, and physical memory addresses is also evenly divided into page, and the size of paging and page must be identical.When program code in virtual address is carried out, the program code in the current paging that needs to use is just mapped to the page of physical memory addresses, then in physical memory addresses, carries out the program code in this paging.Between paging after mapping and page, have mapping relations, MMU conversion page table is for recording the mapping relations of virtual address to physical memory addresses.Under normal circumstances, the quantity of physical memory addresses page is than the quantity much less of virtual address paging.
Program code in virtual address is actual is to be stored in the Physical Page of physical storage, the corresponding physical page address of each Physical Page.There is corresponding relation in virtual address and physical memory address, is specially physical page address and virtual address paging exists relation one to one, and Physical Page concordance list is exactly for recording the corresponding relation of physical memory address to virtual address.When program code in virtual address is carried out, program code in the current paging that needs to use is just mapped to the page of physical memory addresses, specifically inquire about physical page address corresponding to this paging according to Physical Page concordance list, then from this Physical Page, read corresponding program code and write this page.
An example, refers to Fig. 3, and virtual address is divided into b01~b13 totally 13 pagings, and physical memory addresses is divided into c01~c06 totally 6 pages, and it is a01~a13 totally 13 Physical Page that physical storage comprises sequence number.In the time that the program code in the paging that sequence number is b02 need to be carried out, know that by inquiry Physical Page concordance list the program code needing is stored in the Physical Page that sequence number is a02, from the physical page address of a02 Physical Page, read this program code, and this program code is write in the page that physical memory sequence number is c04.Meanwhile, need to change the mapping relations that are written into this paging and page in page table at MMU.
MMU conversion page table comprises multiple page table entries, and page table entry comprises flag and data bit, and flag is used to indicate the virtual address paging that this page table entry is corresponding and whether is mapped to physical memory, and data bit is used for storing data.Page table entry quantity in a MMU conversion table is identical with the quantity of virtual address paging.In Physical Page concordance list, record multiple physical page address, its physical page address quantity is also identical with the quantity of virtual address paging.
Accept above-mentioned example, MMU conversion page table comprises 13 page table entries, 13 pagings of the corresponding virtual address of these 13 page table entries.In the time that the program code in the paging that sequence number is b02 need to be carried out, program code in the Physical Page that is a02 by sequence number writes after the page that physical memory sequence number is c04, revise the flag of corresponding page table entry, make the paging that this flag indication sequence number is b02 mapped, the physical memory addresses of the page that is simultaneously c04 by sequence number writes the data bit of this page table entry.
In this step, in the time that system starts, the page table entry of initialization MMU conversion page table.Be specially: in the time that system starts, chip loads the resident part of one section of code to physical memory automatically, does not need to consider Physical Page index value so the virtual address of this section of code does not participate in switching.
MMU is firm initialized time, and MMU conversion page table is filled in flag and data bit according to whether mapping situation.
The corresponding physical memory addresses mapping of virtual address of loading code is set up, so MMU page table entry will arrange the state of flag for shining upon.The state that in MMU conversion page table, page table entry corresponding to other virtual addresses arranges flag is not for shining upon, and data bit is invalid.
Flag in each page table entry of initialized MMU conversion page table for mapping status not, data bit invalid, i.e. the virtual address of all pagings is not all mapped to physical memory addresses.
Accept above-mentioned example, initialized MMU conversion page table comprises 13 page table entries, and all flags of these 13 page table entries are mapping status not, and all data bit all do not have data writing.
202, the physical page address in Physical Page concordance list is write to the data bit of the corresponding page table entry of MMU conversion page table.
The physical page address quantity that Physical Page concordance list is recorded is identical with the quantity of virtual address paging.Physical Page concordance list is all write in MMU conversion page table, thereby space need not be set independently again for storing Physical Page concordance list.
Accept above-mentioned example, Physical Page concordance list has been recorded 13 physical page address, and 13 paging correspondences of corresponding indication virtual address are in 13 physical page address of physical storage.The physical page address that is a01~a13 Physical Page by sequence number in Physical Page concordance list writes the data bit that sequence number is the corresponding page table entry of MMU conversion page table of b01~b13 paging successively.
203,, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of virtual address paging is dumped to interim list.
In the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of virtual address paging is dumped to interim list, interim list storage is in resident physical memory.Revise the flag in this page table entry simultaneously, virtual address paging corresponding to its indication page table entry is mapped in physical memory addresses, and this physical memory addresses write to the data bit of this page table entry.
Accept above-mentioned example, in the time that the program code in the paging that sequence number is b02 need to be carried out, the physical page address of the preservation in page table entry corresponding with b02 paging in MMU conversion table is transferred to interim list.Then revise the flag of this page table entry, virtual address paging corresponding to its indication page table entry is mapped in physical memory addresses, and the physical memory addresses of the page that is c04 by sequence number writes the data bit of this page table entry.
204,, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, physical page address corresponding in interim list is write to the data bit of the corresponding page table entry of virtual address paging.
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, physical page address corresponding in interim list is write to the data bit of the corresponding page table entry of virtual address paging, interim list storage is in resident physical memory, and the physical page address amount of the Physical Page concordance list that it can hold is identical with the page quantity of physical memory addresses.Retain flag in this page table entry for mapping status not simultaneously, virtual address paging corresponding to its indication page table entry is not mapped in physical memory addresses, revert to the state of this page table entry in step 201.
Accept above-mentioned example, in the time that the program code in the paging that sequence number is b02 need to be carried out, the physical page address of the preservation in page table entry corresponding with b02 paging in MMU conversion table is transferred to interim list.Then revise the flag of this page table entry, virtual address paging corresponding to its indication page table entry is mapped in physical memory addresses, and the physical memory addresses of the page that is c04 by sequence number writes the data bit of this page table entry.
In the present embodiment, in the time that system starts, initialization memory management unit MMU changes the page table entry of page table, Physical Page concordance list is write to the invalid data position of MMU conversion page table, in the time that generation virtual address is switched, part Physical Page concordance list is dumped to interim list.Because Physical Page index table stores in prior art is at resident physical memory, by implementing the present invention program, can save the expense of resident physical memory, thus the expense of having saved overall physical memory.
Second embodiment of the invention will remark additionally to the physical memory management method described in the first embodiment, and the physical memory management method idiographic flow described in the present embodiment refers to Fig. 4, comprises step:
401, in the time that system starts, the page table entry of initialization MMU conversion page table.
MMU conversion page table comprises multiple page table entries, and page table entry comprises flag and data bit, and flag is used to indicate the virtual address paging that this page table entry is corresponding and whether is mapped to physical memory, and data bit is used for storing data.Page table entry quantity in a MMU conversion table is identical with the quantity of virtual address paging.In Physical Page concordance list, record multiple physical page address, its physical page address quantity is also identical with the quantity of virtual address paging.
In this step, in the time that system starts, the page table entry of initialization MMU conversion page table.Flag in each page table entry of initialized MMU conversion page table for mapping status not, data bit invalid, i.e. the virtual address of all pagings is not all mapped to physical memory addresses.
402, the physical page address in Physical Page concordance list is write to the data bit of the corresponding page table entry of MMU conversion page table.
The present embodiment page table entry has used little page, also can use other two kinds of modes.High 20 of little page descriptor is data bit, and low 12 is flag.
Therefore, the low level that flag is page table entry, is 12, and the high position that data bit is page table entry is 20, and the physical page address in Physical Page concordance list is 16.Index value for the Nand flash memory of general capacity take 4KB page as unit is less than 16, so preserve index values with 16.Therefore, the data bit of 20 is large enough to hold the physical page address of 16.
The physical page address quantity of recording due to Physical Page concordance list is identical with the quantity of virtual address paging.Therefore Physical Page concordance list can all be write in MMU conversion page table, thereby space need not be set independently again for storing Physical Page concordance list.
403,, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of virtual address paging is dumped to interim list.
Wherein, MMU conversion page table is all arranged in resident physical memory with interim list.
404, revise the flag of corresponding page table entry.
In the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, revise the flag of corresponding page table entry, make it indicate the virtual address paging that this correspondence page table entry is corresponding to be mapped to physical memory.
405, physical memory addresses corresponding virtual address paging is write to the data bit of corresponding page table entry.
406,, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, revise the flag of corresponding page table entry.
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, revise the flag of corresponding page table entry, make it indicate the virtual address paging that corresponding page table entry is corresponding not to be mapped to physical memory.
407, the data bit of the corresponding page table entry of initialization.
The data bit of the corresponding page table entry of initialization.Even if the data bit in this page table entry is invalid, this invalid data potential energy is enough in and re-writes corresponding physical page address.
408, physical page address corresponding in interim list is write to the data bit of the corresponding page table entry of virtual address paging.
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, physical page address corresponding in interim list is write to the data bit of the corresponding page table entry of virtual address paging, interim list storage is in resident physical memory, and the physical page address amount of the Physical Page concordance list that it can hold is identical with the page quantity of physical memory addresses.Retain flag in this page table entry for mapping status not simultaneously, virtual address paging corresponding to its indication page table entry is not mapped in physical memory addresses.
For example, in an embedded platform, virtual address length is 12MB, and physical memory addresses length is 120KB.
In MMU conversion page table, preserved the mapping relations of virtual address to physical memory addresses, a page table entry length is 4B, wherein, high 20 is data bit, can preserve 4KB virtual address, is specially the address of a virtual address paging, low 12 is flag, is used to indicate corresponding virtual.
Virtual address is saved in Physical Page concordance list mem2store_tbl to the index information of physical memory address, and its concrete form is variable array, and the preservation type of Physical Page concordance list is (2B).
Be multiplied by the preservation type 2B of Physical Page concordance list divided by virtual address Page Length (4KB) therefore the variable array length of Physical Page concordance list mem2store_tbl equals Virtual Space length (12MB), calculating formula is again:
(12×1024×1024)×2÷(4×1024)=6×1024=6KB。
According to the inventive method, Physical Page concordance list is write to MMU conversion page table, be provided with interim list ram2store_tbl, wherein 20KB is as resident area, therefore the variable array length calculating formula of interim list ram2store_tbl is:
[(120-20)×1024]×2÷(4×1024)=50B。
By the inventive method, the corresponding expense of preserving Physical Page concordance list in resident space is compressed to 50B by 6KB.
The detailed description of the each step of the present embodiment refers to the relevant record in the first embodiment, repeats no more here.
In the present embodiment, in the time that system starts, initialization memory management unit MMU changes the page table entry of page table, Physical Page concordance list is write to the invalid data position of MMU conversion page table, in the time that generation virtual address is switched, part Physical Page concordance list is dumped to interim list.Because Physical Page index table stores in prior art is at resident physical memory, by implementing the present invention program, can save the expense of resident physical memory, thus the expense of having saved overall physical memory.
Third embodiment of the invention will be elaborated to a kind of physical memory management devices, in the physical memory management devices described in the present embodiment, comprise one or more unit for realizing one or more steps of preceding method.Therefore, the description of each step in preceding method is applicable to corresponding unit in this physical memory management devices.Described in the present embodiment, physical memory management devices concrete structure refers to Fig. 5, comprising:
Initialization unit 501, the first writing unit 502, unloading unit 503 and the second writing unit 504.
Wherein, initialization unit 501, the first writing unit 502, the second writing unit 503, the second writing unit 504 communicate to connect with MMU conversion page table respectively.
Initialization unit 501, in the time that system starts, the page table entry of initialization memory management unit MMU conversion page table.
MMU conversion page table comprises multiple page table entries, and page table entry comprises flag and data bit, and flag is used to indicate the virtual address paging that this page table entry is corresponding and whether is mapped to physical memory, and data bit is used for storing data.Page table entry quantity in a MMU conversion table is identical with the quantity of virtual address paging.In Physical Page concordance list, record multiple physical page address, its physical page address quantity is also identical with the quantity of virtual address paging.
In the time that system starts, the page table entry of initialization unit 501 initialization MMU conversion page tables.Flag in each page table entry of initialized MMU conversion page table is left not mapping status, data bit is invalid, i.e. the virtual address of all pagings is not all mapped to physical memory addresses.
The first writing unit 502, for writing the physical page address of Physical Page concordance list the data bit of the corresponding page table entry of MMU conversion page table.
The physical page address quantity that Physical Page concordance list is recorded is identical with the quantity of virtual address paging.Physical Page concordance list is all write in MMU conversion page table, thereby space need not be set independently again for storing Physical Page concordance list.
Unloading unit 503, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, dumps to interim list by the physical page address being stored in the corresponding page table entry of virtual address paging.
In the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of virtual address paging is dumped to interim list by unloading unit 503, and interim list storage is in resident physical memory.Revise the flag in this page table entry simultaneously, virtual address paging corresponding to its indication page table entry is mapped in physical memory addresses, and this physical memory addresses write to the data bit of this page table entry.
The second writing unit 504, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, writes physical page address corresponding in interim list the data bit of the corresponding page table entry of virtual address paging.
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, the second writing unit 504 writes physical page address corresponding in interim list the data bit of the corresponding page table entry of virtual address paging, interim list storage is in resident physical memory, and the physical page address amount of the Physical Page concordance list that it can hold is identical with the page quantity of physical memory addresses.Retain flag in this page table entry for mapping status not simultaneously, virtual address paging corresponding to its indication page table entry is not mapped in physical memory addresses.
In the present embodiment, in the time that system starts, the page table entry of initialization unit 501 initialization memory management unit MMU conversion page tables, the first writing unit 502 writes Physical Page concordance list the invalid data position of MMU conversion page table, in the time that generation virtual address is switched, part Physical Page concordance list is dumped to interim list by unloading unit 503.Because Physical Page index table stores in prior art is at resident physical memory, by implementing the present invention program, can save the expense of resident physical memory, thus the expense of having saved overall physical memory.
Fourth embodiment of the invention will remark additionally to the physical memory management devices described in the 3rd embodiment, in the physical memory management devices described in the present embodiment, comprises one or more unit for realizing one or more steps of preceding method.Therefore, the description of each step in preceding method is applicable to corresponding unit in this physical memory management devices.Described in the present embodiment, physical memory management devices concrete structure refers to Fig. 6, comprising:
Initialization unit 601, the first writing unit 602, unloading unit 603, modification unit 604 and the second writing unit 605.
Wherein, initialization unit 601, the first writing unit 602, unloading unit 603, modification unit 604, the second writing unit 605 communicate to connect with MMU conversion page table respectively.
Initialization unit 601, in the time that system starts, the page table entry of initialization memory management unit MMU conversion page table.
MMU conversion page table comprises multiple page table entries, and page table entry comprises flag and data bit, and flag is used to indicate the virtual address paging that this page table entry is corresponding and whether is mapped to physical memory, and data bit is used for storing data.Page table entry quantity in a MMU conversion table is identical with the quantity of virtual address paging.In Physical Page concordance list, record multiple physical page address, its physical page address quantity is also identical with the quantity of virtual address paging.
In the time that system starts, the page table entry of initialization unit 601 initialization MMU conversion page tables.Flag in each page table entry of initialized MMU conversion page table is left not mapping status, data bit is invalid, i.e. the virtual address of all pagings is not all mapped to physical memory addresses.
The first writing unit 602, for writing the physical page address of Physical Page concordance list the data bit of the corresponding page table entry of MMU conversion page table.
Wherein, the low level that flag is page table entry, is 12, and the high position that data bit is page table entry is 20, and the physical page address in Physical Page concordance list is 16.Therefore, the data bit of 20 is large enough to hold the physical page address of 16.
The physical page address quantity of recording due to Physical Page concordance list is identical with the quantity of virtual address paging.Therefore Physical Page concordance list can all be write in MMU conversion page table, thereby space need not be set independently again for storing Physical Page concordance list.
Unloading unit 603, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, dumps to interim list by the physical page address being stored in the corresponding page table entry of virtual address paging.
Wherein, MMU conversion page table is all arranged in resident physical memory with interim list.
Revise unit 604, for revising the flag of corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication be mapped to physical memory.
The second writing unit 605, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, writes physical page address corresponding in interim list the data bit of the corresponding page table entry of virtual address paging.
Revise unit 604, also for revising the flag of corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication not be mapped to physical memory.
The 3rd writing unit, for writing physical memory addresses corresponding to described virtual address paging the data bit of described corresponding page table entry;
Initialization unit 601, also for the data bit of corresponding page table entry described in initialization.
The data bit of the corresponding page table entry of initialization.Even if the data bit in this page table entry is invalid, this invalid data potential energy is enough in and re-writes corresponding physical page address.
In the present embodiment, in the time that system starts, the page table entry of initialization unit 601 initialization memory management unit MMU conversion page tables, the first writing unit 602 writes Physical Page concordance list the invalid data position of MMU conversion page table, in the time that generation virtual address is switched, part Physical Page concordance list is dumped to interim list by unloading unit 603.Because Physical Page index table stores in prior art is at resident physical memory, by implementing the present invention program, can save the expense of resident physical memory, thus the expense of having saved overall physical memory.
One of ordinary skill in the art will appreciate that all or part of step realizing in above-described embodiment method is can carry out the hardware that instruction is relevant by program to complete, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium of mentioning can be ROM (read-only memory), disk or CD etc.
Above a kind of physical memory management method provided by the present invention and device are described in detail, for one of ordinary skill in the art, according to the thought of the embodiment of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.

Claims (8)

1. a physical memory management method, is characterized in that, comprising:
In the time that system starts, the page table entry of initialization memory management unit MMU conversion page table, described page table entry comprises flag and data bit, and described flag is used to indicate the virtual address paging that described page table entry is corresponding and whether is mapped to physical memory, and described data bit is used for storing data;
Physical page address in Physical Page concordance list is write to the data bit of the corresponding page table entry of described MMU conversion page table;
In the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, the physical page address being stored in the corresponding page table entry of described virtual address paging is dumped to interim list;
In the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, physical page address corresponding in described interim list is write to the data bit of the corresponding page table entry of described virtual address paging.
2. method according to claim 1, is characterized in that, describedly further comprises after dumping to interim list being stored in physical page address in the corresponding page table entry of described virtual address paging:
Revise the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication be mapped to physical memory;
Physical memory addresses corresponding to described virtual address paging write to the data bit of described corresponding page table entry.
3. method according to claim 1 and 2, is characterized in that, before the described corresponding page table entry that physical page address corresponding in described interim list is write to described virtual address paging, further comprises:
Revise the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication not be mapped to physical memory;
The data bit of corresponding page table entry described in initialization.
4. method according to claim 1 and 2, is characterized in that,
The page table entry quantity of described MMU conversion page table is identical with the quantity of described virtual address paging;
The physical page address quantity of described Physical Page concordance list is identical with the quantity of described virtual address paging.
5. method according to claim 1 and 2, is characterized in that,
Described flag is the low level of described page table entry, is 12;
Described data bit is a high position for described page table entry, is 20;
Physical page address in described Physical Page concordance list is 16.
6. method according to claim 1 and 2, is characterized in that,
Described MMU conversion page table and described interim list are arranged in resident physical memory.
7. a physical memory management devices, is characterized in that, comprising:
Initialization unit, for in the time that system starts, the page table entry of initialization memory management unit MMU conversion page table, described page table entry comprises flag and data bit, described flag is used to indicate the virtual address paging that described page table entry is corresponding and whether is mapped to physical memory, and described data bit is used for storing data;
The first writing unit, for writing the physical page address of Physical Page concordance list the data bit of the corresponding page table entry of described MMU conversion page table;
Unloading unit, in the time that unmapped arbitrary virtual address paging need to be mapped to physical memory, dumps to interim list by the physical page address being stored in the corresponding page table entry of described virtual address paging;
The second writing unit, in the time that arbitrary virtual address paging of having shone upon does not need to be mapped to physical memory, writes physical page address corresponding in described interim list the data bit of the corresponding page table entry of described virtual address paging.
8. device according to claim 7, is characterized in that, described physical memory management devices further comprises:
Revise unit, for revising the flag of described corresponding page table entry, make virtual address paging corresponding to its described corresponding page table entry of indication be mapped to physical memory;
Described modification unit, also for revising the flag of described corresponding page table entry, makes virtual address paging corresponding to its described corresponding page table entry of indication not be mapped to physical memory;
The 3rd writing unit, for writing physical memory addresses corresponding to described virtual address paging the data bit of described corresponding page table entry;
Described initialization unit, also for the data bit of corresponding page table entry described in initialization.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107992569A (en) * 2017-11-29 2018-05-04 北京小度信息科技有限公司 Data access method, device, electronic equipment and computer-readable recording medium
CN112199678A (en) * 2020-09-25 2021-01-08 杭州安恒信息技术股份有限公司 Online evidence obtaining method and device, computer equipment and readable storage medium
CN115640241A (en) * 2022-10-08 2023-01-24 中科驭数(北京)科技有限公司 Address pool-based memory conversion table item management method, query method and device
CN115794667A (en) * 2023-01-19 2023-03-14 北京象帝先计算技术有限公司 Memory management method, system, component and equipment
CN116204453A (en) * 2022-12-23 2023-06-02 科东(广州)软件科技有限公司 Data access method, device, equipment and storage medium of multi-core system
CN116563089A (en) * 2023-07-11 2023-08-08 南京砺算科技有限公司 Memory management method, device and equipment of graphic processor and storage medium
CN116681578A (en) * 2023-08-02 2023-09-01 南京砺算科技有限公司 Memory management method, graphic processing unit, storage medium and terminal equipment

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184142A (en) * 2011-04-19 2011-09-14 中兴通讯股份有限公司 Method and device for reducing central processing unit (CPU) resource consumption by using giant page mapping
US20120185667A1 (en) * 2009-09-25 2012-07-19 Gandhi Kamlesh Virtual-memory system with variable-sized pages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120185667A1 (en) * 2009-09-25 2012-07-19 Gandhi Kamlesh Virtual-memory system with variable-sized pages
CN102184142A (en) * 2011-04-19 2011-09-14 中兴通讯股份有限公司 Method and device for reducing central processing unit (CPU) resource consumption by using giant page mapping

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CN107992569B (en) * 2017-11-29 2020-10-13 北京小度信息科技有限公司 Data access method and device, electronic equipment and computer readable storage medium
CN112199678A (en) * 2020-09-25 2021-01-08 杭州安恒信息技术股份有限公司 Online evidence obtaining method and device, computer equipment and readable storage medium
CN112199678B (en) * 2020-09-25 2024-04-09 杭州安恒信息技术股份有限公司 Method, device, computer equipment and readable storage medium for online evidence obtaining
CN115640241A (en) * 2022-10-08 2023-01-24 中科驭数(北京)科技有限公司 Address pool-based memory conversion table item management method, query method and device
CN116204453A (en) * 2022-12-23 2023-06-02 科东(广州)软件科技有限公司 Data access method, device, equipment and storage medium of multi-core system
CN115794667A (en) * 2023-01-19 2023-03-14 北京象帝先计算技术有限公司 Memory management method, system, component and equipment
CN116563089A (en) * 2023-07-11 2023-08-08 南京砺算科技有限公司 Memory management method, device and equipment of graphic processor and storage medium
CN116563089B (en) * 2023-07-11 2023-10-13 南京砺算科技有限公司 Memory management method, device and equipment of graphic processor and storage medium
CN116681578A (en) * 2023-08-02 2023-09-01 南京砺算科技有限公司 Memory management method, graphic processing unit, storage medium and terminal equipment
CN116681578B (en) * 2023-08-02 2023-12-19 南京砺算科技有限公司 Memory management method, graphic processing unit, storage medium and terminal equipment

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