CN114936173A

CN114936173A - Read-write method, device, equipment and storage medium of eMMC device

Info

Publication number: CN114936173A
Application number: CN202210684491.0A
Authority: CN
Inventors: 梁宏沛; 张敏光; 黄�俊; 周文龙; 潘坪
Original assignee: Kedong Guangzhou Software Technology Co Ltd
Current assignee: Kedong Guangzhou Software Technology Co Ltd
Priority date: 2022-06-16
Filing date: 2022-06-16
Publication date: 2022-08-23
Anticipated expiration: 2042-06-16
Also published as: CN114936173B

Abstract

The invention discloses a read-write method, a read-write device, read-write equipment and a storage medium of an eMMC device. The method comprises the following steps: configuring a read-write mode of an eMMC device and a pre-designed eMMC read-write scheduler, wherein the read-write mode comprises a CPU cache read-write mode and a DMA read-write mode; when the eMMC read-write request is obtained through the eMMC read-write scheduler, a CPU cache read-write mode or a DMA read-write mode is called, and read-write operation on an eMMC device is achieved. By configuring the read-write mode of the eMMC device and a pre-designed eMMC read-write scheduler, different read-write modes can be called to carry out read-write operation on the eMMC device according to read-write requests, the read-write speed can be greatly improved due to the adoption of cache when the CPU cache read-write mode is called, the CPU does not need to be occupied when the DMA read-write mode is called, CPU resources are saved, and efficient read-write of the eMMC device is realized under the condition that resources are reserved for other services in the system.

Description

Read-write method, device, equipment and storage medium of eMMC device

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a read-write method, a read-write device, read-write equipment and a storage medium of an eMMC device.

Background

An Embedded multimedia controller (eMMC) consists of an Embedded memory solution with an MMC (multimedia Card) interface, a flash memory device and a host controller.

When a current microkernel operating system reads and writes an eMMC device, a CPU (central processing unit) is used for reading and writing data by operating a memory address, and the memory operates the eMMC device through an MMC interface.

However, program instructions run by the CPU are in the DDR memory, so that the CPU needs to execute a large number of instructions when reading and writing the eMMC device, and each instruction needs to access the DDR memory, which not only reduces the reading and writing speed of the eMMC device, but also affects normal operation of other services of the microkernel operating system because a large amount of CPU resources in the microkernel operating system are occupied.

Disclosure of Invention

The invention provides a read-write method, a device, equipment and a storage medium of an eMMC device, and aims to realize efficient read-write of the eMMC device.

According to an aspect of the present invention, there is provided a method for reading and writing an eMMC device, including: configuring a read-write mode of an eMMC device and a pre-designed eMMC read-write scheduler, wherein the read-write mode comprises a CPU cache read-write mode and a DMA read-write mode;

and when the eMMC read-write scheduler acquires an eMMC read-write request, calling the CPU cache read-write mode or the DMA read-write mode to realize the read-write operation of the eMMC device.

According to another aspect of the present invention, there is provided a read/write apparatus for an eMMC device, including:

the eMMC device comprises a configuration module, a data processing module and a control module, wherein the configuration module is used for configuring a read-write mode of an eMMC device and a pre-designed eMMC read-write scheduler, and the read-write mode comprises a CPU cache read-write mode and a DMA read-write mode;

and the eMMC device read-write module is used for calling the CPU cache read-write mode or the DMA read-write mode to realize the read-write operation of the eMMC device when the eMMC read-write scheduler acquires an eMMC read-write request.

According to another aspect of the present invention, there is provided an electronic apparatus including:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores a computer program executable by the at least one processor, the computer program being executable by the at least one processor to enable the at least one processor to perform the method according to any of the embodiments of the invention.

According to another aspect of the present invention, there is provided a computer-readable storage medium having stored thereon computer instructions for causing a processor to execute a method according to any one of the embodiments of the present invention.

According to the technical scheme of the embodiment of the invention, the read-write mode of the eMMC device and the pre-designed eMMC read-write scheduler are configured, so that different read-write modes can be called to carry out read-write operation on the eMMC device according to read-write requests, the cache is adopted when the CPU cache read-write mode is called, the read-write speed can be greatly improved, the CPU is not occupied when the DMA read-write mode is called, the CPU resource is saved, and the efficient read-write of the eMMC device is realized under the condition that resources are reserved for other services in the system.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present invention, nor do they necessarily limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a flowchart of a read-write method for an eMMC device according to an embodiment of the present invention;

fig. 2 is an application framework diagram of a read/write method for an eMMC device according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a preconfigured eMMC device scheduler according to an embodiment of the present invention;

fig. 4 is a flowchart of a read-write method of an eMMC device according to a second embodiment of the present invention;

fig. 5 is a schematic structural diagram of a read-write apparatus for an eMMC device according to a third embodiment of the present invention;

fig. 6 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example one

Fig. 1 is a flowchart of a read-write method for an eMMC device according to an embodiment of the present invention, where this embodiment is applicable to a case of reading from and writing to an eMMC device in a microkernel operating system, and the method may be executed by a read-write apparatus for an eMMC device according to an embodiment of the present invention, where the read-write apparatus may be implemented in hardware and/or software, and the apparatus may be configured in an electronic device. As shown in fig. 1, the method includes:

and step S101, configuring a read-write mode of the eMMC device and a pre-designed eMMC read-write scheduler.

Optionally, configuring a read-write mode of the eMMC device includes: configuring a drive of an eMMC device, and enabling all memory operations of an eMMC program to be cached; and configuring the drive of the eMMC device, and mapping the memory address of the eMMC operation to the DMA.

Optionally, configuring a drive of the eMMC device, and after enabling Cache of all memory operations of the eMMC program, further includes: determining a current instruction executed by a CPU in a memory; and transferring the specified number of target instructions associated with the current instruction from the memory to the Cache.

Specifically, the read-write mode in this embodiment includes a CPU cache read-write mode and a DMA read-write mode. As shown in fig. 2, which is an application framework diagram of the present embodiment, when configuring a drive of an eMMC device, specifically, an enable _ Cache () in an eMMC driver, so that all memory operations of the eMMC program are Cache enabled. And when the memory contains 100 instructions, the current instruction executed by the CPU in the memory is determined to be the 11 th instruction, and under the condition that the capacity of the Cache is 10 instructions, the 11 th to 21 th instructions are taken as target instructions to be transferred to the Cache from the memory, so that the configuration of the read-write mode of the CPU Cache is realized. In addition, when the drive of the eMMC device is configured, the Memory address of the eMMC operation is mapped into Direct Memory Access (DMA), so that the configuration of a DMA read-write mode is realized, and the Access to the eMMC device is directly realized through the DMA according to the mapping relation without occupying the Memory.

Fig. 3 is a schematic structural diagram of a preconfigured eMMC read-write scheduler, which specifically includes an API module providing a read-write interface for a user, a CPU mode read-write module for calling a CPU cache read-write mode, a DMA mode read-write module for calling a DMA read-write mode, an eMMC drive initialization module, and an eMMC resource isolation mutual exclusion module. The eMMC resource isolation mutual exclusion module is used for isolating mutual exclusion of resources of the eMMC device and ensuring that no conflict occurs when the eMMC device is read and written by adopting different reading and writing modes.

It should be noted that the API module that provides a Read/Write interface for a user mainly includes an eMMC Read/Write function, for example, a Read function eMMC _ Read () or a Write function eMMC _ Write (), and also configures a Read/Write duty configuration file eMMC _ qos.config in the eMMC Read/Write scheduler in advance, where the Read/Write duty configuration file specifically includes a Read/Write mode matched to each address resource in the eMMC device.

Optionally, configuring an eMMC read-write scheduler includes: a CPU mode read-write interface and a DMA mode read-write interface for accessing the eMMC device are provided through the drive of the eMMC device; and performing read-write packaging on the CPU mode read-write interface through the CPU mode read-write module, and performing read-write packaging on the DMA mode read-write interface through the DMA mode read-write module.

Optionally, the pre-designed eMMC read-write scheduler further includes: an eMMC resource isolation mutual exclusion module; when an eMMC read-write scheduler is configured, a pre-configured read-write proportion configuration file is called, and the read-write proportion configuration file comprises read-write modes matched with each address resource in an eMMC device; and performing isolation and mutual exclusion operation on resources under each address in the eMMC device through the eMMC resource isolation and mutual exclusion module based on the read-write proportion configuration file.

Specifically, when the system is determined to be powered on and started, the eMMC resource isolation and mutual exclusion module performs isolation and mutual exclusion operation on resources under each address in the eMMC device based on the read-write proportion configuration file. For example, the read-write mode matched with the resource 1 at the address x in the eMMC device included in the read-write duty configuration file is a CPU cache read-write mode, and the read-write mode matched with the resource 2 at the address y is a DMA read-write mode. Isolating and mutually exclusive the resource 1 and the resource 2 through the eMMC resource isolation and mutual exclusion module according to the read-write proportion configuration file, namely configuring the eMMC device, so that only a CPU cache read-write mode can be adopted for the resource 1 under the address x, and the read-write operation on the resource 1 under the address x cannot be realized when a DMA read-write mode is adopted; similarly, only a DMA read-write mode can be adopted for the resource 2 at the address y, and when a CPU cache read-write mode is adopted, the read-write operation on the resource 2 at the address y cannot be realized. In addition, the drive of the eMMC device is initialized through the eMMC drive initialization module so as to provide interfaces corresponding to different modes for accessing the eMMC device, such as a CPU cache read-write mode interface and a DMA read-write mode interface.

And step S102, when the eMMC read-write scheduler acquires the eMMC read-write request, calling a CPU cache read-write mode or a DMA read-write mode to realize the read-write operation on the eMMC device.

Optionally, when the eMMC read-write scheduler obtains the eMMC read-write request, the CPU cache read-write mode or the DMA read-write mode is called, including: when receiving an eMMC read-write request input by a user through an API module, extracting a read-write address of an eMMC device from the eMMC read-write request; inquiring a read-write proportion configuration file according to the read-write address, and determining a read-write mode matched with the resource under the read-write address; and calling a CPU cache read-write mode or a DMA read-write mode according to the matched read-write mode.

In a specific implementation, a Read initial address x input by a user and a Read data request with a Read-write length of 2 are received through an eMMC _ Read () function in a user operation API module, Read addresses x1 and x2 of an eMMC device are extracted from the Read-write request, a Read-write duty configuration file is queried according to the Read-write addresses, and a Read-write mode matched with resources at the Read address is determined to be a DMA Read-write mode.

In a specific implementation, when the read-write mode is determined to be the CPU cache read-write mode, the CPU cache read-write mode interface is called by the CPU mode read-write module in the eMMC read-write scheduler, and the read-write request is sent to the CPU through the CPU cache read-write mode interface. For example, when the read data request includes a read initial address x and the read-write length is 2, the CPU executes a first line instruction "send the read data request to the eMMC device" from the cache, and when the CPU acquires a response from the eMMC device, continues to access a second instruction "read initial address data" in the cache, and sends the second instruction "read initial address data" to the eMMC device, receives a resource 1 at the x1 address fed back by the eMMC device, and writes the resource 1 into the memory; and then continuing to access a third instruction in the cache, namely 'next address data after the initial address is read', sending the third instruction to the eMMC device, receiving the resource 2 under the x2 address fed back by the eMMC device, and writing the resource 2 into the memory. Of course, the embodiment is only an example of the read operation, and the principle of the write operation is substantially the same as that of the above operation, and the details are not described in the embodiment again.

It should be noted that the cache in this embodiment is used for dynamically transferring instructions from the memory, and when one instruction in the cache is executed completely, new instructions are sequentially transferred from the memory to the cache, so that the CPU only needs to access the cache without accessing the memory when executing a program instruction, thereby improving the read-write efficiency of the eMMC device.

In another specific implementation, when the read-write mode is determined to be the DMA read-write mode, the DMA read-write mode interface is called by the DMA read-write module, the read-write request is sent to the DMA unit through the DMA read-write mode interface, and the read-write operation on the eMMC device is directly executed through the DMA unit. For example, when the read data request includes a read initial address x and the read-write length is 2, the CPU directly sends the data request to the eMMC device, and writes the resource 1 at the x1 address and the resource 2 at the x2 address fed back by the eMMC device into the memory, so that when the eMMC reads data in the DMA read-write mode, the DMA "from the peripheral to the memory" is used to read the data of the eMMC device. Of course, in this embodiment, only the read operation is taken as an example, and when data is written to the eMMC device, the data is written to the eMMC device in a manner of "from the memory to the peripheral" using DMA.

It is worth mentioning that the eMMC device is read and written by combining the two read-write modes through the scheduling coordination of the eMMC read-write scheduler, so that the read-write of the optimal and most efficient eMMC equipment is realized on the premise of reserving system resources for other services under the condition that other services are not influenced in a microkernel system.

According to the embodiment of the application, by configuring the read-write mode of the eMMC device and the pre-designed eMMC read-write scheduler, different read-write modes can be called to carry out read-write operation on the eMMC device according to read-write requests, the read-write speed can be greatly improved due to the adoption of the cache when the CPU cache read-write mode is called, the CPU does not need to be occupied when the DMA read-write mode is called, CPU resources are saved, and efficient read-write of the eMMC device is realized under the condition that resources are reserved for other services in the system.

Example two

Fig. 4 is a flowchart of a read-write method for an eMMC device according to a second embodiment of the present invention, where this embodiment is based on the foregoing embodiment, and after the read-write operation on the eMMC device is implemented in different read-write manners, the method further includes detecting a read-write operation result of the eMMC device, where the method includes:

step S201, configuring a read-write mode of the eMMC device and a pre-designed eMMC read-write scheduler.

Step S202, when the eMMC read-write scheduler obtains the eMMC read-write request, a CPU cache read-write mode or a DMA read-write mode is called to realize the read-write operation of the eMMC device.

In step S203, the read/write operation result of the eMMC device is detected.

Specifically, in this embodiment, after performing a read/write operation on the eMMC device in a different manner, the read/write operation result of the eMMC device is detected, for example, when it is determined that the performed operation is to write data into the eMMC device, the eMMC device is detected, and it is determined that the write operation result on the eMMC device is abnormal if it is found that data resources at each address in the eMMC device have not changed before and after the write operation is performed. The reason for the exception may be that a hardware structure DMA unit, a CPU, or a memory in the microkernel system may fail, or that information transmission is invalid due to network interrupt, or that a scheduler software configuration manner is incorrect. It is to be understood that this embodiment is merely an example, and the specific cause of the abnormality is not limited thereto.

When the read-write operation result is detected to determine the abnormal condition, an alarm can be given to prompt a user, so that the user is informed to overhaul hardware or software in time according to the alarm prompt, and the read-write efficiency and accuracy of the eMMC device are further improved.

According to the embodiment of the application, the read-write mode of the eMMC device and the designed eMMC read-write scheduler are configured, so that different read-write modes can be called to carry out read-write operation on the eMMC device according to read-write requests, the read-write speed can be greatly improved due to the adoption of the cache when the CPU cache read-write mode is called, the CPU does not need to be occupied when the DMA read-write mode is called, CPU resources are saved, and efficient read-write of the eMMC device is realized under the condition that resources are reserved for other services in the system. And the read-write operation result of the eMMC device is detected, and alarm prompt is carried out under the condition of abnormal starvation, so that a user can conveniently and timely overhaul, and the read-write efficiency and accuracy of the eMMC device are further improved.

EXAMPLE III

Fig. 5 is a schematic structural diagram of a read/write apparatus for an eMMC device according to a third embodiment of the present invention, and as shown in fig. 5, the apparatus includes: a configuration module 310 and an eMMC device read-write module 320.

The configuration module 310 is configured to configure a read-write mode of the eMMC device and a pre-designed eMMC read-write scheduler, where the read-write mode includes a CPU cache read-write mode and a DMA read-write mode;

the eMMC device read-write module 320 is configured to invoke a CPU cache read-write mode or a DMA read-write mode when acquiring an eMMC read-write request through the eMMC read-write scheduler, so as to implement a read-write operation on the eMMC device.

Optionally, the configuration module is configured to configure a drive of the eMMC device, and enable all memory operations of the eMMC program to a Cache;

and configuring the drive of the eMMC device, and mapping the memory address of the eMMC operation to the DMA.

Optionally, the pre-designed eMMC read-write scheduler includes: the system comprises an API module for providing a read-write interface for a user, a CPU mode read-write module for calling a CPU cache read-write mode and a DMA mode read-write module for calling a DMA read-write mode.

Optionally, the pre-designed eMMC read-write scheduler further includes: the eMMC resource isolation mutual exclusion module;

the configuration module is further used for calling a pre-configured read-write proportion configuration file when the eMMC read-write scheduler is configured, wherein the read-write proportion configuration file comprises a read-write mode matched with each address resource in the eMMC device;

and performing isolation and mutual exclusion operation on resources under each address in the eMMC device through the eMMC resource isolation and mutual exclusion module based on the read-write proportion configuration file.

Optionally, the eMMC device read-write module is configured to extract a read-write address of the eMMC device from the eMMC read-write request when the eMMC read-write request input by the user is received through the API module;

inquiring a read-write proportion configuration file according to the read-write address, and determining a read-write mode matched with resources under the read-write address;

and calling a CPU cache read-write mode or a DMA read-write mode according to the matched read-write mode.

Optionally, the apparatus further includes an instruction cache module, configured to determine a current instruction executed by the CPU in the memory;

and transferring the specified number of target instructions associated with the current instruction from the memory to the Cache.

The tower crane control device provided by the embodiment of the invention can execute the task selection method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example four

FIG. 6 illustrates a schematic structural diagram of an electronic device 10 that may be used to implement an embodiment of the present invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 6, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a Read Only Memory (ROM)12, a Random Access Memory (RAM)13, and the like, wherein the memory stores a computer program executable by the at least one processor, and the processor 11 can perform various suitable actions and processes according to the computer program stored in the Read Only Memory (ROM)12 or the computer program loaded from a storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data necessary for the operation of the electronic apparatus 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

A number of components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, or the like; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

Processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, or the like. The processor 11 performs the various methods and processes described above, such as read and write methods for eMMC devices.

In some embodiments, the task selection method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the task selection method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the read-write method of the eMMC device by any other suitable means (e.g., by way of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), Application Specific Standard Products (ASSPs), system on a chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be performed. A computer program can execute entirely on a machine, partly on a machine, as a stand-alone software package partly on a machine and partly on a remote machine or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. A computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user may provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the Internet.

The computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical host and VPS service are overcome.

It should be understood that various forms of the flows shown above, reordering, adding or deleting steps, may be used. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired results of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made, depending on design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for reading and writing an eMMC device, comprising:

configuring a read-write mode of an eMMC device and a pre-designed eMMC read-write scheduler, wherein the read-write mode comprises a CPU cache read-write mode and a DMA read-write mode;

2. The method of claim 1, wherein configuring read and write modes of the eMMC device comprises:

configuring a drive of the eMMC device, and enabling all memory operations of an eMMC program to be cached;

3. The method of claim 1, wherein the pre-designed eMMC read-write scheduler comprises: the system comprises an API module for providing a read-write interface for a user, a CPU mode read-write module for calling a CPU cache read-write mode and a DMA mode read-write module for calling a DMA read-write mode.

4. The method of claim 3, wherein configuring the eMMC read-write scheduler comprises:

the method comprises the steps that a CPU mode read-write interface and a DMA mode read-write interface for accessing an eMMC device are provided through driving of the eMMC device;

and performing read-write packaging on the CPU mode read-write interface through the CPU mode read-write module, and performing read-write packaging on the DMA mode read-write interface through the DMA mode read-write module.

5. The method of claim 3 or 4, wherein the pre-designed eMMC read-write scheduler further comprises: an eMMC resource isolation mutual exclusion module;

when the eMMC read-write scheduler is configured, a pre-configured read-write proportion configuration file is called, wherein the read-write proportion configuration file comprises read-write modes matched with each address resource in the eMMC device;

6. The method of claim 5, wherein invoking the CPU cache read-write mode or the DMA read-write mode when the eMMC read-write scheduler obtains the eMMC read-write request comprises:

when receiving an eMMC read-write request input by a user through the API module, extracting a read-write address of an eMMC device from the eMMC read-write request;

inquiring the read-write proportion configuration file according to the read-write address, and determining a read-write mode matched with the resource under the read-write address;

and calling the CPU cache read-write mode or the DMA read-write mode according to the matched read-write mode.

7. The method of claim 1, wherein configuring the drivers for the eMMC device after enabling Cache for all memory operations of an eMMC program further comprises:

determining a current instruction executed by a CPU in a memory;

and transferring a specified number of target instructions associated with the current instruction from the memory to the Cache.

8. A read-write apparatus for an eMMC device, comprising:

and the eMMC device read-write module is used for calling the CPU cache read-write mode or the DMA read-write mode when the eMMC read-write scheduler acquires an eMMC read-write request so as to realize the read-write operation of the eMMC device.

9. An electronic device, characterized in that the electronic device comprises:

at least one processor; and

the memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A computer-readable storage medium, having stored thereon computer instructions for causing a processor, when executed, to implement the method of any one of claims 1-7.