CN116560618A - Random computing circuit and method, chip and electronic equipment - Google Patents

Random computing circuit and method, chip and electronic equipment Download PDF

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Publication number
CN116560618A
CN116560618A CN202310537697.5A CN202310537697A CN116560618A CN 116560618 A CN116560618 A CN 116560618A CN 202310537697 A CN202310537697 A CN 202310537697A CN 116560618 A CN116560618 A CN 116560618A
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pulse
sub
control word
calculated
circuit
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魏祥野
修黎明
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Anxian Technology Suzhou Co ltd
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Anxian Technology Suzhou Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/586—Pseudo-random number generators using an integer algorithm, e.g. using linear congruential method
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A random computing circuit and method, a chip and an electronic device, including: the control sub-circuit is used for generating a first control word and a second control word according to the number to be calculated and inputting the first control word and the second control word into the pulse output sub-circuit; the pulse output sub-circuit is used for inputting the pulse to be calculated to the calculation sub-circuit according to the first control word, the second control word and the multipath reference pulses with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of each sub-pulse are controlled by a first control word; the probability of each high-level duration being present is controlled by a second control word; the calculation sub-circuit is used for executing logic operation on the pulse to be calculated.

Description

Random computing circuit and method, chip and electronic equipment
Technical Field
Embodiments of the present disclosure relate to, but not limited to, the field of circuit technologies, and in particular, to a random computing circuit, a random computing method, a random computing chip, and an electronic device.
Background
With the development of moore's law, the computational efficiency is continuously increasing. However, as the characteristic size of the transistor is smaller than 1nm and is close to the atomic diameter size of 0.1nm, problems such as quantum effect and the like will occur, the miniaturization path of the transistor will be physically limited, and the calculation efficiency and accuracy will be seriously affected.
Random computation is a new calculation paradigm, which encodes in a probabilistic manner, with natural advantages in fault tolerance and parallelism. In the current random calculation implementation method, taking a random number implementation method or a pseudo random number implementation method (such as a linear feedback shift register) as an example, only a denominator of 2 can be realized n A probability transition of a fixed denominator (n is greater than or equal to 0), such as 1/2, 5/8, 127/256, cannot achieve any score, such as 1/7, 3/13, etc., which would result in only a small fraction being achieved when performing random calculations, most of which cannot be achieved, which is a significant limitation for any practical application.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
Embodiments of the present disclosure provide a random computing circuit, comprising: a control sub-circuit, a pulse output sub-circuit, and a calculation sub-circuit, wherein:
The control sub-circuit is used for generating a first control word and a second control word according to a number to be calculated, inputting the first control word and the second control word into the pulse output sub-circuit, wherein the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
the pulse output sub-circuit is used for inputting a pulse to be calculated to the calculation sub-circuit according to the first control word, the second control word and the multipath reference pulses with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of the first sub-pulse and the second sub-pulse in the pulse to be calculated are controlled by the first control word; the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
The calculating sub-circuit is used for executing logic operation on the pulse to be calculated and outputting a calculation result.
Embodiments of the present disclosure also provide a chip including a random computing circuit according to any of the embodiments of the present disclosure.
The embodiment of the disclosure also provides electronic equipment, which comprises the chip according to any embodiment of the disclosure.
The embodiment of the disclosure also provides a random calculation method, which is used for the random calculation circuit according to any embodiment of the disclosure, and comprises the following steps:
generating a first control word and a second control word according to a number to be calculated through the control sub-circuit, and inputting the first control word and the second control word into the pulse output sub-circuit, wherein the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
inputting a pulse to be calculated to the calculation sub-circuit through the pulse output sub-circuit according to the first control word, the second control word and a plurality of paths of reference pulses with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of the first sub-pulse and the second sub-pulse in the pulse to be calculated are controlled by the first control word; the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
And executing logic operation on the pulse to be calculated through the calculating sub-circuit, and outputting a calculation result.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the embodiments of the disclosure. The shapes and sizes of various components in the drawings are not to scale true, and are intended to be illustrative of the present disclosure.
FIG. 1 is a schematic diagram of a random computing circuit architecture provided in an exemplary embodiment of the present disclosure;
FIG. 2 is a waveform diagram of multiple reference pulses provided by a signal source provided in an exemplary embodiment of the present disclosure;
fig. 3 is a schematic diagram of a generation principle of a pulse to be calculated according to an exemplary embodiment of the present disclosure;
FIG. 4 is a waveform schematic diagram of several pulses to be calculated provided by exemplary embodiments of the present disclosure;
fig. 5 is a schematic diagram of a pulse output sub-circuit according to an exemplary embodiment of the present disclosure;
FIG. 6 is a schematic diagram of an architecture of another random computing circuit provided by an exemplary embodiment of the present disclosure;
FIG. 7 is a schematic diagram of an architecture of yet another random computing circuit provided by an exemplary embodiment of the present disclosure;
FIG. 8 is a schematic diagram of an architecture of yet another random computing circuit provided by an exemplary embodiment of the present disclosure;
fig. 9 is a flowchart of a random calculation method according to an exemplary embodiment of the present disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.
Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, is intended to mean that elements or items preceding the word encompass the elements or items listed thereafter and equivalents thereof without precluding other elements or items.
In the conventional random calculation process, fractional time-series waveform conversion mainly uses a comparison conversion method of a random number generator or a pseudo random number generator, which converts by binary number comparison, and thus, the final denominator of the converted numbers is 2 n (n is greater than or equal to 0), this results in only a small fraction being realized when performing random calculations, a large fraction being not realized, and a large limitation.
As shown in fig. 1, an embodiment of the present disclosure provides a random calculation circuit including: a control sub-circuit 01, a pulse output sub-circuit 02 and a calculation sub-circuit 03, the pulse output sub-circuit 02 being electrically connected to the control sub-circuit 01 and the calculation sub-circuit 03, respectively, wherein:
a control sub-circuit 01, configured to generate a first control word and a second control word according to a number to be calculated, and input the first control word and the second control word into a pulse output sub-circuit 02, where the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
a pulse output sub-circuit 02 for inputting a pulse to be calculated to the calculation sub-circuit 03 according to the first control word, the second control word and the multi-path reference pulse with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of each sub-pulse in the pulse to be calculated are controlled by a first control word; the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
The calculation sub-circuit 03 is configured to perform a logic operation on the pulse to be calculated and output a calculation result.
According to the random calculation circuit provided by the embodiment of the disclosure, a first control word and a second control word are generated according to a number to be calculated through a control sub-circuit 01, a pulse to be calculated is input to a calculation sub-circuit 03 through a pulse output sub-circuit 02 according to the first control word, the second control word and multi-channel reference pulses with uniform phase intervals, the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are distributed on a time domain, the total high-low level duration of each sub-pulse is fixed, the high-level duration of each sub-pulse comprises at least one of a first high-level duration and a second high-level duration, and the total high-low level duration of each sub-pulse and the occurrence probability of each sub-pulse in the pulse to be calculated are controlled by the first control word; each high-level duration and the occurrence probability of each high-level duration in the pulse to be calculated are controlled by the second control word, and the time sequence waveform conversion and random calculation of the fraction between any 0 and 1 can be realized. In addition, the random computing circuit provided by the embodiment of the disclosure has the dual characteristics of analog and digital computation, and the computing result is completely consistent with the theoretical value without deviation. The random computing circuit provided by the embodiment of the disclosure can be integrated in various chips as digital IP, and the method has the characteristics of low cost, high efficiency, portability and the like.
In some example embodiments, the first control word includes: a first integer part and a first fractional part, the second control word comprising: a second integer portion and a second fractional portion;
the total high-low level duration of the first sub-pulse and the second sub-pulse is controlled by a first integer part, the probability of the first sub-pulse and the second sub-pulse occurring in the pulse to be calculated is controlled by a first fractional part, the first high-level duration and the second high-level duration are controlled by a second integer part, and the probability of the first high-level duration and the second high-level duration occurring in the pulse to be calculated is controlled by a second fractional part.
In the disclosed embodiment, the first control word and the second control word are each a number, and the first control word and the second control word have an integer portion and a fractional portion, respectively. For example, if the first control word is 2.5, the first integer part is 2 and the first fractional part is 0.5; if the second control word is 1.125, the second integer part is 1 and the second fractional part is 0.125. When the first control word or the second control word is an integer, the first fractional part of the first control word or the second fractional part of the second control word is 0.
In the embodiment of the present disclosure, the multiple reference pulses with uniformly-spaced phases may be pulses provided by a signal generator, where the signal generator may be located outside the pulse output sub-circuit 02, and of course, the signal generator may also belong to the pulse output sub-circuit 02, and the embodiment of the present disclosure will be described below by taking the signal generator belongs to the pulse output sub-circuit 02 as an example.
Fig. 2 is a waveform diagram of multiple reference pulses provided by the signal generator, where in fig. 2, the multiple reference pulses include K reference pulses, where K is an integer greater than 1. Referring to fig. 2, the waveforms of the multiple reference pulses are identical (i.e., the periods and amplitudes are identical). The waveforms of the reference pulses are uniformly distributed, the intervals of the reference pulses in the time domain are the same, the phase difference delta of any two adjacent reference pulses in the reference pulses is equal, and the frequencies of the reference pulses are f, K.delta=1/f.
In some exemplary embodiments, the control sub-circuit 01 generates a first control word and a second control word according to the number to be calculated, comprising:
dividing the number to be calculated into a first numerator part A and a first denominator part B;
scaling up or down the first numerator portion A and the first denominator portion B to obtain a second numerator portion A ′ And a second denominator part B ′ So that the second denominator part B ′ Between 1 and K;
by combining the second molecular moiety A ′ As a second control word and outputs a second denominator part B ′ As a first control word output.
In some exemplary embodiments, the first numerator portion a and the first denominator portion B are scaled up or down by a factor of 2 k K is greater than or equal to 1.
For example, the reciprocal of pi is the number to be calculatedFor example, due to->Thus, the first numerator portion a may be set to 113 (binary form 001110001B) and the first denominator portion B may be set to 355 (binary form 101100011B). Assuming that the number of paths K of the multi-path reference pulse generated by the signal generator is 64, the first numerator portion A and the first denominator portion B can be reduced by 8 times, i.e. the second numerator portion A ′ Set to 14.125 (binary form 001110.001B), the second denominator part B ′ Set to 44.375 (binary form 101100.011 b), i.e. +.>Is rewritten as->The first control word is 44.375 and the second control word is 14.125.
As another example, take the figure to be calculated as golden section ratio coefficient 0.618, due toThus, the first molecular moiety a can be set to 309 (binaryIn 100110101B) and the first denominator part B is set to 500 (binary form 111110100B). Assuming that the number of paths K of the multi-path reference pulse generated by the signal generator is 64, the first numerator portion A and the first denominator portion B can be reduced by 8 times, i.e. the second numerator portion A ′ Set to 38.625 (binary form 100110.101B), the second denominator part B ′ Set to 62.5 (binary form 111110.100 b), i.e. +.>Is rewritten as->The first control word is 62.5 and the second control word is 38.625.
In some exemplary embodiments, the total duration of the high and low levels of the pulse to be calculated is T FD ＝(q-p)·T A +p·T B The high level duration of the pulse to be calculated is T HD ＝(q-s)·T HS +s·T HL Wherein the first control word f=i+r, I is a first integer part, r is a first fractional part, the second control word d=ζ+h, ζ is a second integer part, h is a second fractional part, h=s/q, r=p/q, s, p and q are integers, T A Representing the total duration of the high and low levels of the first sub-pulse, T A ＝I·Δ，T B Representing the total duration of the high and low levels of the second sub-pulse, T B ＝(I+1)·Δ，T HS Representing a first high level duration, T HS ＝ζ·Δ，T HL Representing the second high level duration, T HL = (ζ+1) ·Δ, Δ representing the phase difference between any two adjacent reference pulses in the plurality of reference pulses.
In the disclosed embodiment, the first control word F includes a first integer part I and a first fractional part r, i.e., f=i+r, and the second control word D includes a second integer part ζ and a second fractional part h, i.e., d=ζ+h.
For example, the reciprocal of pi is calculated by the number to be calculatedFor example, f=44.375, i=44, >D＝14.125，ζ＝14，/>p＝3，q＝8，s＝1，T A ＝44Δ，T B ＝45Δ，T HS ＝14Δ，T HL The total duration of the high and low levels of the output sub-pulses may be 44 Δ,45 Δ,44 Δ,45 Δ,44 Δ,45 Δ,44 Δ,44 Δ (the order of the output sub-pulses is adjustable, and the present disclosure is not limited to the order of the output sub-pulses). Wherein the probability of 44 delta (i.e. the first sub-pulse) for the total duration of high and low levels is 5/8 and the probability of 45 delta (i.e. the second sub-pulse) for the total duration of high and low levels is 3/8. The high duration of each sub-pulse may be 14Δ,15Δ,14Δ (the order in which the high durations are output may be adjustable), and the present disclosure is not limited in the order in which the high durations are output). Wherein the high level duration is 14Δ (i.e., the first high level duration T HS ) The probability of (2) is 7/8, the high level duration is 45 delta (i.e. the second high level duration T HL ) The probability of (1/8), the total duty cycle of the high-level duration is (14×7+15×1)/(44×5+45×3) =113/355.
As another example, using the number to be calculated as golden ratio coefficient 0.618, f=62.5, i=62,
D＝38.625，ζ＝38，/>p＝4，q＝8，s＝5，T A ＝62Δ，T B ＝63Δ，
T HS ＝38Δ，T HL the total duration of the high and low levels of the output sub-pulses may be 62 Δ,63 Δ,62 Δ,63 Δ,62 Δ,63 Δ,62 Δ,63 Δ (the order of the output sub-pulses is adjustable), and the present disclosure is not limited to the order of the output sub-pulses). Wherein the total duration of the high level and the low level is 62 The probability of delta (i.e., the first sub-pulse) is 4/8 and the probability of 63 delta (i.e., the second sub-pulse) for the total duration of the high and low levels is 4/8. The high duration of each sub-pulse may be 38Δ,39Δ,38Δ,39Δ (the order in which the high durations are output may be adjustable), and the present disclosure is not limited in the order in which the high durations are output). Wherein the high level duration is 38Δ (i.e., the first high level duration T HS ) The probability of (2) is 3/8, the high-level duration is 39Δ (i.e., the second high-level duration T HL ) The probability of (2) is 5/8, and the total duty cycle of the high level duration is (38×3+39×5)/(62×4+63×4) =309/500.
In the embodiment of the disclosure, the duty ratio of the pulse to be calculated is used for representing the number to be calculated, the number to be calculated is the number to be involved in calculation, the number to be calculated is between 0 and 1, and the random calculation circuit provided by the embodiment of the disclosure is used for carrying out logic calculation on the number between 0 and 1. For example, if the number to be calculated is 0.5, the duty ratio of the pulse to be calculated output by the pulse output sub-circuit 02 is 1/2, that is, the duty ratio of the duration of the high level in the pulse to be calculated is 1/2, and the pulse to be calculated may be 11110000.
In the embodiment of the disclosure, the total duration of the high level and the low level of the first sub-pulse and the second sub-pulse in the pulse to be calculated is controlled by a first integer part, and the probability of the first sub-pulse and the second sub-pulse in the pulse to be calculated is controlled by a first decimal part. For example, assume that the total duration of the high and low levels of the first sub-pulse is denoted as T A The total duration of the high and low levels of the second sub-pulse is denoted as T B The first integer part of the first control word is denoted as I, then T A ＝I·Δ，T B = (i+1) ·Δ. Of course T A And T B Other representations are possible, e.g., T B = (i+2) ×Δ, etc., embodiments of the present disclosure are described as T A ＝I·Δ，T B = (i+1) ·Δ is an example. If the first fractional part of the first control word is denoted as r, the ratio of the probability of occurrence of the first sub-pulse and the second sub-pulse in the pulse to be calculated is (q-p)/p, p/q=r, at which time the total duration T of the high and low levels of the pulse to be calculated FD ＝(q-p)·T A +p·T B 。
In the embodiment of the disclosure, each sub-pulse in the pulse to be calculated may have two high-level durations: the first high-level duration and the second high-level duration, the magnitudes of which are controlled by the second integer part, and the probability of occurrence of the first high-level duration and the second high-level duration in the pulse to be calculated is controlled by the second fractional part. For example, assume that the first high-level duration is denoted as T HS The second high level duration is denoted as T HL The second integer part of the second control word is denoted ζ, then T HS ＝ζ·Δ，T HL = (ζ+1) ·Δ. Of course T HS And T HL Other representations are possible, e.g., T HL = (ζ+2) ·Δ, etc., embodiments of the present disclosure are described in T HS ＝ζ·Δ，T HL = (ζ+1) ·Δ is an example. If the second fractional part of the second control word is denoted as h, then the ratio of the probability of occurrence of the first high-level duration and the second high-level duration in the pulse to be calculated is (q-s)/s, s/q=h, at which time the high-level duration T in the pulse to be calculated HD ＝(q-s)·T HS +s·T HL 。
In some exemplary embodiments, q may be a least common multiple of the denominator in the shortest score corresponding to the first fractional part r and the denominator in the shortest score corresponding to the second fractional part h. For example, whenWhen q may be the least common multiple 15 of 5 and 3, i.e., q=15, p= 9,s =10. In other exemplary embodiments, q may be other than the least common multiple of the denominator in the shortest score corresponding to the first fractional part r and the denominator in the shortest score corresponding to the second fractional part h, for example, when->When q may be 30, p may be 18, and s may be 20.
As shown in fig. 3, T B Compared with T A Larger, represented as T in FIG. 3 B Length ratio T of (2) A Long. When the first decimal of the first control wordWhen the part is 0.5, the probability of occurrence of the first sub-pulse and the second sub-pulse in the pulse to be calculated is equal, T A And T B The probability of occurrence is equal, see the pulse to be calculated shown in FIG. 3, where T A And T B Alternating with each other. When the first decimal part is smaller than 0.5, the probability of occurrence of the first sub-pulse in the pulse to be calculated is larger than that of the second sub-pulse, T A Probability of occurrence is greater than T B Probability of occurrence. When the first decimal part is greater than 0.5, the probability of occurrence of the first sub-pulse in the pulse to be calculated is smaller than the probability of occurrence of the second sub-pulse, T B Probability of occurrence is greater than T A Probability of occurrence. When the first control word is an integer, the first fractional part of the first control word is 0, and the pulse signal includes only the first sub-pulse and does not include the second sub-pulse.
In embodiments of the present disclosure, T HL Length ratio T of (2) HS Is longer (not shown in fig. 3). When the second decimal part of the second control word is 0.5, the probability of the first high level duration and the second high level duration appearing in the pulse to be calculated is equal, T HL And T HS The probability of occurrence is equal. When the second fraction is less than 0.5, the first high level duration T in the pulse is calculated HS The probability of occurrence is greater than the second high level duration T HL Probability of occurrence. When the second fractional part is greater than 0.5, the first high level duration T in the pulse to be calculated HS The probability of occurrence is smaller than the second high level duration T HL Probability of occurrence. When the second control word is an integer, the second fractional part of the second control word is 0, and the pulse signal only includes the first high-level duration and does not include the second high-level duration.
In the embodiment of the present disclosure, the inputs of the pulse output subcircuit 02 include: the pulse array with the delta time intervals of K, a first control word F and a second control word D are used for controlling the total time of the high level and the low level of the output pulse and the time of the high level through the first control word F and the second control word D, wherein the first control word F mainly controls the total time of the high level and the low level of the output pulse, and the second control word D mainly controls the time of the high level of the output pulse. When the output period operates at a time-averaged frequency (including a plurality of different periods), the pulse output subcircuit 02 satisfies the following condition:
T A ＝I·Δ,T B ＝(I+1)·Δ(1)
T HS ＝ζ·Δ,T HL ＝(ζ+1)·Δ,ζ∈[1,(I-2)](3)
T H ＝(1-h)·T HS +h·T HL ＝ζ·Δ+h·Δ＝D·Δ(4)
T A and T B Is the total time length of the high level and the low level of the two sub-pulses output by the pulse output sub-circuit 02, T B Ratio T A A delta longer, T as described in equation (1) A And T B The probability of occurrence is controlled by a first control word F, where f=i+r, I is an integer, r is a fraction, r is T B Probability of occurrence, 1-r is T A The probability of occurrence is as described in equation (2). For example, when f=3.25, the total duration of the high and low levels of the output sub-pulse may be 3,3,3,4,3,3,3,4, where the probability of the total duration of the high and low levels being 3 is 3/4 and the probability of the total duration of the high and low levels being 4 is 1/4. In addition to the total duration of the high and low levels of the output pulse, the duration of the high level of each sub-pulse may also be controlled. T (T) HS And T HL Is the two high-level durations of each sub-pulse, T HL Ratio T HS One delta longer as described in equation (3). Also, the lengths of the two high-level durations are controlled by the second control word D, as described in equation (4). Where d=ζ+h, ζ is an integer, and h is a decimal. h is T HL The occurrence probability is 1-h is T HS The probability of occurrence. For example, when d=1.75, the high duration of the output sub-pulse may be 1,2,2,2,1,2,2,2, where the probability of a high duration of 1 is 1/4 and the high duration isThe probability of 2 is 3/4.
In the embodiment of the disclosure, the first control word F and the second control word D may have different combinations to control the output, and are respectively as follows:
(1) The first control word F is an integer and the second control word D is an integer: the pulse to be calculated output by the pulse output sub-circuit 02 operates in a pulse width modulation (Pulse Width Modulation, PWM) mode. If d=3, f=7, the waveform can be analogically 11100001110000 after being digitized, wherein the high-level duration has a duty ratio of 3/7.
(2) The first control word F is an integer and the second control word D contains a fraction: the pulse to be calculated output by the pulse output sub-circuit 02 works in a variable PWM mode, such as d=3.5, f=7, and the waveform after being digitized can be analogically 11100001111000, wherein the duty ratio of the high level duration is 7/14.
(3) The first control word F contains a decimal, and the second control word D is an integer: the pulse to be calculated output from the pulse output sub-circuit 02 operates in a Time Average Frequency (TAF) mode, such as d=3, f=7.5, and the waveform is 111000011100000 after being digitized, wherein the duty ratio of the high level duration is 6/15.
(4) The first control word F contains a fraction and the second control word D contains a fraction: the pulse to be calculated output by the pulse output sub-circuit 02 works in a PWM-TAF mode, for example, d=3.5, f=7.5, and the waveform is 111000011110000 after being digitized, wherein the duty ratio of the high level duration is 7/15.
The above cases can be summarized by the formula (5), wherein the duty ratio of the high level duration is timeCan be reduced to +.>Since h and r are decimal, it is written as integer divided form, i.e. +.>Where h=s/q and r=p/q. Embodiments of the present disclosure may be implemented by converting different numbers to be calculatedFor different first control words F and second control words D, e.g. d=3.5, f=7; d=2.75, f=15.5, etc., thereby converting any number to be calculated into a probability waveform. Fig. 4 shows a waveform schematic of several pulses to be calculated provided by exemplary embodiments of the present disclosure.
In the embodiment of the disclosure, the calculating sub-circuit 03 is configured to perform logic calculation according to the duty ratio of the pulse to be calculated, and output a calculation result of the logic calculation. The pulse output sub-circuit 02 inputs the pulse to be calculated to the calculating sub-circuit 03, and the calculating sub-circuit 03 can perform logic calculation according to the duty ratio of the pulse to be calculated (representing the number to be calculated), which is equivalent to performing logic calculation according to the number to be calculated. For example, the duty cycle of the pulse to be calculated is 1/2, and the calculation sub-circuit 03 can perform logic calculation based on 1/2. The logical computation herein may be any logical computation, for example, the logical computation includes at least one of addition, subtraction, multiplication, division, evolution, squaring, and the like. When the logic computation includes addition, the computation sub-circuit 03 includes or gates, or a data selector (MUX), or the like.
In summary, in the random calculation circuit provided in the embodiments of the present disclosure, the pulse output sub-circuit 02 can output the pulse to be calculated, and the calculation sub-circuit 03 can perform logic calculation according to the duty ratio of the pulse to be calculated. When a bit in the pulse to be calculated is wrong, the duty ratio of the pulse to be calculated does not change greatly, and further the result of logic calculation does not change greatly, so that the accuracy of the calculation result output by the calculation sub-circuit 03 is high.
And, the control sub-circuit 01 may control the duty ratio of the pulse to be calculated, the total duration of the high and low levels of each sub-pulse, the probability of occurrence of the sub-pulse, the duration of the high level of each sub-pulse, and the like, which are outputted by the pulse output sub-circuit 02, by the first control word and the second control word. Therefore, accurate control of the pulse to be calculated can be achieved. In the embodiment of the disclosure, since the number to be calculated represented by the pulse to be calculated can cover the whole interval from 0 to 1, the application range of the random calculation circuit is wider.
The pulse output sub-circuit 02 according to the embodiment of the present disclosure has various structures, and will be explained below by taking the structure shown in fig. 5 as an example. Referring to fig. 5, the pulse output unit 02 includes: the first processing unit 21, the second processing unit 22, the output unit 23 and the signal generator 24 are all connected with the second processing unit 22.
The signal generator 24 is configured to output a plurality of reference pulses with uniformly-spaced phases to the second processing unit 22;
the first processing unit 21 is configured to output a first control signal and a second control signal to the second processing unit 22 according to the first control word and the second control word, respectively;
the second processing unit 22 is configured to select an I-th reference pulse from multiple paths of reference pulses (e.g., K-th reference pulse, K > 1) according to the first control signal, select a J-th reference pulse from multiple paths of reference pulses according to the second control signal, and select one path of reference pulse from the I-th reference pulse and the J-th reference pulse as an output pulse, where 1 is less than or equal to I, and 1 is less than or equal to J;
the output unit 23 is configured to output a pulse to be calculated according to the output pulse of the second processing unit 22.
The operation of the first processing unit 21, the second processing unit 22, the output unit 23 and the signal generator 24 will be described with reference to fig. 5:
the first processing unit 21 includes a first logic controller 211 and a second logic controller 212.
Referring to fig. 5, the first logic controller 211 includes a first adder 2111, a first register 2112, and a second register 2113, and the first register 2112 is connected to the first adder 2111 and the second register 2113, respectively. The first logic controller 211 is operative to generate a first control signal according to the first control word F.
A first logic controller 211 for adding all bits stored in the first register 2112 and the frequency control word F by the first adder 2111 under the effect of the enable signal, and saving the addition result in the first register 2112 at the rising edge of the second clock frequency CLK 2; on the next rising edge of the second clock frequency CLK2, the most significant bit stored in the first register 2112 is stored in the second register 2113 as a selection signal of the first k→1 multiplexer 221, that is, the aforementioned first control signal for selecting the I-th reference pulse output from the K-way phase uniformly spaced reference pulses.
When adding the control word F and the most significant bit stored in the first register 2112, assuming that the value in the first register 2112 is less than 1, if the decimal part of the addition result is carried, the most significant bit stored in the second register 2113 is i+1; if no carry occurs during the addition, the most significant bit stored in the second register 2113 is I. When I+1 is in the second register 2113, the total duration of the high and low levels of the sub-pulses correspondingly output by the pulse output sub-circuit 02 is T B When the second register 2113 is I, the pulse output sub-circuit 02 outputs a sub-pulse having a total duration of high and low levels of T A The output T can be seen as =I.delta A Or T B The smaller the fractional part of the first control word is, the less likely the carry is to occur, the output T is related to the fractional part size of the first control word A The greater the probability of outputting TB, and vice versa.
Here, the first register 2112 may include a first portion storing an integer and a second portion storing a decimal. When adding, the integer part of the first control word F and the content in the first part are added, and the fractional part of the first control word F and the content in the second part are added. The addition is binary addition, and is performed by the first adder 2111.
The second logic controller 212 includes a second adder 2121, a third register 2122, and a fourth register 2123. The third register 2122 is connected to the second adder 2121 and the fourth register 2123, respectively. The second logic controller 212 is operative to generate a second control signal based on the second control word D.
The second logic controller 212 is configured to add the second control word D and the most significant bit (in the embodiment of the present disclosure, the most significant bit refers to an integer part of a numerical value) stored in the first register 2112 by the second adder 2121 under the effect of the enable signal, and save the addition result in the third register 2122 at the rising edge of the second clock frequency CLK 2. After the addition result is saved in the third register 2122, at the rising edge of the first clock frequency CLK1, the information stored in the third register 2122 is stored in the fourth register 2123 and used as a selection signal of the second k→1 multiplexer 222, that is, the aforementioned second control signal for selecting the J-th reference pulse output from the K-th reference pulses. The second clock frequency CLK2 is opposite to the first clock frequency CLK1, for example, the second clock frequency CLK2 may be a signal of the first clock frequency CLK1 after being subjected to the not gate.
Here, the third register 2122 may include a first portion storing an integer and a second portion storing a decimal. When adding, the integer part of the second control word D and the content in the first part are added, and the fractional part of the second control word D and the content in the second part are added. The addition is binary addition, and is performed by a second adder 2121.
It should be noted that, in the embodiment of the present disclosure, the input of the second adder 2121 includes the second control word D, and optionally, the input of the second adder 2121 may also include other parameters for controlling the high level duration, which is not limited in the embodiment of the present disclosure.
Referring to fig. 5, the second processing unit 22 includes a first k→1 multiplexer 221, a second k→1 multiplexer 222, and a 2→1 multiplexer 223. The first k→1 multiplexer 221 and the second k→1 multiplexer 222 respectively include a plurality of inputs, a control input, and an output. The 2-to-1 multiplexer 223 includes a control input, an output, a first input, and a second input. The output of the first K.fwdarw.1 multiplexer 221 is connected to a first input of the 2.fwdarw.1 multiplexer 223, and the output of the second K.fwdarw.1 multiplexer 222 is connected to a second input of the 2.fwdarw.1 multiplexer 223; the plurality of input terminals of the first K- > 1 multiplexer 221 and the plurality of input terminals of the second K- > 1 multiplexer 222 are connected to the signal generator 24; the control input of the first k→1 multiplexer 221 is connected to the second register 2113, and the control input of the second k→1 multiplexer 222 is connected to the fourth register 2123.
The control input terminal of the first k→1 multiplexer 221 selects the I-th reference pulse output from the K paths of reference pulses with uniformly-spaced phases under the control of the first control signal generated by the first logic controller 211; the control input of the second K→1 multiplexer 222 selects the J-th reference pulse output from the K-way uniformly phase-spaced reference pulses under the control of the second control signal generated by the second logic controller 212.
Taking the first k→1 multiplexer 221 as an example, when selecting the reference pulse, the reference pulse output of the 3 rd reference pulse in the K reference pulses with uniformly spaced phases may be selected according to the value stored in the second register 2113, that is, the value of the first control signal, for example, the value stored in the second register 2113 is 3.
The 2→1 multiplexer 223 may select one of the I-th reference pulse from the output of the first k→1 multiplexer 221 and the J-th reference pulse from the output of the second k→1 multiplexer 222 as the output of the 2→1 multiplexer 223 at the rising edge of the first clock frequency CLK 1. For example, the I-th reference pulse is selected beginning at the first rising edge until the second rising edge, the J-th reference pulse is selected beginning at the second rising edge until the third rising edge, and so on.
Since the 2-1 multiplexer 223 is selected from the outputs of the two K-1 multiplexers, the outputs of the two K-1 multiplexers are combined to form a new period, since the first pulse signal and the second pulse signal of the outputs of the two K-1 multiplexers differ by an integer number of delta, and there are two cases of I delta and I+1 delta, so that T exists in the pulse to be calculated output by the final pulse output sub-circuit 02 A And T B Two different high and low levels total duration.
Referring to fig. 5, the output unit 23 includes a trigger circuit. The trigger circuit is used for generating a pulse to be calculated. The trigger circuit includes a D flip-flop 231. The D flip-flop 231 includes a data input, a clock input, an output, and an inverting output. The clock input terminal of the D flip-flop 231 is connected to the 2→1 multiplexer 223, and the data input terminal of the D flip-flop 231 is connected to the inverting output terminal of the D flip-flop 231, and the output terminal or inverting output terminal of the D flip-flop 231 can be used as the output terminal of the pulse output sub-circuit 02, i.e. the end generating the pulse to be calculated, so that the pulse to be calculated outputted by the pulse output sub-circuit 02 is the first clock frequency CLK1 or the second clock frequency CLK2 in fig. 5.
The clock input terminal of the D flip-flop 231 receives the output from the output terminal of the 2→1 multiplexer 223, and outputs the first clock frequency CLK1 through the output terminal, outputs the second clock frequency CLK2 through the inverted output terminal, and outputs the second clock frequency CLK2 to the data input terminal of the D flip-flop 231.
The pulse output subcircuit 02 provided by embodiments of the present disclosure may be referred to as a variable probability random number generator, such as a variable probability random number generator based on a Time-Average frequency pulse-direct-composition (TAF-DPS) circuit.
In the embodiment of the disclosure, the phase difference delta of any two adjacent reference pulses in the multiple reference pulses can be adjusted, and when delta is larger, the power consumption of the random calculation circuit is lower. When Δ is smaller, the random calculation circuit has higher calculation efficiency and higher performance.
Further, in the above embodiment, taking the random calculation circuit including one pulse output sub-circuit 02 as an example, alternatively, the random calculation circuit provided in the embodiment of the disclosure may also include a plurality of pulse output sub-circuits 02; at this time, the control sub-circuit 01 is configured to input a first control word and a second control word corresponding to the pulse output sub-circuit 02 to each of the pulse output sub-circuits 02. The first control word and the second control word corresponding to different pulse output subcircuits 02 may be the same or different, which is not limited by the embodiments of the present disclosure.
Illustratively, the output sub-circuit 02 includes: the first pulse output sub-circuit 02A and the second pulse output sub-circuit 02B are exemplified. As shown in fig. 6, the first pulse output sub-circuit 02A and the second pulse output sub-circuit 02B are each connected to the control sub-circuit 01 and to the calculation sub-circuit 03. The control sub-circuit 01 is used for respectively inputting corresponding first control words and second control words to the two pulse output sub-circuits, the first pulse output sub-circuit 02A is used for inputting a first pulse to be calculated to the calculation sub-circuit 03, and the second pulse output sub-circuit 02B is used for inputting a second pulse to be calculated to the calculation sub-circuit 03. The duty ratio of the first to-be-calculated pulse represents a first to-be-calculated number, the duty ratio of the second to-be-calculated pulse represents a second to-be-calculated number, and the first to-be-calculated number and the second to-be-calculated number are both between 0 and 1. The calculating sub-circuit 03 may perform logic calculation on the first number to be calculated and the second number to be calculated, for example, in fig. 6, taking the example that the logic calculation includes multiplication, where the calculating sub-circuit 03 is an and logic gate, and the and logic gate may multiply the first number to be calculated and the second number to be calculated when performing logic calculation on the first number to be calculated and the second number to be calculated.
Further, as shown in fig. 7, the random computing circuit provided in the embodiment of the disclosure may further include: the sampling sub-circuit 04 and the clock sub-circuit 05, the calculation sub-circuit 03 and the clock sub-circuit 05 are connected to the sampling sub-circuit 04, for example, the calculation sub-circuit 03 is connected to an input terminal of the sampling sub-circuit 04, and the sampling sub-circuit 04 is also connected to the control sub-circuit 01 (the connection relationship is not shown in fig. 7). The control sub-circuit 01 is also used to input a target sequence length to the sampling sub-circuit 04 and the clock sub-circuit 05 is used to provide a clock signal to the sampling sub-circuit 04. The sampling sub-circuit 04 is configured to sample the calculation result output by the calculating sub-circuit 03 according to the clock signal and the target sequence length, obtain a result sequence of the target sequence length, and output an indication signal of a duty ratio of the result sequence (e.g., output the indication signal from the Q terminal). The indication signal may be, for example, all 1 s (high) and/or all 0 s (low) in the resulting sequence.
Fig. 7 is an example in which the random calculation circuit further includes the sampling sub-circuit 04 and the clock sub-circuit 05 on the basis of fig. 1, and when the random calculation circuit further includes the sampling sub-circuit 04 and the clock sub-circuit 05 on the basis of fig. 6, the random calculation circuit may be as shown in fig. 8.
Random computation is a computational paradigm proposed by von neumann, the most important feature of which is that the number is represented by a bit stream that can be handled by very simple circuitry, and the number itself is interpreted as a probability, i.e. the probability that each bit in the string is 1. Whereas the probability can be estimated in terms of frequency, according to bernoulli's law of large numbers, i.e. the probability of 1 per bit can be expressed in terms of the number of 1's in the stream of bits. For example: 1000 may represent 1/4 and 1100 may represent 1/2. In the embodiment of the disclosure, the pulse to be calculated (a string of bit streams) output by the pulse output sub-circuit may represent the number to be calculated, and then the calculation sub-circuit 03 performs random calculation according to the pulse to be calculated. The random computing circuit has the dual characteristics of analog (duty cycle) and digital (logic value). In addition, the random computing circuit is a digital circuit, is easy to integrate and transplant, and can reduce the research and development cost.
In addition, the random computing circuit can belong to a processor, and the random computing circuit does not need to access the memory in the computing process, so that the computing efficiency of the random computing circuit is not affected by the bandwidth of the memory.
In summary, in the random computation circuit provided in the embodiments of the present disclosure, the pulse output sub-circuit may output the pulse to be computed, and the computation sub-circuit may perform logic computation according to the duty ratio of the pulse to be computed. When a bit in the pulse to be calculated is wrong, the duty ratio of the pulse to be calculated does not change greatly, and further the result of logic calculation does not change greatly, so that the accuracy of the calculation result output by the calculation sub-circuit is higher. In addition, the calculation result of the random calculation circuit provided by the embodiment of the disclosure is completely consistent with the theoretical calculation result, and no calculation deviation exists.
The embodiment of the disclosure provides a random calculation method, which can be used for any random calculation circuit provided by the embodiment of the disclosure. As shown in fig. 9, the method includes:
step 901, generating a first control word and a second control word according to a number to be calculated through the control sub-circuit, and inputting the first control word and the second control word into the pulse output sub-circuit, wherein the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
Step 902, inputting, by the pulse output sub-circuit, a pulse to be calculated to the calculation sub-circuit according to the first control word, the second control word and a plurality of paths of reference pulses with uniformly-spaced phases, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of each sub-pulse in the pulse to be calculated are controlled by the first control word; the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
and 903, performing logic operation on the pulse to be calculated by the calculation sub-circuit, and outputting a calculation result.
In some exemplary embodiments, the number of paths of the multi-path reference pulse is K, where K is an integer greater than 1, and generating a first control word and a second control word according to the number to be calculated includes:
dividing the number to be calculated into a first numerator part A and a first denominator part B;
Scaling up or down the first numerator portion A and the first denominator portion B to obtain a second numerator portion A ′ And a second denominator part B ′ So that the second denominator part B ′ Between 1 and K;
subjecting the second molecular moiety A ′ As the second control word and outputs the second denominator part B ′ As the first control word output.
In some exemplary embodiments, the first numerator portion a and the first denominator portion B are scaled up or down by a factor of 2 k K is greater than or equal to 1.
In some exemplary embodiments, the first control word includes: a first integer part and a first fractional part, the second control word comprising: a second integer portion and a second fractional portion;
the total high-low level duration of the first sub-pulse and the second sub-pulse is controlled by the first integer part, the probability of occurrence of the first sub-pulse and the second sub-pulse in the pulse to be calculated is controlled by the first decimal part, the first high-level duration and the second high-level duration are controlled by the second integer part, and the probability of occurrence of the first high-level duration and the second high-level duration in the pulse to be calculated is controlled by the second decimal part.
In some exemplary embodiments, the total duration of the high and low levels of the pulse to be calculated is T FD ＝(q-p)·T A +p·T B The high level duration of the pulse to be calculated is T HD ＝(q-s)·T HS +s·T HL Wherein the first control word f=i+r, I is the first integer part, r is the first fractional part, the second control word d=ζ+h, ζ is the second integer part, h is the second fractional part, h=s/q, r=p/q, s, p and q are integers, T A Representing the total duration of the high level and the low level of the first sub-pulse, T A ＝I·Δ，T B Representing the total duration of the high level and the low level of the second sub-pulse, T B ＝(I+1)·Δ，T HS Representing the first high level duration, T HS ＝ζ·Δ，T HL Representing the second high level duration, T HL = (ζ+1) ·Δ, Δ representing the phase difference between any two adjacent reference pulses in the plurality of reference pulses.
In some exemplary embodiments, q is a least common multiple of the denominator in the shortest score corresponding to the first fractional part r and the denominator in the shortest score corresponding to the second fractional part h.
In some exemplary embodiments, the pulse output sub-circuit includes: the device comprises a first processing unit, a second processing unit and an output unit, wherein the first processing unit and the output unit are connected with the second processing unit; step 902 includes:
Outputting a first control signal and a second control signal according to the first control word and the second control word through a first processing unit;
selecting an I-th standard pulse from the multiple paths of reference pulses according to a first control signal by a second processing unit, selecting a J-th standard pulse from the multiple paths of reference pulses according to a second control signal, and selecting one path of reference pulse from the I-th standard pulse and the J-th standard pulse as an output pulse, wherein I is more than or equal to 1 and J is more than or equal to 1;
and outputting the pulse to be calculated according to the output pulse of the second processing unit through an output circuit.
In some exemplary embodiments, the logical calculations include at least one of addition, subtraction, multiplication, division, evolution, squaring.
The explanation of the above steps may refer to the corresponding descriptions in the above embodiments for the random calculation circuit, and the embodiments on the method side are not repeated.
The embodiment of the disclosure also provides a chip, which comprises any random computing circuit provided by the embodiment of the disclosure. The chip may be a CPU, GPU, or the like.
The embodiment of the disclosure also provides electronic equipment, which comprises any one of the chips provided by the embodiment of the disclosure. The electronic device may be a computer.
In this disclosure, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "plurality" refers to two or more, unless explicitly defined otherwise.
The term "and/or" in this disclosure is merely one association relationship describing the associated object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be noted that, different embodiments provided in the embodiments of the present disclosure can be referred to each other, and the embodiments of the present disclosure are not limited thereto. The sequence of the steps of the method embodiment provided in the embodiment of the present disclosure may be appropriately adjusted, and the steps may also be correspondingly increased or decreased according to the situation, so that any method that is easily conceivable to be changed by a person skilled in the art within the technical scope of the present disclosure should be covered within the protection scope of the present disclosure, and therefore will not be described in detail.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims (13)

1. A random computing circuit, comprising: a control sub-circuit, a pulse output sub-circuit, and a calculation sub-circuit, wherein:
the control sub-circuit is used for generating a first control word and a second control word according to a number to be calculated, inputting the first control word and the second control word into the pulse output sub-circuit, wherein the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
the pulse output sub-circuit is used for inputting a pulse to be calculated to the calculation sub-circuit according to the first control word, the second control word and the multipath reference pulses with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of each sub-pulse in the pulse to be calculated are controlled by the first control word; the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
The calculating sub-circuit is used for executing logic operation on the pulse to be calculated and outputting a calculation result.
2. The random computing circuit of claim 1, wherein the number of paths of the multiple reference pulses is K, K being an integer greater than 1, the control sub-circuit generating a first control word and a second control word from the number to be computed, comprising:
dividing the number to be calculated into a first numerator part A and a first denominator part B;
scaling up or down the first numerator portion A and the first denominator portion B to obtain a second numerator portion A ′ And a second denominator part B ′ So that the second denominator part B ′ Between 1 and K;
subjecting the second molecular moiety A ′ As the second control word and outputs the second denominator part B ′ As the first control word output.
3. The random computing circuit of claim 2, wherein the first numerator portion a and the first denominator portion B are scaled up or down by a factor of 2 k K is greater than or equal to 1.
4. The random computing circuit of claim 1, wherein the first control word comprises: a first integer part and a first fractional part, the second control word comprising: a second integer portion and a second fractional portion;
The total high-low level duration of the first sub-pulse and the second sub-pulse is controlled by the first integer part, the probability of occurrence of the first sub-pulse and the second sub-pulse in the pulse to be calculated is controlled by the first decimal part, the first high-level duration and the second high-level duration are controlled by the second integer part, and the probability of occurrence of the first high-level duration and the second high-level duration in the pulse to be calculated is controlled by the second decimal part.
5. The random computing circuit of claim 4, wherein the total duration of the high and low levels of the pulse to be computed is T FD ＝(q-p)·T A +p·T B The high level duration of the pulse to be calculated is T HD ＝(q-s)·T HS +s·T HL Wherein the first control word f=i+r, I is the first integer part, r is the first fractional part, the second control word d=ζ+h, ζ is the second integer part, h is the second fractional part, h=s/q, r=p/q, s, p and q are integers, T A Representing the total duration of the high level and the low level of the first sub-pulse, T A ＝I·Δ，T B Representing the total duration of the high level and the low level of the second sub-pulse, T B ＝(I+1)·Δ，T HS Representing the first high level duration, T HS ＝ζ·Δ，T HL Representing the second high level duration, T HL = (ζ+1) ·Δ, Δ representing the phase difference between any two adjacent reference pulses in the plurality of reference pulses.
6. The random computing circuit of claim 5, wherein q is a least common multiple of a denominator in a shortest score corresponding to the first fractional portion r and a denominator in a shortest score corresponding to the second fractional portion h.
7. The random computing circuit of claim 1, wherein the pulse output subcircuit comprises: the device comprises a signal generator, a first processing unit, a second processing unit and an output unit, wherein the second processing unit is respectively connected with the signal generator, the first processing unit and the output unit, and the device comprises the following components:
the signal generator is used for outputting multipath reference pulses with uniformly-spaced phases to the second processing unit;
the first processing unit is used for generating a first control signal according to the first control word and outputting the first control signal to the second processing unit, and generating a second control signal according to the second control word and outputting the second control signal to the second processing unit;
the second processing unit is used for selecting an I-th standard pulse from the multiple paths of standard pulses according to the first control signal, selecting a J-th standard pulse from the multiple paths of standard pulses according to the second control signal, and selecting one path of standard pulse from the I-th standard pulse and the J-th standard pulse as an output pulse, wherein I is less than or equal to 1, and J is less than or equal to 1;
The output unit is used for outputting the pulse to be calculated according to the output pulse of the second processing unit.
8. The random computing circuit of claim 7, wherein the first processing unit comprises a first logic controller and a second logic controller, wherein:
the first logic controller comprises a first adder, a first register and a second register, wherein the first register is respectively connected with the first adder and the second register, and comprises a first part for storing integers and a second part for storing decimal;
the first logic controller is configured to add, under the effect of an enable signal, the first control word to all bits stored in the first register through the first adder, and save an addition result to the first register at a rising edge of a second clock frequency; and storing the most significant bit stored in the first register into the second register as the first control signal at a rising edge of a second clock frequency;
the second logic controller comprises a second adder, a third register and a fourth register, the third register is respectively connected with the second adder and the fourth register, and the third register comprises a first part for storing integers and a second part for storing decimal;
The second logic controller is configured to add, under the effect of an enable signal, the second control word to the most significant bit stored in the first register through the second adder, and store an addition result into the third register when the rising edge of the second clock frequency occurs; and storing the most significant bit stored in the third register into the fourth register as the second control signal at a rising edge of the first clock frequency; the second clock frequency is opposite the first clock frequency.
9. The random computing circuit of claim 8, wherein the second processing unit comprises a first k→1 multiplexer, a second k→1 multiplexer, and a 2→1 multiplexer, K being an integer greater than 1, wherein:
the first K-1 multiplexer is used for selecting an I-th standard pulse output from K paths of standard pulses with uniformly-spaced phases under the control of a first control signal generated by the first logic controller;
the second K-1 multiplexer is used for selecting a J-th standard pulse output from K paths of standard pulses with uniformly-spaced phases under the control of a second control signal generated by the second logic controller;
The 2-1 multiplexer is configured to select, as an output signal of the 2-1 multiplexer, one of an I-th reference pulse output from the first K-1 multiplexer and a J-th reference pulse output from the second K-1 multiplexer at a rising edge of a first clock frequency.
10. The circuit of claim 9, wherein the output unit comprises: a D flip-flop comprising a data input, a clock input, an output, and an inverting output, wherein:
the clock input end of the D trigger is connected with the output end of the 2-1 multiplexer, the data input end of the D trigger is connected with the inverted output end, the output end outputs the signal of the first clock frequency, and the inverted output end outputs the signal of the second clock frequency.
11. A chip comprising a random computing circuit according to any one of claims 1 to 10.
12. An electronic device comprising the chip of claim 11.
13. A random calculation method for use in the random calculation circuit according to any one of claims 1 to 10, the random calculation method comprising:
Generating a first control word and a second control word according to a number to be calculated through the control sub-circuit, and inputting the first control word and the second control word into the pulse output sub-circuit, wherein the number to be calculated is between 0 and 1, and the ratio of the second control word to the first control word is equal to the number to be calculated;
inputting a pulse to be calculated to the calculation sub-circuit through the pulse output sub-circuit according to the first control word, the second control word and a plurality of paths of reference pulses with uniform phase intervals, wherein: the pulse to be calculated comprises at least one of a first sub-pulse and a second sub-pulse which are arranged on a time domain, the total high-low level time length of each sub-pulse is fixed, the high-level time length of each sub-pulse comprises at least one of a first high-level time length and a second high-level time length, and the total high-low level time length of each sub-pulse and the occurrence probability of each sub-pulse in the pulse to be calculated are controlled by the first control word;
the probability of each high-level duration appearing in the pulse to be calculated is controlled by the second control word;
and executing logic operation on the pulse to be calculated through the calculating sub-circuit, and outputting a calculation result.
CN202310537697.5A 2023-05-12 2023-05-12 Random computing circuit and method, chip and electronic equipment Pending CN116560618A (en)

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