CN116546748A - Method for strengthening circuit board line signal and structure thereof - Google Patents
Method for strengthening circuit board line signal and structure thereof Download PDFInfo
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- CN116546748A CN116546748A CN202210084919.8A CN202210084919A CN116546748A CN 116546748 A CN116546748 A CN 116546748A CN 202210084919 A CN202210084919 A CN 202210084919A CN 116546748 A CN116546748 A CN 116546748A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000005728 strengthening Methods 0.000 title abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 558
- 239000000758 substrate Substances 0.000 claims abstract description 202
- 230000008054 signal transmission Effects 0.000 claims abstract description 114
- 239000012792 core layer Substances 0.000 claims abstract description 57
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 230000002708 enhancing effect Effects 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
- 239000011241 protective layer Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000001125 extrusion Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0207—Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
Abstract
The invention provides a method for strengthening circuit signals of a circuit board and a structure thereof, wherein the method comprises the following steps: forming a first substrate body having a first signal transmission line layer and a second substrate body having a second signal transmission line layer on the upper surface and the lower surface of the core layer, respectively; forming a first circuit signal enhancement layer and a second circuit signal enhancement layer on the first substrate body and the second substrate body respectively; forming a third substrate body with a third signal transmission line layer and a fourth substrate body with a fourth signal transmission line layer on the bearing substrate respectively; separating the third substrate body and the fourth substrate body from the carrier substrate; the first signal transmission line layer and the third signal transmission line layer are combined through the first line signal enhancement layer, and the second signal transmission line layer and the fourth signal transmission line layer are combined through the second line signal enhancement layer.
Description
Technical Field
The present invention relates to a signal enhancement method and a structure thereof, and more particularly to a circuit board circuit signal enhancement method and a structure thereof.
Background
Please refer to fig. 7A-7H, which are flowcharts illustrating a conventional circuit board circuit manufacturing method, and fig. 7I is a top view of a conventional circuit board circuit structure. In fig. 7A, at least one through hole 701 is formed for a carrier 70 by a laser process. In fig. 7B, a first inner layer circuit 71 and a second inner layer circuit 72 are respectively formed on the upper surface and the lower surface of the carrier 70, and at least one through hole 701 is formed, wherein the first inner layer circuit 71 and the second inner layer circuit 72 are electrically connected through the at least one through hole 701. In fig. 7C, a first upper dielectric layer 73 and a first lower dielectric layer 74 are disposed on the upper surface and the lower surface of the carrier 70, respectively, and encapsulate the first inner circuit 71 and the second inner circuit 72. In fig. 7D, at least one first upper blind via 731 and at least one first lower blind via 741 are formed on the surfaces of the first upper dielectric layer 73 and the first lower dielectric layer 74, respectively, to expose a portion of the first inner layer line 71 and the second inner layer line 72. In fig. 7E, a first upper circuit layer 75 and a first lower circuit layer 76 are formed on the surfaces of the first upper dielectric layer 73 and the first lower dielectric layer 74, and in the at least one first upper blind hole 731 and the at least one first lower blind hole 741, respectively, wherein the first upper circuit layer 75 and the first lower circuit layer 76 are electrically connected through the at least one first upper blind hole 731, the at least one first lower blind hole 741, the first inner circuit 71 and the second inner circuit 72. In fig. 7F, a second upper dielectric layer 77, a second lower dielectric layer 78, a second upper circuit layer 79 and a second lower circuit layer 80 are formed respectively, wherein the second upper dielectric layer 77 is formed on the first upper dielectric layer 73, the second upper circuit layer 79 is formed on the surface of the second upper dielectric layer 77 and in at least one second upper blind hole 771 of the second upper dielectric layer 77, the second lower circuit layer 80 is formed on the surface of the second lower dielectric layer 78 and in at least one second lower blind hole 781 of the second lower dielectric layer 78, and the second upper circuit layer 79 and the second lower circuit layer 80 are electrically connected through the first upper circuit layer 75 and the first lower circuit layer 76. In fig. 7G, a third upper dielectric layer 81, a third lower dielectric layer 82, a third upper circuit layer 83 and a third lower circuit layer 84 are formed respectively, wherein the third upper circuit layer 83 is formed on the surface of the third upper dielectric layer 81 and in at least one third upper blind hole 811 of the third upper dielectric layer 81, the third lower circuit layer 84 is formed on the surface of the third lower dielectric layer 82 and in at least one third lower blind hole 821 of the third lower dielectric layer 82, and the third upper circuit layer 83 and the third lower circuit layer 84 are electrically connected through the second upper circuit layer 79 and the second lower circuit layer 80. In fig. 7H, a first solder mask layer 85 and a second solder mask layer 86 are formed on the surfaces of the third upper dielectric layer 81 and the third lower dielectric layer 82, respectively, and a portion of the third upper circuit layer 83 and a portion of the third lower circuit layer 84 are respectively covered, and another portion of the third upper circuit layer 83 and another portion of the third lower circuit layer 84 are respectively exposed, thereby completing the conventional circuit board circuit structure 7.
As described above, in the circuit board circuit structure 7, since the dielectric layers are stacked one on top of the other on the upper surface and the lower surface of the carrier 70, the dielectric layers are covered by the circuit layers. However, due to the structural rigidity of typical dielectric layer materials, hybrid materials such as epoxy, fiberglass, or other filler materials are often used. The materials are materials with high dielectric coefficients and high dielectric loss coefficients, so that signal transmission of the high-frequency signals of the circuit layer in the carrier 70 is easy to be influenced by the dielectric layer materials with high dielectric coefficients and high dielectric loss coefficients or the carrier 70 materials, the loss rate of the high-frequency signals is high, and the heat dissipation effect of the circuit board circuit structure 7 is influenced, and therefore the development of the circuit board circuit structure 7 is influenced, wherein the dielectric loss coefficient of the dielectric layer materials is about 0.013.
In addition, in the structure of the conventional circuit board circuit, since the circuit board circuit structure 7 is a multi-layered stacked structure, the size of the circuit board formed by stacking is large, and therefore, when a part of the circuit of the multi-layered structure has a problem or a process error, the problem or the process error is continuously accumulated in the structure of each layer when the part of the circuit cannot be removed from the multi-layered structure, thereby affecting the overall yield of the circuit board circuit structure 7.
Accordingly, how to provide a method for enhancing the circuit signal of a circuit board and a structure thereof have become the subject of urgent research.
Disclosure of Invention
In view of the above problems, the present invention provides a method for enhancing a circuit signal of a circuit board, comprising the following steps: forming a first substrate body with a first signal transmission line layer and a second substrate body with a second signal transmission line layer on the upper surface and the lower surface of a core layer of the core layer respectively; forming a first line signal enhancement layer and a second line signal enhancement layer on the first substrate surface of the first substrate body and the second substrate surface of the second substrate body respectively, wherein the first line signal enhancement layer has a first dielectric coefficient lower than the first substrate body and a first dielectric loss coefficient lower than the first substrate body, and the second line signal enhancement layer has a second dielectric coefficient lower than the second substrate body and a second dielectric loss coefficient lower than the second substrate body; forming a third substrate body with a third signal transmission line layer and a fourth substrate body with a fourth signal transmission line layer on the upper surface of the bearing substrate and the lower surface of the bearing substrate respectively; separating the third substrate body from the carrier substrate and separating the fourth substrate body from the carrier substrate; a third signal transmission line layer combining the first line signal enhancement layer and the third substrate body, and a fourth signal transmission line layer combining the second line signal enhancement layer and the fourth substrate body; the combined first line signal enhancement layer is arranged around part of the first signal transmission line layer, the combined second line signal enhancement layer is arranged around part of the second signal transmission line layer, and part of the first signal transmission line layer, the second signal transmission line layer, the third signal transmission line layer and the fourth signal transmission line layer are electrically connected to form a circuit board line signal enhancement structure.
The invention provides a circuit board line signal enhancement structure, which comprises a core layer, a first substrate body, a second substrate body, a first line signal enhancement layer, a second line signal enhancement layer, a third substrate body and a fourth substrate body. The first substrate body comprises a first signal transmission line layer and is arranged on the upper surface of the core layer. The second substrate body comprises a second signal transmission line layer and is arranged on the lower surface of the core layer. The first line signal enhancement layer is disposed around a portion of the first signal transmission line layer. The second line signal enhancement layer is disposed around a portion of the second signal transmission line layer. The third substrate body is arranged on the first substrate body and is provided with a third signal transmission line layer. The fourth substrate body is arranged on the second substrate body and provided with a fourth signal transmission line layer. The first line signal enhancement layer has a first dielectric coefficient lower than the first substrate body and a first dielectric loss coefficient lower than the first substrate body, and the second line signal enhancement layer has a second dielectric coefficient lower than the second substrate body and a second dielectric loss coefficient lower than the second substrate body.
In the circuit board line signal strengthening method and the structure thereof, the signal strengthening layer with low dielectric coefficient and low dielectric loss coefficient is arranged on the preset line transmission path, thereby reducing the loss rate of high-frequency signals transmitted in the carrier board line and simultaneously having the heat dissipation function. In addition, the circuit board line signal strengthening method and the structure thereof manufacture asymmetric coreless carrier boards through the structure of the separated substrate (bearing substrate), and arrange each substrate body on different substrates, so that in the process of reducing the whole circuit board line structure, line detection is carried out, bad parts are removed, and the process yield of the subsequent circuit board line structure is further improved.
Drawings
FIGS. 1A-1E are flowcharts of steps for forming a core layer, a first substrate body and a second substrate body according to the present invention;
FIG. 2 is a cross-sectional view of forming a first and a second line signal enhancement layers on the surfaces of a first and a second substrate body;
FIG. 3 is a cross-sectional view of a structure for forming a carrier substrate, a third substrate body and a fourth substrate body;
fig. 4A to 4D are flowcharts of separating the third substrate body and the fourth substrate body from the carrier substrate;
FIGS. 5A and 5D are an exploded view, a combined view, a partially enlarged view and a top view of a circuit board circuit signal enhancement structure of the present invention;
FIG. 6 is a cross-sectional view of a circuit board circuit signal enhancement structure of the present invention;
FIGS. 7A-7H are flowcharts of conventional circuit board circuit manufacturing methods; and
fig. 7I is a top view of a conventional circuit board circuit structure.
Detailed Description
The method for strengthening the circuit signal of the circuit board comprises the following steps: in step S11, a first substrate body having a first signal transmission line layer and a second substrate body having a second signal transmission line layer are formed on the upper surface and the lower surface of the core layer, respectively; in step S12, forming a first line signal enhancement layer and a second line signal enhancement layer on the surfaces of the first substrate body and the second substrate body, respectively, wherein the first line signal enhancement layer and the second line signal enhancement layer have dielectric coefficients lower than those of the first substrate body and the second substrate body and dielectric loss coefficients lower than those of the first substrate body and the second substrate body, respectively; in step S13, a third substrate body having a third signal transmission line layer and a fourth substrate body having a fourth signal transmission line layer are formed on the upper surface and the lower surface of the carrier substrate, respectively; in step S14, separating the third substrate body and the fourth substrate body from the carrier substrate, and removing the carrier substrate; in step S15, the first signal transmission line layer of the first substrate body and the third signal transmission line layer of the third substrate body are combined through the first line signal enhancement layer, and the second signal transmission line layer of the second substrate body and the fourth signal transmission line layer of the fourth substrate body are combined through the second line signal enhancement layer; the combined first line signal strengthening layer is coated around a preset first signal transmission line layer, the combined second line signal strengthening layer is coated around a preset second signal transmission line layer, and part of the first signal transmission line layer, the second signal transmission line layer, the third signal transmission line layer and the fourth signal transmission line layer are electrically connected to form a circuit board line signal strengthening structure.
Please refer to fig. 1A to 1E, which are flowcharts illustrating steps of forming a core layer, a first substrate body and a second substrate body in step S11. As shown in fig. 1A, in step S11, a core layer 10 is provided, and at least one through hole 101 is formed in the core layer 10; as shown in fig. 1B, in step S12, a first inner layer circuit 11 and a second inner layer circuit 12 are formed on the upper surface and the lower surface of the core layer 10, respectively, and a first inner layer circuit 11 and a second inner layer circuit 12 are formed in at least one through hole 101, wherein the first inner layer circuit 11 and the second inner layer circuit 12 formed in the at least one through hole 101 are electrically connected; as shown in fig. 1C, in step S13, a first dielectric layer 13 and a second dielectric layer 14 are respectively disposed on the upper surface and the lower surface of the core layer 10, and cover the first inner layer 11 and the second inner layer 12; as shown in fig. 1D, in step S14, at least one first blind via 131 and at least one second blind via 141 are formed on the surfaces of the first dielectric layer 13 and the second dielectric layer 14, respectively, so as to expose a portion of the first inner circuit 11 and the second inner circuit 12; as shown in fig. 1E, in step S15, a first circuit layer 15 and a second circuit layer 16 are formed on the surfaces of the first dielectric layer 13 and the second dielectric layer 14, and the first circuit layer 15 and the second circuit layer 16 are formed in at least one first blind hole 131 and at least one second blind hole 141, wherein a portion of the first circuit layer 15 and a portion of the second circuit layer 16 are electrically connected through the at least one first blind hole 131, the at least one second blind hole 141, the first inner circuit 11 and the second inner circuit 12 and protrude out of the at least one first blind hole 131 and the at least one second blind hole 141 to form a first signal transmission circuit layer 17 and a second signal transmission circuit layer 18, respectively, wherein the first substrate body a includes a structure on the upper surface of the core layer 10, and the second substrate body B includes a structure under the lower surface of the core layer 10. After forming the first substrate body a having the first signal transmission line layer 17 and the second substrate body B having the second signal transmission line layer 18 on the upper surface and the lower surface of the core layer 10, the line inspection is performed with respect to the completed core layer 10 structure, and the portions of the lines having damage and poor line electrical characteristics are cut off to pick out the core layer 10 having a good structure.
Referring to fig. 2, a cross-sectional view of the first and second circuit signal enhancement layers formed on the surfaces of the first and second substrate bodies in step S12 is shown. As shown in fig. 1E, after the first substrate body a and the second substrate body B are structured on the upper surface and the lower surface of the core layer 10, a first line signal enhancement layer 19A and a second line signal enhancement layer 19B are formed on the surfaces of the first substrate body a and the second substrate body B, respectively.
Please refer to fig. 3, which is a cross-sectional view illustrating a structure of the carrier substrate, the third substrate body, and the fourth substrate body according to step S13. Step S13 further comprises the following steps: in step S130, the carrier substrate 20 is provided, wherein the carrier substrate 20 may be a resin matrix (CCL) having double-sided copper foils 201, 202; in step S131, a first release layer and a second release layer (not shown) are formed on the upper surface and the lower surface of the carrier substrate 20, respectively; in step S132, a first upper signal connection layer 21 and a first lower signal connection layer 22 are formed on the first release layer and the second release layer, respectively; in step S133, a first upper dielectric layer 23 and a first lower dielectric layer 24 are respectively disposed on the upper signal connection layer 21 and the first lower signal connection layer 22, and cover the first upper signal connection layer 21 and the first lower signal connection layer 22; in step S134, at least one first upper blind via 231 and at least one first lower blind via 241 are formed on the surfaces of the first upper dielectric layer 23 and the first lower dielectric layer 24, respectively, to expose portions of the first upper signal connection layer 21 and the first lower signal connection layer 22; in step S135, a second upper circuit layer 25 and a second lower circuit layer 26 are respectively formed on the surfaces of the first upper dielectric layer 23 and the first lower dielectric layer 24, and in at least one first upper blind via 231 and at least one first lower blind via 241; in step S136, a second upper dielectric layer 27 and a second lower dielectric layer 28 are respectively disposed on the surfaces of the first upper dielectric layer 23 and the first lower dielectric layer 24, and cover the second upper circuit layer 25 and the second lower circuit layer 26; in step S137, at least one second upper blind via 271 and at least one second lower blind via 281 are formed on the surfaces of the second upper dielectric layer 27 and the second lower dielectric layer 28, respectively, to expose a portion of the second upper circuit layer 25 and the second lower circuit layer 26; in step S138, a third upper circuit layer 29 and a third lower circuit layer 30 are respectively formed on the surfaces of the second upper dielectric layer 27 and the second lower dielectric layer 28 and in at least one second upper blind via 271 and at least one second lower blind via 281, wherein a portion of the third upper circuit layer 29 is electrically connected to the second upper circuit layer 25 and the first upper signal connection layer 21 to form a third signal transmission circuit layer 31, and a portion of the third lower circuit layer 30 is electrically connected to the second lower circuit layer 26 and the first lower signal connection layer 22 to form a fourth signal transmission circuit layer 32; in step S139, the first solder mask layer 33 and the second solder mask layer 34 are formed on the surfaces of the second upper dielectric layer 27 and the second lower dielectric layer 28, and a portion of the third upper circuit layer 29 and the third lower circuit layer 30 are exposed, wherein the third substrate body C comprises a structure on the upper surface of the carrier substrate 20, and the fourth substrate body D comprises a structure under the lower surface of the carrier substrate 20. It should be noted that, in the embodiment of the present invention, the third substrate body C and the fourth substrate body D disposed on the upper surface and the lower surface of the carrier substrate 20 are a multi-layer circuit board structure, and the number of layers (including the dielectric layer and the circuit layer) of the multi-layer circuit board is merely illustrative and not limited to three layers in this embodiment. After the third substrate body C and the fourth substrate body D are formed, the circuit is detected for the completed third substrate body C and fourth substrate body D, and the portion of the circuit with damage and poor circuit electrical property is cut off to select the third substrate body C and the fourth substrate body D with good structure.
Referring to fig. 4A to fig. 4D, in step S14, a flow chart of separating the third substrate body and the fourth substrate body from the carrier substrate is shown, and step S14 further includes the following steps. As shown in fig. 4A, in step S141, the third substrate body C and the fourth substrate body D are separated from the carrier substrate 20. As shown in fig. 4B, in step S142, the first protection layer 35 and the second protection layer 36 are disposed on the surface of the first upper signal connection layer 21 and the surface of the first lower signal connection layer 22, respectively, and in an embodiment of the present invention, the first protection layer 35 and the second protection layer 36 are etching-resistant dry films and are formed on the surface of the first upper signal connection layer 21 and the surface of the first lower signal connection layer 22 in an exposure and development manner, so as to expose the positions where the first upper signal connection layer 21 and the first lower signal connection layer 22 need to be etched. As shown in fig. 4C, in step S143, portions of the first upper signal connection layer 21 and the first lower signal connection layer 22 are etched. As shown in fig. 4D, in step S144, the first protection layer 35 and the second protection layer 36 are removed to form a third substrate body C and a fourth substrate body D.
Please refer to fig. 5A and 5D, which are an exploded view, a combined view, a partially enlarged view and a top view of the circuit board circuit signal enhancement structure according to step S15. As shown in fig. 5A and 5B, after the first substrate body a, the core layer 10, the second substrate body B, the third substrate body C and the fourth substrate body D are completed according to the above steps, in step S15, the first signal transmission line layer 17 of the first substrate body a is combined with the third signal transmission line layer 31 of the third substrate body C through the first line signal enhancement layer 19A, and the second signal transmission line layer 18 of the second substrate body B is combined with the fourth signal transmission line layer 32 of the fourth substrate body D through the second line signal enhancement layer 19B, that is, the third substrate body C is disposed on the first substrate body a, the first substrate body a is disposed on the upper surface of the core layer 10, the fourth substrate body D is disposed under the second substrate body B, and the second substrate body B is disposed on the lower surface of the core layer 10. As shown in the partial enlarged view of fig. 5C, the combined first line signal enhancement layer 19A is wrapped around the preset first signal transmission line layer 17, the combined second line signal enhancement layer 19B is wrapped around the preset second signal transmission line layer 18, and part of the first signal transmission line layer 17, the second signal transmission line layer 18, the third signal transmission line layer 31 and the fourth signal transmission line layer 32 are electrically connected to form a circuit board line signal enhancement structure 1.
Referring to fig. 5D again, it should be noted that in the above-mentioned circuit board circuit signal enhancement method, the circuit board circuit signal enhancement structure 1 does not cover the first circuit signal enhancement layer 19A for the whole first signal transmission circuit layer 17 or cover the second circuit signal enhancement layer 19B for the whole second signal transmission circuit layer 18, but covers the first circuit signal enhancement layer 19A around the first signal transmission circuit layer 17 and the second circuit signal enhancement layer 19B around the second signal transmission circuit layer 18 according to the predetermined signal transmission path so as to reduce the loss of the high-frequency signal in the circuit transmission path.
In the embodiment of the invention, the first line signal enhancement layer 19A and the second line signal enhancement layer 19B are made of a pure plastic material having a dielectric constant less than or equal to 2 and a dielectric loss coefficient less than or equal to 0.002, and include epoxy resin, and are bonded to the first signal transmission line layer 17 and the first upper signal connection layer 21 in an extrusion manner during the process of bonding the first substrate body a and the third substrate body C, and bonded to the second signal transmission line layer 18 and the first lower signal connection layer 22 in an extrusion manner during the process of bonding the second substrate body B and the fourth substrate body D. Further, as shown in fig. 4C, in step S143, after etching portions of the first upper signal connection layer 21 and the first lower signal connection layer 22, a groove structure is formed, and in step S15 of fig. 1E, the first circuit layer 15 and the second circuit layer 16 protrude from the first blind hole 131 and the second blind hole 141, respectively, so that when the first signal enhancement layer 19A is combined with the first signal transmission circuit layer 17 of the first substrate body a and the third signal transmission circuit layer 31 of the third substrate body C, and the second signal enhancement layer 19B is combined with the second signal transmission circuit layer 18 of the second substrate body B and the fourth signal transmission circuit layer 32 of the fourth substrate body D, the first circuit layer 15 and the second circuit layer 16 protruding from the first blind hole 131 and the second blind hole 141 are pressed against and butt-jointed in the first upper signal connection layer 21 and the first lower signal connection layer 22 of the groove structure, respectively. Furthermore, by this bonding, the first and second circuit signal enhancement layers 19A and 19B respectively disposed on the surfaces of the first and second substrate bodies a and B are further pressed into the first upper and lower signal connection layers 21 and 22 of the groove structure, and are wrapped around the first and second circuit layers 15 and 16.
Please refer to fig. 6, which is a cross-sectional view of the circuit board circuit signal enhancement structure of the present invention. The circuit board line signal enhancement structure 1 comprises a core layer 10, a first substrate body a, a second substrate body B, a first line signal enhancement layer 19A, a second line signal enhancement layer 19B, a third substrate body C and a fourth substrate body D. The first substrate body a has a first signal transmission line layer 17 and is disposed on the upper surface of the core layer 10. The second substrate body B has a second signal transmission line layer 18 and is disposed on the lower surface of the core layer 10. The first signal enhancement layer 19A is disposed around a portion of the first signal transmission line layer 17. The second signal enhancement layer 19B is disposed around a portion of the second signal transmission line layer 18. The third substrate body C is disposed on the first substrate body a and has a third signal transmission line layer 31. The fourth substrate body D is disposed on the second substrate body B and has a fourth signal transmission line layer 32. Part of the first signal transmission line layer 17, the second signal transmission line layer 18, the third signal transmission line layer 31 and the fourth signal transmission line layer 32 are electrically connected, and the first line signal enhancement layer 19A and the second line signal enhancement layer 19B have dielectric coefficients lower than those of the first substrate body a and the second substrate body B and lower than those of the first substrate body a and the second substrate body B, respectively.
As shown in fig. 6, the core layer 10 includes at least one via 101, a first inner layer 11, a second inner layer 12, a first dielectric layer 13, a second dielectric layer 14, a first circuit layer 15, and a second circuit layer 16. The first inner layer 11 is disposed on the upper surface of the core layer 10 and in the at least one through hole 101. The second inner layer circuit 12 is disposed on the lower surface of the core layer 10 and in the at least one through hole 101, such that the first inner layer circuit 11 is electrically connected to the second inner layer circuit 12 through the at least one through hole 101. The first dielectric layer 13 is disposed on the upper surface of the core layer 10 and encapsulates the first inner layer 11. The second dielectric layer 14 is disposed on the lower surface of the core layer 10 and encapsulates the second inner layer circuit 12. The first circuit layer 15 is disposed on the surface of the first dielectric layer 13 and disposed in at least one first blind via 131 of the first dielectric layer 13. The second circuit layer 16 is disposed on the surface of the second dielectric layer 14 and disposed in the at least one second blind via 141 of the second dielectric layer 14. The first circuit layer 15 and the second circuit layer 16 are electrically connected through at least one first blind hole 131, at least one second blind hole 141, the first inner circuit 11 and the second inner circuit 12, and protrude from at least one first blind hole 131 and at least one second blind hole 141 to form a first signal transmission circuit layer 17 and a second signal transmission circuit layer 18.
As shown in fig. 6, the third substrate body C includes a first upper signal connection layer 21, a first upper dielectric layer 23, a second upper circuit layer 25, a second upper dielectric layer 27, a third upper circuit layer 29 and a first solder mask layer 33. A part of the first upper signal connection layer 21 is disposed on the surface of the first dielectric layer 13 of the core layer 10, and another part is disposed on the first circuit layer 15 of the core layer 10. The first upper dielectric layer 23 is disposed on the first dielectric layer 13 of the core layer 10, and encapsulates the first upper signal connection layer 21, the first circuit layer 15 and the first circuit signal enhancement layer 19A. The second upper circuit layer 25 is disposed on the surface of the first upper dielectric layer 23 and in the at least one first upper blind via 231 of the first upper dielectric layer 23. The second upper dielectric layer 27 is disposed on the surface of the first upper dielectric layer 23 and covers the second upper circuit layer 25. The third upper circuit layer 29 is disposed on the surface of the second upper dielectric layer 27, and in the at least one second upper blind via 271 of the second upper dielectric layer 27. The first solder mask layer 33 is disposed on the surface of the second upper dielectric layer 27 and exposes a portion of the third upper circuit layer 29.
As shown in fig. 6, the fourth substrate body D includes a first lower signal connection layer 22, a first lower dielectric layer 24, a second lower circuit layer 26, a second lower dielectric layer 28, a third lower circuit layer 30 and a second solder mask layer 34. A portion of the first lower signal connection layer 22 is disposed on the surface of the second dielectric layer 14 of the core layer 10, and another portion is disposed on the second circuit layer 16 of the core layer 10. The first lower dielectric layer 24 is disposed on the second dielectric layer 14 of the core layer 10, and encapsulates the first lower signal connection layer 22, the second circuit layer 16 and the second circuit signal enhancement layer 19B. The second lower circuit layer 26 is disposed on the surface of the first lower dielectric layer 24 and in at least one first lower blind via 241 of the first lower dielectric layer 24. The second lower dielectric layer 28 is disposed on the surface of the first lower dielectric layer 24 and covers the second lower circuit layer 26. The third lower circuit layer 30 is disposed on the surface of the second lower dielectric layer 28, and at least one second lower blind via 281 of the second lower dielectric layer 28. The second solder mask layer 34 is disposed on the surface of the second lower dielectric layer 28 and exposes a portion of the third lower circuit layer 30. The third upper circuit layer 29 and the third lower circuit layer 30 are electrically connected through at least one second upper blind via 271, at least one second lower blind via 281, the second upper circuit layer 25 and the second lower circuit layer 26 to form a third signal transmission circuit layer 31 and a fourth signal transmission circuit layer 32.
In the embodiment of the invention, the first line signal enhancement layer 19A and the second line signal enhancement layer 19B are made of a pure plastic material with a dielectric constant less than or equal to 2 and a dielectric loss coefficient less than or equal to 0.002.
In summary, the circuit board line signal enhancement method and the structure thereof of the present invention are provided with the signal enhancement layer with low dielectric coefficient and low dielectric loss coefficient on the predetermined line transmission path, so as to reduce the loss rate of the high frequency signal transmitted in the carrier board line, and simultaneously have the heat dissipation function. In addition, the circuit board line signal strengthening method and the structure thereof manufacture asymmetric coreless carrier boards through the structure of the separated substrate (bearing substrate), and arrange each substrate body on different substrates, so that in the process of reducing the whole circuit board line structure, line detection is carried out, bad parts are removed, and the process yield of the subsequent circuit board line structure is further improved.
Claims (10)
1. A method for enhancing a circuit signal of a circuit board, comprising:
forming a first substrate body having a first signal transmission line layer on an upper surface of a core layer;
forming a second substrate body with a second signal transmission line layer on the lower surface of a core layer of the core layer;
forming a first circuit signal enhancement layer on a first substrate surface of the first substrate body; wherein the first line signal enhancement layer has a first dielectric coefficient lower than the first substrate body and a first dielectric loss coefficient lower than the first substrate body;
forming a second circuit signal enhancement layer on a second substrate surface of the second substrate body; wherein the second line signal enhancement layer has a second dielectric constant lower than the second substrate body and a second dielectric loss coefficient lower than the second substrate body;
forming a third substrate body with a third signal transmission line layer on the upper surface of a bearing substrate;
forming a fourth substrate body with a fourth signal transmission line layer on the lower surface of a bearing substrate of the bearing substrate;
separating the third substrate body from the carrier substrate, and separating the fourth substrate body from the carrier substrate; and
combining the first line signal enhancement layer with the third signal transmission line layer of the third substrate body, and combining the second line signal enhancement layer with the fourth signal transmission line layer of the fourth substrate body;
the combined first line signal enhancement layer is arranged around part of the first signal transmission line layer, and the combined second line signal enhancement layer is arranged around part of the second signal transmission line layer to form a circuit board line signal enhancement structure.
2. The method of claim 1, wherein forming the first substrate body with the first signal transmission line layer on the upper surface of the core layer and forming the second substrate body with the second signal transmission line layer on the lower surface of the core layer comprises:
providing the core layer and forming at least one through hole in the core layer;
forming a first inner layer circuit on the upper surface of the core layer, forming a second inner layer circuit on the lower surface of the core layer, and forming the first inner layer circuit and the second inner layer circuit in the at least one through hole; wherein the first inner layer circuit and the second inner layer circuit formed in the at least one through hole are electrically connected;
a first dielectric layer is arranged on the upper surface of the core layer and coats the first inner layer circuit;
a second dielectric layer is arranged on the lower surface of the core layer and coats the second inner layer circuit;
forming at least one first blind hole in the first dielectric layer to expose part of the first inner layer circuit;
forming at least one second blind hole in the second dielectric layer to expose part of the second inner layer circuit;
forming a first circuit layer on the surface of the first dielectric layer and in the at least one first blind hole;
forming a second circuit layer on the surface of the second dielectric layer and in the at least one second blind hole;
the first circuit layer and the second circuit layer are electrically connected through the at least one first blind hole, the at least one second blind hole, the first inner layer circuit and the second inner layer circuit and protrude out of the at least one first blind hole and the at least one second blind hole so as to form the first signal transmission circuit layer and the second signal transmission circuit layer.
3. The method of claim 1, wherein forming the third substrate body with the third signal transmission line layer on the upper surface of the carrier substrate, and forming the lower surface of the carrier substrate with the fourth signal transmission line layer comprises:
providing the bearing substrate;
forming a first release layer on the upper surface of the bearing substrate;
forming a second release layer on the lower surface of the bearing substrate;
forming a first upper signal connection layer on the first release layer;
forming a first lower signal connection layer on the second release layer;
a first upper dielectric layer is arranged on the first upper signal connection layer and coats the first upper signal connection layer;
a first lower dielectric layer is arranged on the first lower signal connection layer and coats the first lower signal connection layer;
forming at least one first upper blind via on the first upper dielectric layer to expose a portion of the first upper signal connection layer;
forming at least one first lower blind via on the first lower dielectric layer to expose a portion of the first lower signal connection layer;
forming a second upper circuit layer on the first upper dielectric layer and in the at least one first upper blind hole;
forming a second lower circuit layer on the first lower dielectric layer and in the at least one first lower blind hole;
a second upper dielectric layer is arranged on the first upper dielectric layer and coats the second upper circuit layer;
a second lower dielectric layer is arranged on the first lower dielectric layer and coats the second lower circuit layer;
forming at least one second upper blind hole on the second upper dielectric layer to expose part of the second upper circuit layer;
forming at least one second lower blind hole on the second lower dielectric layer to expose part of the second lower circuit layer;
forming a third upper circuit layer on the second upper dielectric layer and in the at least one second upper blind hole;
forming a third lower circuit layer on the second lower dielectric layer and in the at least one second lower blind hole;
wherein the third upper wiring layer is electrically connected to the second upper wiring layer and the first upper signal connection layer to form the third signal transmission wiring layer, and the third lower wiring layer is electrically connected to the second lower wiring layer and the first lower signal connection layer to form the fourth signal transmission wiring layer;
forming a first solder mask layer on the second upper dielectric layer and exposing a part of the third upper circuit layer; and
forming a second solder mask layer on the second lower dielectric layer and exposing a portion of the third lower circuit layer.
4. The method of claim 3, wherein separating the third substrate body from the carrier substrate, and separating the fourth substrate body from the carrier substrate comprises:
setting a first protection layer on the first upper signal connection layer;
setting a second protection layer on the first lower signal connection layer;
etching part of the first upper signal connection layer and the first lower signal connection layer; and
and removing the first protective layer and the second protective layer.
5. The method of claim 3, wherein the first and second signal enhancement layers are epoxy resin, and are bonded to the first signal transmission layer and the first upper signal connection layer, and the second signal transmission layer and the first lower signal connection layer by pressing.
6. The method of claim 1, wherein the first dielectric constant of the first line signal enhancement layer and the second dielectric constant of the second line signal enhancement layer are less than or equal to 2, and the first dielectric loss coefficient and the second dielectric loss coefficient are less than or equal to 0.002.
7. A circuit board line signal enhancement structure, comprising:
a core layer;
the first substrate body is provided with a first signal transmission line layer and is arranged on the upper surface of a core layer of the core layer;
the second substrate body is provided with a second signal transmission line layer and is arranged on the lower surface of a core layer of the core layer;
the first line signal enhancement layer is arranged around part of the first signal transmission line layer; wherein the first line signal enhancement layer has a first dielectric coefficient lower than the first substrate body and a first dielectric loss coefficient lower than the first substrate body;
the second line signal enhancement layer is arranged around part of the second signal transmission line layer; wherein the second line signal enhancement layer has a second dielectric constant lower than the second substrate body and a second dielectric loss coefficient lower than the second substrate body;
the third substrate body is arranged on the first substrate body and is provided with a third signal transmission line layer; and
a fourth substrate body disposed on the second substrate body and having a fourth signal transmission line layer;
wherein a part of the first signal transmission line layer, the second signal transmission line layer, the third signal transmission line layer, and the fourth signal transmission line layer are electrically connected.
8. The circuit board wiring signal enhancement structure according to claim 7, wherein said core layer further comprises:
at least one through hole;
a first inner layer circuit arranged on the upper surface of the core layer and in the at least one through hole;
a second inner layer circuit arranged on the lower surface of the core layer and in the at least one through hole;
the first dielectric layer is arranged on the upper surface of the core layer and coats the first inner layer circuit;
the second dielectric layer is arranged on the lower surface of the core layer and coats the second inner layer circuit;
the first circuit layer is arranged on the first dielectric layer and at least one first blind hole of the first dielectric layer; and
the second circuit layer is arranged on the second dielectric layer and in at least one second blind hole of the second dielectric layer;
wherein the first inner layer circuit and the second inner layer circuit formed in the at least one through hole are electrically connected;
the first circuit layer and the second circuit layer are electrically connected through the at least one first blind hole, the at least one second blind hole, the first inner layer circuit and the second inner layer circuit and protrude out of the at least one first blind hole and the at least one second blind hole so as to form the first signal transmission circuit layer and the second signal transmission circuit layer.
9. The circuit board wiring signal enhancement structure according to claim 8, wherein the third substrate body comprises:
a first upper signal connection layer, a part of which is arranged on the surface of the first dielectric layer, and another part of which is arranged on the first circuit layer;
the first upper dielectric layer is arranged on the first dielectric layer and is used for coating the first upper signal connection layer, the first circuit layer and the first circuit signal enhancement layer;
a second upper circuit layer disposed on the first upper dielectric layer and in at least one first upper blind via of the first upper dielectric layer;
the second upper dielectric layer is arranged on the first upper dielectric layer and coats the second upper circuit layer;
a third upper circuit layer disposed on the second upper dielectric layer and in at least one second upper blind via of the second upper dielectric layer; and
the first solder mask layer is arranged on the second upper dielectric layer and exposes part of the third upper circuit layer;
the fourth substrate body includes:
a first lower signal connection layer, a part of which is arranged on the second dielectric layer, and another part of which is arranged on the second circuit layer;
the first lower dielectric layer is arranged on the second dielectric layer and coats the first lower signal connection layer, the second circuit layer and the second circuit signal enhancement layer;
a second lower circuit layer disposed on the first lower dielectric layer and in at least one first lower blind via of the first lower dielectric layer;
the second lower dielectric layer is arranged on the first lower dielectric layer and coats the second lower circuit layer;
a third lower circuit layer disposed on the second lower dielectric layer and in at least one second lower blind via of the second lower dielectric layer; and
the second solder mask layer is arranged on the second lower dielectric layer and exposes part of the third lower circuit layer;
the third upper circuit layer and the third lower circuit layer are electrically connected through the at least one second upper blind hole, the at least one second lower blind hole, the second upper circuit layer and the second lower circuit layer to form the third signal transmission circuit layer and the fourth signal transmission circuit layer.
10. The circuit board routing signal enhancement structure of claim 7, wherein the first dielectric coefficient of the first routing signal enhancement layer and the second dielectric coefficient of the second routing signal enhancement layer are less than or equal to 2, and the first dielectric loss coefficient and the second dielectric loss coefficient are less than or equal to 0.002.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210084919.8A CN116546748A (en) | 2022-01-25 | 2022-01-25 | Method for strengthening circuit board line signal and structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210084919.8A CN116546748A (en) | 2022-01-25 | 2022-01-25 | Method for strengthening circuit board line signal and structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116546748A true CN116546748A (en) | 2023-08-04 |
Family
ID=87447600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210084919.8A Pending CN116546748A (en) | 2022-01-25 | 2022-01-25 | Method for strengthening circuit board line signal and structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116546748A (en) |
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2022
- 2022-01-25 CN CN202210084919.8A patent/CN116546748A/en active Pending
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