CN116546352A - Control method and control device of optical module - Google Patents
Control method and control device of optical module Download PDFInfo
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- CN116546352A CN116546352A CN202310535313.6A CN202310535313A CN116546352A CN 116546352 A CN116546352 A CN 116546352A CN 202310535313 A CN202310535313 A CN 202310535313A CN 116546352 A CN116546352 A CN 116546352A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q2011/0079—Operation or maintenance aspects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
- H04Q11/0062—Network aspects
- H04Q2011/0084—Quality of service aspects
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Abstract
The invention relates to a control method, a control device, equipment and a storage medium of an optical module, which are used for controlling and managing the optical module in a switch system through a programmed CPLD, wherein the control method comprises a power-on starting control step, and comprises the following steps: when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified; when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the optical module to be started normally. Through the technical scheme, the problems of low CPU utilization rate, low running speed and instability when the CPU is used for managing the optical module in the switch at present can be solved.
Description
Technical Field
The invention relates to the technical field of switch optical modules, in particular to a control method and a control device of an optical module.
Background
Currently, an optical module is one of the important components in a switch system, and it takes on the task of transmitting optical signals in the switch system. The number and quality of the optical modules of the switch directly affect the transmission performance quality and stability of the switch. The control and management of optical modules is one of the important functions in a switch system.
The traditional exchanger system uses CPU (CentralProcessorUnit) or MCU (MicroControl Unit) to realize the management of the optical module, including the monitoring, power supply control, hot plug function and the like of the optical module; in this working mode, the CPU needs to determine the in-place status of the optical module in real time, which increases the utilization rate of the CPU and reduces the CPU running speed of the switch system.
When the CPU is used for controlling the power supply of the optical module, the CPU is controlled to send out a delay signal with fixed time, and the optical module timing control implementation mode is difficult to operate and unstable.
Disclosure of Invention
In order to solve the technical problems, the invention provides a control method, a control device, equipment and a storage medium of an optical module, wherein the control method is used for solving the problems of low CPU utilization rate, low running speed and instability when a CPU is used for managing the optical module in a switch at present.
In order to achieve the above object, the present invention provides a control method of an optical module, configured to control and manage an optical module in a switch system by using a programmed CPLD, where the control method includes a power-on start control step, which includes:
when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the optical module to be started normally.
Further, the control method further includes an in-situ monitoring step, which includes:
an in-place monitoring circuit in the CPLD monitors in real time an in-place signal pin of the optical module; the jitter removing circuit in the bit monitoring circuit carries out voltage deburring on the bit pin signal on the bit signal pin;
when the deburred on-site pin signal is converted from an off-site state to an on-site state and the on-site state maintains to meet a first preset clock, the on-site monitoring circuit judges that the optical module is on-site and outputs the on-site signal of the optical module to the delay output circuit;
when the deburred on-site pin signal is converted from the on-site state to the off-site state and the off-site state maintains to meet the second preset clock, the on-site monitoring circuit judges that the optical module is not on-site and outputs the optical module off-site signal to the delay output circuit.
Further, when the delay output circuit in the CPLD receives the bit signal of the optical module, the delay output circuit outputs a high level according to a first preset time delay, which specifically includes:
when a first precision delay circuit in the delay output circuit receives an optical module in-place signal, judging whether the maintenance time of the optical module in-place signal meets a first delay time; if yes, outputting high voltage for controlling a second precision delay circuit in the delay output circuit to start working;
and after the second precision delay circuit is started, outputting high voltage according to second delay time delay for controlling the optical module to be electrified.
Further, the control method further includes a power-down control step, which includes:
when the delay output circuit receives the optical module non-bit signal, outputting a low level for controlling the optical module to be powered down;
when the optical module is powered down, the optical module configuration circuit pulls down the optical module reset signal and clears a timing register; the timing register is used for timing the power-on time of the optical module.
Further, the control method further includes an upper layer communication control step, which includes:
and when the optical module reset signal is pulled up to meet the third preset time, a register interface in the CPLD sends out optical module readiness notification information to the CPU.
Further, the control method further includes an optical module information management step, which includes accessing and acquiring, by the CPLD, configuration information of the optical module through an integrated circuit bus;
when the optical module is in place and stable, the CPLD reads the voltage and current information of the optical module;
the CPLD judges the compatibility of the optical module;
the CPLD monitors the temperature of the optical module regularly; when the temperature of the optical module is too high, an interrupt signal is sent through an upper layer CPU.
Further, the first preset time is 100ms, and the second preset time is 200ms.
The invention also provides a control device of the optical module, which is used for realizing the control method of the optical module, and comprises a delay output circuit in the CPLD and an optical module configuration circuit in the CPLD;
the delay output circuit is used for: when an on-site signal of the optical module is received, outputting a high level according to a first preset time delay so as to control the optical module to be electrified;
the optical module configuration circuit is used for: and when the power-on time of the optical module reaches a second preset time, pulling up an optical module reset signal so as to control the optical module to be started normally.
The invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the following steps when executing the computer program:
when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the optical module to be started normally.
The present invention further provides a computer readable storage medium storing a computer program which when executed by a processor performs the steps of:
when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the optical module to be started normally.
Compared with the prior art, the technical scheme provided by the invention has the following technical effects:
in the invention, the optical module in the switch system is controlled and managed by the programmed CPLD; in order to improve the stability and reliability of the optical module during hot plug, the optical module is realized through a power-on starting control step;
the programmed CPLD may include a delay output circuit, an optical module configuration circuit;
in the power-on starting control step, when the delay output circuit receives the bit signal of the optical module, the delay output circuit delays to output a high level according to a first preset time so as to control the optical module to be powered on;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit pulls up an optical module reset signal so as to control the optical module to be started normally;
therefore, the working state of the optical module can be automatically identified and configured through the CPLD; namely, when the optical module is in place, the optical module is delayed to output high level and is controlled to be electrified; after the power-on is stable, resetting the optical module and controlling the normal starting of the optical module; the CPLD delay control is used to improve the control precision and response efficiency;
therefore, the CPLD circuit can identify and control the insertion of the optical module and control the power supply of the optical module, so that the safety and reliability of the optical module during operation are ensured;
meanwhile, the management workload of the upper controller CPU of the switch on the optical module can be effectively reduced, and the CPU utilization rate is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flow chart of a control method of an optical module according to a first embodiment of the invention;
fig. 2 is a block diagram of a control device of an optical module in a second embodiment of the present invention;
fig. 3 is an internal structure diagram of a computer device in the second embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
as shown in fig. 1, an embodiment of the present invention provides a control method for an optical module, which is used for controlling and managing the optical module in a switch system through a programmed CPLD, where the control method includes a power-on start control step, and includes:
s21, when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified;
and S22, when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the normal starting of the optical module.
In a specific embodiment, the optical module in the switch system is controlled and managed through the programmed CPLD; in order to improve the stability and reliability of the optical module during hot plug, the optical module is realized through a power-on starting control step;
the programmed CPLD may include a delay output circuit, an optical module configuration circuit;
in the power-on starting control step, when the delay output circuit receives the bit signal of the optical module, the delay output circuit delays to output a high level according to a first preset time so as to control the optical module to be powered on;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit pulls up an optical module reset signal so as to control the optical module to be started normally;
therefore, the working state of the optical module can be automatically identified and configured through the CPLD; namely, when the optical module is in place, the optical module is delayed to output high level and is controlled to be electrified; after the power-on is stable, resetting the optical module and controlling the normal starting of the optical module; the CPLD delay control is used to improve the control precision and response efficiency;
therefore, the CPLD circuit can identify and control the insertion of the optical module and control the power supply of the optical module, so that the safety and reliability of the optical module during operation are ensured;
meanwhile, the management workload of the upper controller CPU of the switch on the optical module can be effectively reduced, and the CPU utilization rate is improved.
In a practical embodiment, the signal of the debounce circuit may be received by a delay output circuit (i.e., a delay circuit); when the bit judgment of the debounce circuit is received, the high level is output after 100ms of delay, and the optical module is controlled to be electrified;
when the optical module is not powered on, the reset signal of the optical module is kept at a low level; and after 200ms of power-on of the optical module, pulling up the reset signal of the optical module to enable the optical module to be started normally.
In practice, the CPU, namely the centralprocessounit, represents the central processing unit; CPLD, complexProgram Logicdevice, represents a programmable logic device; MCU, micro ControlUnit, stands for microcontroller.
CPLD is an abbreviation for programmable logic device (complexpprogram logic device), which is a digital circuit device used to implement certain logic functions. The CPLD is comprised of one or more programmable logic units (ProgrammableLogicBlocks, PLBs), each PLB typically containing one or more programmable logic gates, flip-flops, and other digital circuit components. By programming the CPLD, these programmable components can be connected together to implement complex digital circuit functions such as counters, state machines, data selectors, etc.
CPLDs are often used in applications requiring low latency, high speed, and reliability, such as communication devices, digital signal processing, controllers, meters, and test equipment. The CPLD can also be used for realizing functions such as protocol conversion, data conversion, time sequence generation and the like.
In order to improve the stability and reliability of the optical module during hot plug, the control method of the optical module automatically realizes the power supply control of the optical module, the working state control of the optical module and the hot plug function, and is realized by a hardware circuit.
Namely, the working state of the optical module is automatically identified and configured through the CPLD circuit. The workload of operating and controlling the optical module by the upper controller (CPU, centralProcessorUnit) of the switch is effectively reduced, and the CPU utilization rate is effectively improved.
The CPLD circuit is used for identifying and controlling the insertion and extraction of the optical module and controlling the power supply of the optical module, so that the safety and reliability of the work of the optical module are ensured, and the usability and flexibility of the system in the operation process are effectively improved.
In a preferred embodiment, the first preset time is 100ms and the second preset time is 200ms.
In a preferred embodiment, the control method further comprises an in-situ monitoring step comprising:
an in-situ monitoring circuit in the S11CPLD monitors in-situ signal pins of the optical module in real time; the jitter removing circuit in the bit monitoring circuit carries out voltage deburring treatment on the bit pin signal on the bit signal pin;
s12, when the deburred on-site pin signal is converted from an off-site state to an on-site state and the on-site state maintains to meet a first preset clock, the on-site monitoring circuit judges that the optical module is on-site and outputs the on-site signal of the optical module to the delay output circuit;
s13, when the deburred on-site pin signal is converted from the on-site state to the off-site state and the off-site state maintains to meet the second preset clock, the on-site monitoring circuit judges that the optical module is not on-site and outputs the optical module off-site signal to the delay output circuit.
In an actual embodiment, in an on-site monitoring circuit of the optical module, the circuit monitors on-site signal pins of the optical module in real time, performs jitter removal processing on input signals of the on-site pins of the optical module, and supplies power to the optical module after the signals subjected to jitter removal processing are connected to a delay output circuit for a period of time.
The judgments of the debounce circuit and the delay circuit are asymmetric to the bit and the non-bit:
when the debounce circuit monitors that an on-site pin signal of the optical module is converted from an on-site state to an off-site state, if the off-site state keeps 3 clocks, judging that the module is off-site;
when the debounce circuit monitors that the bit signal pin of the optical module is changed from an unoccupied state to a bit state and the bit state lasts for 16 clocks, the debounce circuit judges that the optical module is in place.
In a preferred embodiment, S21 specifically includes:
s211, judging whether the maintenance time of the optical module in-place signal meets the first delay time or not when a first precision delay circuit in the delay output circuit receives the optical module in-place signal; if yes, outputting high voltage for controlling a second precision delay circuit in the delay output circuit to start working;
and S212, after the second precision delay circuit is started, outputting high voltage according to the second delay time delay for controlling the power-on of the optical module.
In a practical embodiment, the output of the bit signal is coupled to a delay circuit; in order to save circuit resources, delay circuits with different precision are used for cascading, and the delay circuits with the precision of 100ns are directly connected with the debounce circuit;
when the optical module is in place, the delay circuit starts counting, and outputs high level after 50 clock rising edge clocks; if the debounce circuit determines that the module is not in place during the count, the count is immediately cleared and a low level is output.
The output is connected to another delay circuit of the same type and with different precision, and the delay circuit supplies power to the optical module after 150ms delay.
In a preferred embodiment, the control method further comprises a power-down control step, which includes:
s41, outputting a low level when the delay output circuit receives the optical module non-bit signal, and controlling the optical module to be powered down;
s42, when the optical module is powered down, the optical module configuration circuit pulls down an optical module reset signal and clears a timing register; the timing register is used for timing the power-on time of the optical module.
In a practical embodiment, the delay output circuit (i.e. the delay circuit) receives the signal of the debounce circuit; when the out-of-bit judgment of the debounce circuit is received, the timing register is cleared immediately, and a low level is output to control the optical module to be powered down.
When the optical module is not powered on, the reset signal of the optical module is kept at a low level; after 200ms of the optical module is electrified, the reset signal of the optical module is pulled up, so that the optical module is started normally; and when the circuit stops the power supply of the optical module, the reset signal of the optical module is pulled down, and the timing register is cleared.
In a preferred embodiment, the control method further includes an upper layer communication control step including:
and S3, when the reset signal of the optical module is pulled up to meet the third preset time, a register interface in the CPLD sends out the readiness notification information of the optical module to the CPU.
In a practical embodiment, in the register interface module, the register interface provides an upper layer Controller (CPU) control light module power supply, reset signal interface. When the reset signal of the optical module is pulled high for 2s, the optical module considers that the MCU in the optical module is started, writes high specific registers and synchronously informs the CPU that the optical module is ready.
In a preferred embodiment, the control method further comprises an optical module information management step comprising at least one of:
the CPLD accesses and acquires configuration information of the optical module through the integrated circuit bus;
when the optical module is in place and stable, the CPLD reads the voltage and current information of the optical module;
CPLD judges the compatibility of the optical module;
CPLD monitors the temperature of the optical module regularly; when the temperature of the optical module is too high, an interrupt signal is sent through an upper layer CPU.
In a practical embodiment, the circuit can also acquire more relevant information about the optical module through i2c access; after the optical module is in place and stable, the voltage and current information of the optical module is read, the compatibility of the optical module is judged, the temperature of the optical module is monitored regularly, and a CPU sends interruption and the like when the temperature of the optical module is too high.
In a practical embodiment, the control method of the optical module may be implemented by managing a hardware circuit of the optical module, where the management manner includes the following steps:
1. monitoring function: hardware monitors the optical module interrupt signal; and when an interrupt occurs, reporting the signal to an upper processor.
2. Optical module configuration function: the optical module can be reset according to the in-place state of the optical module, and the laser of the optical module can be controlled to emit light.
3. And the hot plug control circuit comprises: the method is used for controlling the safe inserting and extracting operation of the optical module and avoiding damage to the switch system and the optical module.
The main module design of the circuit is as follows:
1) Optical module in-place monitoring circuit
The circuit monitors the in-place signal pin of the optical module in real time, carries out jitter removal processing on the input signal of the in-place pin of the optical module, and supplies power to the optical module after the signal subjected to jitter removal processing is connected into the delay output circuit for a period of time.
The judgments of the debounce circuit and the delay circuit are asymmetric to the bit and the non-bit:
when the debounce circuit monitors that an on-site pin signal of the optical module is converted from an on-site state to an off-site state, if the off-site state keeps 3 clocks, judging that the module is off-site;
when the debounce circuit monitors that the bit signal pin of the optical module is changed from an unoccupied state to a bit state and the bit state lasts for 16 clocks, the debounce circuit judges that the optical module is in place.
The delay output circuit (namely a delay circuit) receives the signal of the debounce circuit; when the bit judgment of the debounce circuit is received, the high level is output after 100ms of delay, and the optical module is controlled to be electrified; when the out-of-bit judgment of the debounce circuit is received, the timing register is cleared immediately, and a low level is output to control the optical module to be powered down.
2) Optical module configuration signal timing
When the optical module is not powered on, the reset signal of the optical module is kept at a low level;
after 200ms of the optical module is electrified, the reset signal of the optical module is pulled up, so that the optical module is started normally;
and when the circuit stops the power supply of the optical module, the reset signal of the optical module is pulled down, and the timing register is cleared.
3) Register interface module
The register interface provides an upper layer Controller (CPU) interface for controlling the power supply and reset signals of the optical module. When the reset signal of the optical module is pulled high for 2s, the optical module considers that the MCU in the optical module is started, writes high specific registers and synchronously informs the CPU that the optical module is ready.
The specific implementation scheme of the debounce circuit and the delay circuit is as follows:
in order to ensure that the on-site information of the optical module is monitored in real time, the clock of an on-site debounce circuit of the optical module is set to be 20ns;
when the continuous sampling of the rising edges of 3 clocks detects that the bit signal of the optical module is high, the anti-shake circuit judges that the optical module is not in place;
when the continuous 16 clock rising edges monitor that the optical module bit signal is low, the jitter removing circuit judges that the optical module is in place.
The output of the bit signal is connected to a delay circuit; in order to save circuit resources, delay circuits with different precision are used for cascading, and the delay circuits with the precision of 100ns are directly connected with the debounce circuit;
when the optical module is in place, the delay circuit starts counting, and outputs high level after 50 clock rising edge clocks; if the debounce circuit determines that the module is not in place during the count, the count is immediately cleared and a low level is output.
The output is connected to another delay circuit with the same type and different precision, and the delay circuit supplies power to the optical module after 150ms delay is realized;
after the optical module is stably powered for 200ms, the reset_n pin of the optical module is pulled up, so that the singlechip of the optical module starts to work; after 2s, the singlechip is considered to be started, and the bit information of the optical module is transmitted to the CPU through a specific register.
In summary, the control method of the optical module provided by the embodiment of the invention has the following advantages:
1) The power-on and power-off processing of the optical module is asymmetric through the jitter removing circuit and the delay circuit;
when the optical module is pulled out, the circuit can timely power down the optical module within 1ms, and the stability of the switch system when the optical module is pulled out is ensured.
The light module is powered for 150ms after being in place and stable, so that the problem of repeated switching power supply can be avoided, and the stability and safety of the light module are ensured.
2) The time sequence control related to the optical module is realized through cascade connection of delay circuits with different precision, and circuit resources are obviously saved while the circuit precision and the system stability are ensured.
3) The CPLD is used for carrying out real-time control and delay control on the related modules, so that the CPU use efficiency in the switch system is improved.
The control method of the optical module has the following beneficial effects:
the hardware circuit is controlled by the stable and reliable optical module, so that the on-site state of the optical module can be monitored in real time;
compared with the traditional MCU directly controlling the optical module, the CPLD circuit can automatically supply power to the optical module and configure related information of the optical module (such as an initialized optical module and the like), so that the upper controller is assisted to complete real-time processing of the simple module, and the use efficiency of the upper controller can be effectively improved.
Compared with the traditional method, the design is more stable in the hot plug function level, and the flexibility and the stability of the switch system are effectively improved.
It should be noted that, the control method of the optical module described above may also be applied to other hot plug modules that require a specific time sequence; the hardware circuit can automatically complete power supply, initial information configuration and state monitoring of the module, and can effectively improve the efficiency and system stability of the processor.
It should be noted that, although the steps in the flowchart are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
Embodiment two:
as shown in fig. 2, the embodiment of the present invention further provides a control device for an optical module, where the control device is configured to implement the foregoing method for controlling an optical module, and the control device includes a delay output circuit in a CPLD and an optical module configuration circuit in the CPLD;
the delay output circuit is used for: when an on-site signal of the optical module is received, outputting a high level according to a first preset time delay so as to control the optical module to be electrified;
the optical module configuration circuit is used for: when the power-on time of the optical module reaches a second preset time, the reset signal of the optical module is pulled high so as to control the optical module to be started normally.
In a preferred embodiment, the control device further comprises an in-place monitoring unit comprising an in-place monitoring circuit in the CPLD;
the in-situ monitoring circuit is used for monitoring in-situ signal pins of the optical module in real time; the jitter removing circuit in the bit monitoring circuit is used for performing voltage deburring on the bit pin signal on the bit signal pin;
when the deburred on-site pin signal is converted from an off-site state to an on-site state and the on-site state maintains to meet a first preset clock, the on-site monitoring circuit is used for judging that the optical module is on-site and outputting the on-site signal of the optical module to the delay output circuit;
when the deburred on-site pin signal is converted from the on-site state to the off-site state and the off-site state maintains to meet the second preset clock, the on-site monitoring circuit is used for judging that the optical module is not on-site and outputting the optical module off-site signal to the delay output circuit.
In a preferred embodiment, the delay output circuit comprises a first precision delay circuit and a second precision delay circuit;
the first precision delay circuit is used for: when an optical module in-place signal is received, judging whether the maintenance time of the optical module in-place signal meets a first delay time or not; if yes, outputting high voltage for controlling a second precision delay circuit in the delay output circuit to start working;
the second precision delay circuit is used for: and after the power-on, outputting high voltage according to the second delay time delay for controlling the power-on of the optical module.
In a preferred embodiment, the control device further comprises a power-down control unit comprising a delay output circuit, an optical module configuration circuit;
the delay output circuit is used for: when the optical module is not in-place signal is received, outputting low level for controlling the optical module to be powered down;
the optical module configuration circuit is used for: when the optical module is powered down, the reset signal of the optical module is pulled down, and the timing register is cleared; the timing register is used for timing the power-on time of the optical module.
In a preferred embodiment, the control device further comprises an upper layer communication control unit comprising a register interface in the CPLD; the register interface is used for:
and when the reset signal of the optical module is pulled up to meet the third preset time, sending out the readiness notification information of the optical module to the CPU.
In a preferred embodiment, the control device further comprises an optical module information management unit for at least one of:
the CPLD accesses and acquires configuration information of the optical module through the integrated circuit bus;
when the optical module is in place and stable, the CPLD reads the voltage and current information of the optical module;
CPLD judges the compatibility of the optical module;
CPLD monitors the temperature of the optical module regularly; when the temperature of the optical module is too high, an interrupt signal is sent through an upper layer CPU.
For specific limitations of the above apparatus, reference may be made to the limitations of the method described above, which are not repeated here.
Each of the modules in the above apparatus may be implemented in whole or in part by software, hardware, and combinations thereof. The above modules may be embedded in hardware, or may be independent of a processor in the computer device, or may be stored in software in a memory in the computer device, so that the processor may call and execute operations corresponding to the above modules.
The computer device may be a terminal, as shown in fig. 3, which includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
It is to be understood that the structures shown in the above figures are merely block diagrams of some of the structures associated with the present invention and are not limiting of the computer devices to which the present invention may be applied, and that a particular computer device may include more or less components than those shown, or may combine some of the components, or have a different arrangement of components.
Implementation of all or part of the flow in the above-described embodiment methods may be accomplished by a computer program that instructs related hardware, and the computer program may be stored in a non-volatile computer readable storage medium, and the computer program may include the flow in the above-described embodiment methods when executed.
Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
It should be noted that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. The control method of the optical module is characterized by being used for controlling and managing the optical module in the switch system through the programmed CPLD, and comprises a power-on starting control step, which comprises the following steps:
when a delay output circuit in the CPLD receives an optical module bit signal, outputting a high level according to a first preset time delay for controlling the optical module to be electrified;
when the power-on time of the optical module reaches a second preset time, the optical module configuration circuit in the CPLD pulls up an optical module reset signal for controlling the optical module to be started normally.
2. The method of controlling an optical module according to claim 1, further comprising an in-situ monitoring step comprising:
an in-place monitoring circuit in the CPLD monitors in real time an in-place signal pin of the optical module; the jitter removing circuit in the bit monitoring circuit carries out voltage deburring on the bit pin signal on the bit signal pin;
when the deburred on-site pin signal is converted from an off-site state to an on-site state and the on-site state maintains to meet a first preset clock, the on-site monitoring circuit judges that the optical module is on-site and outputs the on-site signal of the optical module to the delay output circuit;
when the deburred on-site pin signal is converted from the on-site state to the off-site state and the off-site state maintains to meet the second preset clock, the on-site monitoring circuit judges that the optical module is not on-site and outputs the optical module off-site signal to the delay output circuit.
3. The method for controlling an optical module according to claim 1 or 2, wherein when the delay output circuit in the CPLD receives the bit signal of the optical module, the delay output circuit outputs a high level according to a first preset time delay, comprising:
when a first precision delay circuit in the delay output circuit receives an optical module in-place signal, judging whether the maintenance time of the optical module in-place signal meets a first delay time; if yes, outputting high voltage for controlling a second precision delay circuit in the delay output circuit to start working;
and after the second precision delay circuit is started, outputting high voltage according to second delay time delay for controlling the optical module to be electrified.
4. A control method of a light module as recited in claim 3, further comprising a power-down control step comprising:
when the delay output circuit receives the optical module non-bit signal, outputting a low level for controlling the optical module to be powered down;
when the optical module is powered down, the optical module configuration circuit pulls down the optical module reset signal and clears a timing register; the timing register is used for timing the power-on time of the optical module.
5. The control method of an optical module according to claim 4, further comprising an upper layer communication control step of:
and when the optical module reset signal is pulled up to meet the third preset time, a register interface in the CPLD sends out optical module readiness notification information to the CPU.
6. The control method of an optical module according to claim 1, further comprising an optical module information management step including at least one of:
the CPLD accesses and acquires configuration information of the optical module through an integrated circuit bus;
when the optical module is in place and stable, the CPLD reads the voltage and current information of the optical module;
the CPLD judges the compatibility of the optical module;
the CPLD monitors the temperature of the optical module regularly; when the temperature of the optical module is too high, an interrupt signal is sent through an upper layer CPU.
7. The method according to claim 1, wherein the first preset time is 100ms and the second preset time is 200ms.
8. A control device of an optical module, characterized in that it is configured to implement the control method of an optical module according to any one of claims 1 to 7, the control device comprising a delay output circuit in the CPLD, an optical module configuration circuit in the CPLD;
the delay output circuit is used for: when an on-site signal of the optical module is received, outputting a high level according to a first preset time delay so as to control the optical module to be electrified;
the optical module configuration circuit is used for: and when the power-on time of the optical module reaches a second preset time, pulling up an optical module reset signal so as to control the optical module to be started normally.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of controlling an optical module according to any one of claims 1-7 when the computer program is executed.
10. A computer-readable storage medium storing a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the control method of an optical module according to any one of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310535313.6A CN116546352A (en) | 2023-05-12 | 2023-05-12 | Control method and control device of optical module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310535313.6A CN116546352A (en) | 2023-05-12 | 2023-05-12 | Control method and control device of optical module |
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| CN116546352A true CN116546352A (en) | 2023-08-04 |
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| CN202310535313.6A Pending CN116546352A (en) | 2023-05-12 | 2023-05-12 | Control method and control device of optical module |
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