CN116543716A

CN116543716A - Display panel driving method, common voltage output circuit and display panel

Info

Publication number: CN116543716A
Application number: CN202310366112.8A
Authority: CN
Inventors: 蒋勇杰; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-08-04

Abstract

The application discloses a display panel's drive method, public voltage output circuit and display panel, display panel's drive method includes: receiving a starting signal, and controlling the first switch to be in a closed state; the first common electrode is controlled not to be electrified through the first switch, and the pixel unit is coupled with the second common electrode to achieve the same voltage as the second common electrode; in response to receiving the first frame synchronization signal, the control module outputs a high level, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, the control power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit. According to the display device, the first common electrode, the second common electrode and the input voltage of the pixel unit are controlled in a differentiated mode through the first switch and the second switch, so that when the display device is started, the display panel displays normally, and the display is not white and does not flash.

Description

Display panel driving method, common voltage output circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a driving method of a display panel.

Background

A liquid crystal display is one of the most widely used flat panel displays. A liquid crystal display generally includes a liquid crystal layer disposed between two substrates, and displays an image by adjusting a state of the liquid crystal layer according to a magnitude of an electric field applied to the liquid crystal layer, thereby adjusting transmission of light. With the popularization of large-size panels at present, the panel has a relatively large number of problems that regional white screen or splash screen phenomenon occurs at the far end at the moment of starting.

Disclosure of Invention

In view of this, the present application provides a driving method of a display panel, a common voltage output circuit and a display panel, so as to solve the problem that in the prior art, a region white screen or a splash screen appears at a far end at the moment of starting.

In order to solve the technical problem, the first technical scheme provided by the application is as follows: provided is a driving method of a display panel, including: receiving a starting signal, and controlling the first switch to be in a closed state; the first switch is used for controlling the first common electrode not to be electrified, and the pixel unit is coupled with the second common electrode so as to achieve the same voltage as the second common electrode; in response to receiving a first frame synchronization signal, the control module outputs a high level, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, the control power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit.

Optionally, the controlling the power output line to input a first voltage higher than the coupling voltage to the pixel unit includes: the power supply output line is controlled to input a first voltage higher than the coupling voltage to the pixel unit in a period of one frame of picture.

Optionally, the time of the frame of picture is obtained by a ratio of unit time to the operating frequency.

Optionally, the control module outputs a high level in response to receiving a first frame synchronization signal, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, controlling the power supply output line to input a first voltage higher than the coupling voltage to the pixel unit includes: the control module outputs a high level and controls a power output line to input a first voltage to the pixel unit, so that the voltage difference between the voltage of the pixel unit and the voltage of the second common electrode is less than or equal to 1.5V.

Optionally, the control module outputs a high level in response to receiving a first frame synchronization signal, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, after the control power supply output line inputs the first voltage higher than the coupling voltage to the pixel unit, the control power supply output line comprises: in response to receiving a second frame synchronization signal, the control module controls the power output line to input display screen voltage to the pixel unit; wherein the display screen voltage is higher than the first voltage.

Optionally, the controlling the first common electrode to be unpowered through the first switch, and the pixel unit to reach the same voltage as the second common electrode through coupling with the second common electrode, includes: controlling the first public electrode to be electrified and controlling the second public electrode to be electrified at the same time of controlling the first public electrode not to be electrified; controlling a second switch to be opened, and conducting the first public electrode and the second public electrode; and in response to the first common electrode reaching a target potential, controlling the second switch to be opened so as to enable the first common electrode to stop being electrified.

In order to solve the technical problem, the second technical scheme provided by the application is as follows: there is provided a common voltage output circuit for a display panel, including: the liquid crystal display device comprises a public electrode and a control switch, wherein the public electrode comprises a first public electrode and a second public electrode, and the first public electrode and the second public electrode are matched to form a voltage for driving liquid crystal molecules to deflect; the control switch is arranged between the first public electrode and the second public electrode and is used for switching on or switching off the electric connection of the first public electrode and the second public electrode; wherein, the control switch includes: the grid electrode, the source electrode and the drain electrode are electrically connected with the second common electrode; the source electrode is electrically connected with the first common electrode; the drain electrode is connected to the second common electrode through an equivalent resistance, and a voltage difference is maintained between the gate electrode and the drain electrode through the equivalent resistance.

Optionally, the circuit further comprises: the thin film transistor switch is electrically connected with the power output line and used for controlling the output voltage of the power output line; the liquid crystal capacitor is arranged between the thin film transistor switch and the second common electrode and is used for driving the liquid crystal molecules to deflect; and the storage capacitor is electrically connected with the liquid crystal capacitor and the thin film transistor switch and is used for charging the liquid crystal capacitor so as to keep the electric quantity of the liquid crystal capacitor.

Optionally, the control switch and the thin film transistor switch are both MOS transistors.

In order to solve the technical problem, a third technical scheme provided by the application is as follows: a display panel is provided that is electrically connected to the common voltage output circuit of any one of the above.

The beneficial effects of this application: unlike the prior art, the driving method of the display panel of the present application includes: receiving a starting signal, and controlling the first switch to be in a closed state; the first switch is used for controlling the first common electrode not to be electrified, and the pixel unit is coupled with the second common electrode so as to achieve the same voltage as the second common electrode; in response to receiving a first frame synchronization signal, the control module outputs a high level, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, the control power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit. According to the method and the device, when the first frame synchronizing signal and the second frame synchronizing signal are received at the moment of starting, the input voltages of the first public electrode, the second public electrode and the pixel unit are controlled in a differentiated mode through the first switch and the second switch, so that the display panel can normally display when the device is started, and the display blushing and the screen flashing cannot occur.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic block diagram of a main module structure of a common voltage output circuit provided in the present application;

FIG. 2 is a schematic diagram of a display panel provided herein;

FIG. 3 is a schematic circuit diagram of a common voltage output circuit provided in the present application;

fig. 4 is a schematic structural diagram of a display device provided in the present application;

FIG. 5 is a schematic block diagram of a method of driving a display panel provided herein;

FIG. 6 is a schematic block flow diagram of a sub-step of step S2 provided in FIG. 5;

FIG. 7 is a schematic block flow diagram of a sub-step of step S3 provided in FIG. 5;

FIG. 8 is a power-on timing diagram provided herein;

FIG. 9 is a schematic block diagram of the flow of steps subsequent to step S3 provided in FIG. 5;

fig. 10 is a schematic diagram of a case where an area white screen appears at the far end at the start-up instant of a large-size panel provided in the present application;

reference numerals illustrate:

10-common electrode, 101-whitening area, 11-first common electrode, 12-second common electrode, 13-frame signal line, 14-scan line, 15-power output line, 20-driving module, 30-power management integrated circuit, 40-control module, 50-level conversion module, 60-liquid crystal capacitor, 61-storage capacitor, 70-array substrate, 71-pixel unit, 711-sub-pixel, 72-thin film transistor, 80-color film substrate, 90-liquid crystal layer, 91-liquid crystal molecule, Q1-thin film transistor switch/first switch, Q2-control switch/second switch, R1-equivalent resistor, 100-common voltage output circuit, 200-display panel, 400-display device.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The terms "first," "second," and the like, herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "first", "second", or "first" may include at least one such feature, either explicitly or implicitly. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The inventors of the present application found that: the problem of regional white screen appears at the far end in the starting moment, and the television complete machine can solve the white screen problem by delaying the starting of backlight. However, at present, in the early test or detection of the panel manufacturer/complete machine manufacturer, no special backlight exists, so that the phenomenon of starting up a white screen is observed, and the test/detection is affected. Meanwhile, the inventor discovers that: the reason for the occurrence of the power-on white screen is that at the power-on instant, the scan line (Gate) and the power output line s_out are in the off state, and the a_com common electrode and the cf_com common electrode are simultaneously powered on. But for display panel design reasons CF _ COM at the near and far ends of the panel can reach the target value almost simultaneously. But a_com is connected by a transparent conductive layer (e.g. ITO) in the panel, the impedance is large, the near end can reach the target value quickly, and the far end is slower to power up due to the impedance.

As shown in fig. 10, the Pixel unit (Pixel) at the far end is powered up slowly under the combined action of the a_com and the cf_com, and in this process, the cf_com and the Pixel unit have a voltage difference, so that the liquid crystal molecules rotate to display blushing. When the scanning line is turned on, the power output line normally charges the pixel unit, and the abnormality disappears.

In order to solve the above problems, the present application provides a driving method of a display panel, a common voltage output circuit and a display panel.

Referring to fig. 1 and 10, fig. 1 is a schematic block diagram of a main module structure of a common voltage output circuit provided in the present application, and fig. 10 is a schematic diagram of a situation that a regional white screen appears at a far end at a start-up instant of a large-size panel provided in the present application.

The common voltage output circuit 100 provided in the present application may be used for the display panel 200, where the common voltage output circuit 100 includes a level conversion module 50, a control module 40, a Power Management Integrated Circuit (PMIC) 30, and a driving module 20, and the level conversion module 50 may be separately disposed on a driving circuit board or may be integrated in the driving module 20, for example, the driving module 20 may be a Gamma IC (Gamma chip).

Referring to fig. 2 and 3, fig. 2 is a schematic diagram of a structure of a display panel provided in the present application, and fig. 3 is a schematic diagram of a circuit structure of a common voltage output circuit provided in the present application.

As shown in fig. 2 and 3, the display panel 200 includes a common electrode 10, an array substrate 70, a color film substrate 80, a liquid crystal layer 90, and scan lines (Gate lines) 14, data lines (Data lines, not shown), and power output lines 15; the scan lines 14 and the data lines intersect each other laterally and longitudinally to form a plurality of defined regions. The array substrate 70 includes a plurality of pixel cells 71 and a plurality of Thin Film Transistors (TFTs) 72, the TFTs 72 are located in a defined area, and the TFTs 72 include a gate electrode, a source electrode, and a drain electrode, wherein the drain electrode is electrically connected to the pixel cells 71, and the source electrode is electrically connected to a data line. The liquid crystal layer 90 includes a plurality of liquid crystal molecules 91. Referring to fig. 3, the display panel 200 includes a plurality of subpixels 711 arranged in an array, and the subpixels 711 may be R (red), G (green), and B (blue) subpixels. The data line is electrically connected to the pixel unit 71 through the thin film transistor 72 for charging the storage capacitor 61.

As shown in fig. 3, the common voltage output circuit 100 further includes a common electrode 10, a thin film transistor switch Q1, a liquid crystal capacitor 60, a storage capacitor 61, and a control switch Q2. The common electrode 10 includes a first common electrode 11 and a second common electrode 12, and the first common electrode 11 and the second common electrode 12 cooperate to form a voltage for driving the liquid crystal molecules 91 to deflect, for example, a voltage difference between the first common electrode 11 and the second common electrode 12 determines a deflection angle of the liquid crystal molecules 91. In this embodiment, the first common electrode 11 may be a substrate common electrode (a_com), and the second common electrode 12 may be a common electrode layer (cf_com) on the color film substrate 80. The driving module 20 is configured to transmit a gate driving signal to the plurality of scan lines 14 of the display panel 200 under the control of the gate clock signal to turn on the thin film transistors 72 so that the data voltage signals of the data lines are written into the pixel units 71. In this way, a voltage difference is formed between the pixel unit 71 and the common electrode 10, so that the liquid crystal of the display panel 200 is driven to deflect, and different pictures are displayed.

The control module 40 is electrically connected to the frame signal line 13 (STV line) and the gate clock signal line (not shown), respectively, and is configured to supply a first frame signal (STV signal) to the frame signal line 13 and a gate clock signal to the gate clock signal line.

The control module 40 may include a Timing Controller (TCON); the driving module 20 may include a DC/DC (direct current/direct current) converter, or may further include a P-Gamma IC (programmable Gamma chip). If the driving module 20 includes a P-Gamma IC, the level shifter 50 may be integrated into the P-Gamma IC.

As shown in fig. 3, the thin film transistor switch Q1 is electrically connected to the scan line 14, the liquid crystal capacitor 60, and the power output line 15 for controlling the output voltage of the power output line 15. For example, the thin film transistor switch Q1 controls the specific voltage value output from the power output line 15, and controls whether the power output line 15 outputs a high voltage or a low voltage.

The liquid crystal capacitor 60 is disposed between the thin film transistor switch Q1 and the second common electrode 12, and is used for driving the liquid crystal molecules 91 to deflect. The liquid crystal capacitor 60 serves as a driving mechanism for the liquid crystal molecules 91, and drives the liquid crystal molecules 91 to deflect by a corresponding angle according to the value of the voltage difference between the first common electrode 11 and the second common electrode 12.

The storage capacitor 61 is electrically connected to the liquid crystal capacitor 60 and the tft switch Q1, and the storage capacitor 61 is a capacitor storage structure having a storage capacity far greater than that of the liquid crystal capacitor 60, and is used to charge the liquid crystal capacitor 60 when the liquid crystal capacitor 60 is not powered, so as to maintain the electric quantity of the liquid crystal capacitor 60.

The control switch Q2 is disposed between the first common electrode 11 and the second common electrode 12 for turning on or off the electrical connection of the first common electrode 11 and the second common electrode 12. The control switch Q2 includes a gate electrode electrically connected to the second common electrode 12, a source electrode electrically connected to the first common electrode 11, and a drain electrode. The drain electrode is connected to the second common electrode 12 through the equivalent resistor R1, and a voltage difference is maintained between the gate electrode and the drain electrode through the equivalent resistor R1. The equivalent resistor R1 is a bias resistor, which can keep a voltage difference between the gate and the drain of the control switch Q2, and when the control switch Q2 is in an on state, the first common electrode 11 and the second common electrode 12 can be in an on state, so that a voltage difference is generated between the liquid crystal capacitor 60 connected to the thin film transistor switch Q1 and the second common electrode 12, and the liquid crystal molecules 91 are driven to deflect.

In this embodiment, the control switch Q2 and the thin film transistor switch Q1 are both MOS (metal) -oxide-semiconductor (semiconductor) field effect transistors, and the MOS has a very high switching frequency, so that the MOS can be turned on quickly when receiving an on signal.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a display device provided in the present application.

The application also discloses a display panel 200, which is used for the display device 400, the display panel 200 is electrically connected with the public voltage output circuit 100 described in any one of the above, the display panel 200 is electrically connected with the driving module 20 and the level conversion module 50, and the specific structure of the driving module 20 and the level conversion module 50 and the specific connection manner with the display panel 200 can refer to the foregoing. The display panel 200 may be an LCD (Liquid Crystal Display ), and the display device 400 may be an LCD display device, for example: ADS (Advanced Super Dimension Switch, advanced super-dimensional field switching) liquid crystal display devices; alternatively, the display device 400 may be any product or component having a display function, such as a television, a digital camera, a mobile phone, and a tablet computer. The display device 400 can solve the problem of poor white flash caused by the fact that the common voltage signal is started earlier than the grid driving signal in the related art; meanwhile, the problem of bad black lines caused by GOA noise reduction action in the flashing period in the related technology can be solved; the method has the characteristics of high product quality and good user experience.

Referring to fig. 5, fig. 5 is a schematic block flow diagram of a driving method of a display panel provided in the present application.

The driving method of the display panel 200 provided in the present application may include:

s1: and receiving a starting signal, and controlling the first switch Q1 to be in a closed state.

Specifically, at the moment of starting up, the control module 40 receives the starting-up signal and controls the first switch Q1 to be in the off state continuously, so that the first common electrode 11 is not powered on, and the signal of the first common electrode 11 cannot be input into the display panel 200. In this embodiment, the first switch Q1 is a thin film transistor switch, specifically may be an N-MOS transistor, where the MOS transistor has a very high switching frequency, and the first switch Q1 may be controlled to be turned on or off rapidly as required.

S2: the first common electrode 11 is controlled not to be powered up by the first switch Q1, and the pixel unit 71 is coupled to the second common electrode 12 to reach the same voltage as the second common electrode 12.

Specifically, the control module 40 controls the first switch Q1 to be in the off state, so that the first common electrode 11 is not powered on when the first switch Q1 is in the off state, that is, the a_com cannot input a signal into the display panel 200 due to the off state of the first switch Q1. At this time, the pixel unit 71 in the display panel 200 may reach the same voltage value as the second common electrode 12, for example, 7V in fig. 3, under the coupling of the second common electrode 12. I.e., the voltage difference between the pixel unit 71 and cf_com is made zero, so that the display panel 200 does not display.

Referring to fig. 6, fig. 6 is a schematic block flow diagram of a sub-step of step S2 provided in fig. 5.

Further, the step S2 of controlling the first common electrode 11 to be unpowered through the first switch Q1 and the pixel unit 71 to reach the same voltage as the second common electrode 12 through coupling with the second common electrode 12 may include:

s21: the first common electrode 11 is controlled not to be powered on, and the second common electrode 12 is controlled to be powered on.

Specifically, at the moment of starting up, the control module 40 controls the second common electrode 12 at the far end of the display panel 200 to be rapidly powered on, and the first common electrode 11 is not powered on due to the impedance of the transparent conductive layer, such as ITO, in the display panel 200. The control module 40 may be a Timing Controller (TCON), by which the first common electrode 11 is controlled not to be powered on and the second common electrode 12 is controlled to be powered on simultaneously.

S22: the second switch Q2 is controlled to be turned on, and the first common electrode 11 is turned on with the second common electrode 12.

Specifically, the second switch Q2 is controlled to be turned on by the timing controller, so that the first public electrode 11 and the second public electrode 12 at the far end are conducted, so that the first public electrode 11 and the second public electrode 12 at the far end and the near end can be electrified almost at the same time, and the situation that the voltage difference between the two ends of the liquid crystal capacitor 60 at the far end is too large to deflect the liquid crystal molecules 91 is avoided. In this embodiment, the second switch Q2 is a control switch Q2, which may be a MOS transistor.

S23: in response to the first common electrode 11 reaching the target potential, the second switch Q2 is controlled to be turned off so that the first common electrode 11 stops being powered on.

Specifically, the control module 40 determines that the first common electrode 11a_com reaches the target potential, and it can be understood that if the first common electrode 11 does not reach the target potential, the second switch Q2 is kept on, so that the first common electrode 11 and the second common electrode 12 are turned on, and the first common electrode 11 can be continuously powered up until the first common electrode 11 reaches the target potential. If the first common electrode 11 reaches the target potential, the second switch Q2 may be controlled to stop operating by the control module 40. Because the voltage difference between the gate and the source of the second switch Q2MOS transistor is smaller, the second switch Q2 may be controlled to stop working, and at this time, the first common electrode 11 in the display panel 200 is powered by an external common electrode.

Referring to fig. 7 and 8, fig. 7 is a schematic block flow chart of the substeps of step S3 provided in fig. 5, and fig. 8 is a power-on timing chart provided in the present application.

S3: in response to receiving the first frame synchronization signal, the control module 40 outputs a high level such that the first switch Q1 is in an on state and such that the first common electrode 11 is input into the display panel 200; meanwhile, the control power supply output line 15 inputs a first voltage higher than the coupling voltage to the pixel unit 71.

Specifically, when the timing controller receives the first frame synchronization Signal (STV), that is, when the timing controller detects that the timing controller outputs the first STV, a high level is output through the timing controller, so that the first switch Q1 is turned on, and thus the first common electrode 11a_com may be input into the display panel 200. The STV is a clock signal, or may be CK, and the STV or CK may be equivalent to a scan signal (GATE) inside the display panel 200. At this time, the black picture data (data) is output through the timing controller while the timing controller controls the first common electrode 11 to be input into the display panel 200, and the timing controller may input a first voltage, that is, a black picture voltage, to the pixel unit 71 through the power output line 15 (s_out). It can be understood that the black screen voltage is higher than the coupling voltage of the second common electrode 12 and the pixel unit 71. Since the voltage rise of the first common electrode 11 has less influence on the coupling of the pixel unit 71 at this time, the display panel 200 still displays black at this time. When the timing controller TCON sends the first STV signal, the first common electrode 11a_com starts to send signals to the display panel 200, and the first frame data of the timing controller TCON sends a black frame, so as to avoid the condition of screen flashing abnormality when the display panel is started.

As shown in fig. 7, in the present embodiment, the step S3 of controlling the power output line 15 to input the first voltage higher than the coupling voltage to the pixel unit 71 may include:

s31: the control power supply output line 15 inputs a first voltage higher than the coupling voltage to the pixel unit 71 for one frame of picture.

Specifically, when the first voltage higher than the coupling voltage is input to the pixel unit 71 through the power output line 15, the first voltage needs to be input within a period of one frame of the display panel 200, that is, a period of not higher than one frame of the display panel, so that the voltage of the pixel unit 71 is reduced too much to generate white, and the like, and the white-whitening region 101 at the top end of the display panel 200 is avoided. The time of one frame of picture is related to the current operating frequency, and in this embodiment, the time can be obtained by calculating the ratio of unit time to the operating frequency.

In the present embodiment, in response to receiving the first frame synchronization signal, the control module 40 outputs a high level such that the first switch Q1 is in an on state and such that the first common electrode 11 is input into the display panel 200. Meanwhile, the step S3 of controlling the power output line 15 to input a first voltage higher than the coupling voltage to the pixel unit 71 may further include:

s32: the control module 40 outputs a high level and controls the power output line 15 to input a first voltage to the pixel unit 71 such that a voltage difference between the pixel unit 71 and the second common electrode 12 is 1.5V or less.

Specifically, as shown in fig. 8, when the control module 40 outputs a high level and controls the power output line 15 to input the first voltage to the pixel unit 71, it is required to dynamically detect whether the voltage difference between the voltage of the pixel unit 71 and the second common electrode 12 is 1.5V or less. Since the voltage difference between the pixel unit 71 and the second common electrode 12 is greater than 1.5V, the liquid crystal molecules 91 are deflected, thereby whitening the display panel 200. Therefore, when the control module 40 outputs a high level and controls the power output line 15 to input the first voltage to the pixel unit 71, the voltage difference between the voltage of the pixel unit 71 and the voltage of the second common electrode 12 is 1.5V or less, so that the display panel 200 can be prevented from whitening when the first voltage is input.

Referring to fig. 9, fig. 9 is a schematic block flow diagram of steps subsequent to step S3 provided in fig. 5.

In response to receiving the first frame synchronization signal, the control module 40 outputs a high level such that the first switch Q1 is in an on state and such that the first common electrode 11 is input into the display panel 200. Meanwhile, after the step S3 of controlling the power output line 15 to input the first voltage higher than the coupling voltage to the pixel unit 71, it may further include:

s4: in response to receiving the second frame synchronization signal, the control module 40 controls the power output line 15 to input the display screen voltage to the pixel unit 71; wherein the display screen voltage is higher than the first voltage.

Specifically, if the timing control module 40 receives the second frame synchronization signal, the timing control module 40 sends the normal display screen data, and charges the pixel unit 71 by controlling the power output line 15, that is, inputs the voltage of the normal display screen to the pixel unit 71, so that the display panel 200 can display normally.

The driving method of the display panel disclosed by the application comprises the following steps: receiving a starting signal, and controlling the first switch to be in a closed state; the first common electrode is controlled not to be electrified through the first switch, and the pixel unit is coupled with the second common electrode to achieve the same voltage as the second common electrode; in response to receiving the first frame synchronization signal, the control module outputs a high level, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, the control power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit. According to the method and the device, when the first frame synchronizing signal and the second frame synchronizing signal are received at the moment of starting, the input voltages of the first public electrode, the second public electrode and the pixel unit are controlled in a differentiated mode through the first switch and the second switch, so that the display panel can normally display when the device is started, and the display blushing and the screen flashing cannot occur.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.

Claims

1. A driving method of a display panel, comprising:

receiving a starting signal, and controlling the first switch to be in a closed state;

the first switch is used for controlling the first common electrode not to be electrified, and the pixel unit is coupled with the second common electrode so as to achieve the same voltage as the second common electrode;

in response to receiving a first frame synchronization signal, the control module outputs a high level, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, the control power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the control power output line inputs a first voltage higher than a coupling voltage to the pixel unit, including:

the power supply output line is controlled to input a first voltage higher than the coupling voltage to the pixel unit in a period of one frame of picture.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

the time of the frame of picture is obtained by the ratio of unit time to working frequency.

4. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the control module outputs a high level in response to receiving a first frame synchronization signal, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, controlling the power supply output line to input a first voltage higher than the coupling voltage to the pixel unit includes:

the control module outputs a high level and controls a power output line to input a first voltage to the pixel unit, so that the voltage difference between the voltage of the pixel unit and the voltage of the second common electrode is less than or equal to 1.5V.

5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,

the control module outputs a high level in response to receiving a first frame synchronization signal, so that the first switch is in an on state, and the first common electrode is input into the display panel; meanwhile, after the control power supply output line inputs the first voltage higher than the coupling voltage to the pixel unit, the control power supply output line comprises:

in response to receiving a second frame synchronization signal, the control module controls the power output line to input display screen voltage to the pixel unit; wherein the display screen voltage is higher than the first voltage.

6. The method of claim 1, wherein the step of determining the position of the substrate comprises,

the first switch controls the first common electrode not to be electrified, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode, and the method comprises the following steps:

controlling the first public electrode to be electrified and controlling the second public electrode to be electrified at the same time of controlling the first public electrode not to be electrified;

controlling a second switch to be opened, and conducting the first public electrode and the second public electrode;

and in response to the first common electrode reaching a target potential, controlling the second switch to be opened so as to enable the first common electrode to stop being electrified.

7. A common voltage output circuit for a display panel, comprising:

a common electrode comprising: the liquid crystal display device comprises a first public electrode and a second public electrode, wherein the first public electrode and the second public electrode are matched to form a voltage for driving liquid crystal molecules to deflect;

the control switch is arranged between the first public electrode and the second public electrode and is used for conducting or disconnecting the electrical connection of the first public electrode and the second public electrode; wherein, the control switch includes:

a gate electrode electrically connected to the second common electrode;

a source electrode electrically connected to the first common electrode;

and a drain electrode connected to the second common electrode through an equivalent resistance, and maintaining a voltage difference between the gate electrode and the drain electrode through the equivalent resistance.

8. The circuit of claim 7, further comprising:

the thin film transistor switch is electrically connected with the power output line and used for controlling the output voltage of the power output line;

the liquid crystal capacitor is arranged between the thin film transistor switch and the second common electrode and is used for driving the liquid crystal molecules to deflect;

and the storage capacitor is electrically connected with the liquid crystal capacitor and the thin film transistor switch and is used for charging the liquid crystal capacitor so as to keep the electric quantity of the liquid crystal capacitor.

9. The circuit of claim 8, wherein the circuit further comprises a logic circuit,

the control switch and the thin film transistor switch are both MOS transistors.

10. A display panel, characterized in that it is electrically connected to the common voltage output circuit according to any one of the preceding claims 7 to 9.