CN116541335A - Method for distributing serial addresses and electronic equipment - Google Patents
Method for distributing serial addresses and electronic equipment Download PDFInfo
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- CN116541335A CN116541335A CN202310818824.9A CN202310818824A CN116541335A CN 116541335 A CN116541335 A CN 116541335A CN 202310818824 A CN202310818824 A CN 202310818824A CN 116541335 A CN116541335 A CN 116541335A
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- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 2
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides an electronic device for assigning serial addresses, comprising: the system comprises a main board and at least two board cards, wherein the main board comprises three main board interfaces; the board card comprises three input interfaces and three output interfaces; the main board interface is respectively connected with the first sub-interface of the board card; the first input interface of the board card is in virtual connection with the third output interface of the board card; the second input interface of the board card is electrically connected with the first output interface of the board card; the third input interface of the board card is electrically connected with the second output interface of the board card; all the board cards are provided with input interfaces and output interfaces with the same layout, and all the board cards are provided with the same connection relation between the input interfaces and the output interfaces. The invention solves the problem of higher production and management cost of serial board card address allocation in the prior art, and realizes that a plurality of board cards connected in series are provided with automatically allocated addresses through the design of the interfaces and the connection relations of the same configuration on the improved board card.
Description
Technical Field
The present invention relates to the field of electronic devices, and in particular, to a method for allocating serial addresses and an electronic device.
Background
As the design of a systematic device tends to be modularized, a core motherboard needs to communicate with multiple expansion boards, and an i2c bus is one of common communication modes. The same type of expansion board card serially connected on the same bus needs to be allocated with different addresses to realize communication between the core main board and the expansion board card. The current address allocation method for multiple serial expansion boards generally needs to perform hardware distinction setting for the expansion boards of the same type, and has high production and management costs.
Disclosure of Invention
In order to solve the problem of higher production and management costs in serial board card address allocation in the prior art, a first aspect of the present invention provides an electronic device for allocating serial addresses, including:
the main board is provided with a plurality of grooves,
at least two of the boards are provided with a plurality of boards,
wherein the motherboard comprises three motherboard interfaces; the board card comprises three input interfaces and three output interfaces;
the main board interface is respectively connected with the first sub-interfaces of the board card;
the first input interface of the board card is in virtual connection with the third output interface of the board card;
the second input interface of the board card is electrically connected with the first output interface of the board card;
the third input interface of the board card is electrically connected with the second output interface of the board card;
the first input interface, the second input interface and the third input interface are three input interfaces which are sequentially arranged; the first output interface, the second output interface and the third output are three output interfaces corresponding to the positions of the first input interface, the second input interface and the third input interface in sequence;
all the board cards are provided with the input interfaces and the output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces.
In some embodiments, all adjacent boards have the same connection relationship between the input interface and the output interface;
the connection relation between the input interface and the output interface is as follows:
the first output interface of the previous board is electrically connected with the first input interface of the next board;
the second output interface of the previous board is electrically connected with the second input interface of the next board;
the third output interface of the previous board is in virtual connection with the third input interface of the next board.
In some embodiments, the number of cards having different addresses in series does not exceed four.
In some embodiments, the addresses of the boards of the serial of not more than four different addresses are, in order of serial connection with the motherboard, in order of: 000. 001, 011, 111.
In some embodiments, the electronic device for assigning serial addresses further includes a power supply assembly correspondingly connected to each input interface of the board, the power supply assembly including a pull-up resistor and a power source.
In some embodiments, the power supply assembly is configured to:
when the input interface is in virtual connection, the output interface correspondingly connected with the input interface is in high level;
when the input interface is at a low level, the output interface correspondingly connected with the input interface is at a low level;
when the input interface is at a high level, the output interface correspondingly connected with the input interface is at a high level.
In some embodiments, the second input interface of the board is electrically connected to the first output interface of the board through a resistor, the third input interface of the board is electrically connected to the second output interface of the board through a resistor, and the three motherboard interfaces of the motherboard are grounded through resistors.
A second aspect of the present invention provides a method of assigning serial addresses, comprising:
manufacturing a main board and at least two board cards; wherein the motherboard comprises three motherboard interfaces; the board card comprises three input interfaces and three output interfaces; the main board interface is respectively connected with the first sub-interfaces of the board card; the first input interface of the board card is in virtual connection with the third output interface of the board card; the second input interface of the board card is electrically connected with the first output interface of the board card; the third input interface of the board card is electrically connected with the second output interface of the board card; all the board cards are provided with the input interfaces and the output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces;
sequentially connecting the at least two boards with the main board in series;
and supplying power to the main board and at least two board cards, so that the at least two board cards obtain the automatically allocated addresses.
In some embodiments, the method for sequentially connecting the at least two boards to the motherboard in series includes: all adjacent board cards are connected with each other by the same connection relation between the input interface and the output interface; the connection relation between the input interface and the output interface is as follows: the first output interface of the previous board is electrically connected with the first input interface of the next board; the second output interface of the previous board is electrically connected with the second input interface of the next board; the third output interface of the previous board is in virtual connection with the third input interface of the next board.
In some embodiments, at least two boards acquire no more than four addresses automatically allocated, and the order of acquiring the addresses automatically allocated is as follows: 000. 001, 011, 111.
The invention realizes the change of the 3-bit address by setting the consistent electric connection or virtual connection between the interfaces with the same configuration on the board card, so that a plurality of board cards connected on the main board in series with the same design are provided with the automatically allocated addresses. The motherboard of the embodiment does not need to increase ic or interface, and the board card adopts the same design, thereby avoiding the increased cost of multi-version design.
Drawings
FIG. 1 is a schematic diagram of an electronic device for assigning serial addresses according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic diagram of an electronic device for assigning serial addresses according to another exemplary embodiment of the present invention;
FIG. 3 is a schematic diagram of an electronic device for assigning serial addresses according to yet another exemplary embodiment of the present invention;
fig. 4 is a flowchart of a serial address allocation method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first message may also be referred to as a second message, and similarly, a second message may also be referred to as a first message, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
Under the requirement that one main board needs to communicate with each expansion board in service and management level, address allocation used by a plurality of similar i2c devices is one of reasons for increasing production and management costs. In the prior art, i2c mux on the motherboard, such as pca9546, the ic of such i2c switch manages the same type of i2 c. The address of i2c ic is managed by cpld on the extended board card.
However, the connection between the motherboard and the extended board needs to add ic and plural interfaces to the motherboard, which increases the design cost and the pcb area. In addition, the cpld degrees of different versions are required to be defined in a targeted manner, and the expanded board cards of the different cpld versions are required to be managed separately, so that the cost is further increased.
In view of this, the invention provides a serial address allocation method and electronic equipment, which realize automatic allocation of addresses of boards with four or less expansion by designing a set of unified hardware design and connection relations on the boards.
Fig. 1 is a schematic diagram of an electronic device for allocating serial addresses according to an exemplary embodiment of the present invention.
Referring to fig. 1, the electronic device for serial address allocation provided in this embodiment includes a motherboard 0 and two boards: a first board card 1 and a second board card 2.
In the connection of the interfaces, the potential of the interface with floating input is N under the condition that no pull-up resistor is pulled up; the potential of the interface with the floating input is H under the condition that a pull-up resistor is pulled up; the electric potential of the interface of the control board card is serial board card configuration addresses through designing the connection relation of the interfaces of the board card, wherein the electric potential of the interface connected with the electric potential 0 is 0 and G.
The motherboard 0 includes three motherboard interfaces, and the first board card 1 and the second board card 2 each include three input interfaces and three output interfaces.
One end of the three main board interfaces of the main board 0 is connected with the resistor and then grounded, and the other end of the three main board interfaces is respectively connected with three input interfaces of a first board card connected with the resistor in series, and the address of the first board card is 000.
The first board card 1 and the second board card 2 have the same layout of the input interface and the output interface, and all the boards have the same connection relationship between the input interface and the output interface.
The three input interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively as follows: the first input interface, the second input interface and the third input interface. The three output interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the second board card 2 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the second board card 2 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
The connection relation between the input interface and the output interface which are the same in the board card comprises:
the first input interface of the first board card 1 is in virtual connection with the third output interface of the first board card 1, and likewise, the first input interface of the second board card 2 is in virtual connection with the third output interface of the second board card 2.
The second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1, and likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2.
The third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1, and likewise, the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2.
In the power-on state, output pin potentials corresponding to three main board interfaces of the main board are 0, 0 and 0, so that input pin potentials corresponding to three input interfaces of the first board card 1 connected with the main board interface are 0, 0 and 0. Based on the connection relationship, the output pin potential corresponding to the three output interfaces of the first board card 1 is G, G, N. The input pin potentials corresponding to the three input interfaces of the second board card 2 are 0, 0 and 1, and based on the connection relationship, the output pin potentials corresponding to the three output interfaces of the second board card 2 are G, H, N. Thus, the address of the first board 1 based on the expansion of the motherboard is 000, and the address of the second board 2 serial with the first board 1 is 001.
According to the embodiment, the 3-bit address is changed by setting consistent electric connection or virtual connection between the interfaces with the same configuration on the board card, so that a plurality of board cards with the same design and connected in series on the main board can be provided with the automatically allocated addresses. The motherboard of the embodiment does not need to increase ic or interface, and the board card adopts the same design, thereby avoiding the increased cost of multi-version design.
The connection relation between the first board card 1 and the second board card 2 is as follows: the first output interface of the first board card 1 is electrically connected with the first input interface of the second board card 2; the second output interface of the first board card 1 is electrically connected with the second input interface of the second board card 2; the third output interface of the first board card 1 is in virtual connection with the third input interface of the second board card 2.
Based on the connection relationship, three output interfaces with output pin potential of G, G, N of the first board card 1 are sequentially connected with three input interfaces of the second board card 2, so that input pin potential of an input interface of the second board card 2 connected with the output pin potential of the output interface of the first board card 1 is 0, and virtual connection enables potential of an input floating interface to be 1 under the action of a later power supply assembly.
In some embodiments, the power supply component includes a pull-up resistor and a power source. When the input interface is in virtual connection, the output interface correspondingly connected with the input interface is in high level; when the input interface is at a low level, the output interface correspondingly connected with the input interface is at a low level; when the input interface is at a high level, the output interface correspondingly connected with the input interface is at a high level.
It can be understood that the electrical connection between the input interface and the output interface in the board card can be provided with a resistor, and the three main board interfaces of the main board are grounded through the resistor so as to avoid surge current. Specifically, the second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1 through a resistor, and the third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1 through a resistor. Likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2 through a resistor, and the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2 through a resistor.
The board card provided by the embodiment does not need to consider the setting of the i2c address, and adopts a unified design and a connection mode to realize automatic allocation of the address: after any two boards manufactured according to the design are connected to the boards in series, the addresses of the boards are sequentially and fixedly distributed as 000 and 001.
Fig. 2 is a schematic diagram of an electronic device for assigning serial addresses according to another exemplary embodiment of the present invention.
Referring to fig. 2, the electronic device for serial address allocation provided in this embodiment includes a motherboard 0 and three boards: the first board card 1, the second board card 2 and the third board card 3.
In the connection of the interfaces, the potential of the interface with floating input is N under the condition that no pull-up resistor is pulled up; the potential of the interface with the floating input is H under the condition that a pull-up resistor is pulled up; the electric potential of the interface of the control board card is serial board card configuration addresses through designing the connection relation of the interfaces of the board card, wherein the electric potential of the interface connected with the electric potential 0 is 0 and G.
The motherboard 0 includes three motherboard interfaces, and the first board 1, the second board 2, and the third board 3 each include three input interfaces and three output interfaces.
One end of the three main board interfaces of the main board 0 is connected with the resistor and then grounded, and the other end of the three main board interfaces is respectively connected with three input interfaces of a first board card connected with the resistor in series, and the address of the first board card is 000.
The first board card 1, the second board card 2 and the third board card 3 have the input interface and the output interface with the same layout, and all the board cards have the same connection relationship between the input interface and the output interface.
The three input interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively as follows: the first input interface, the second input interface and the third input interface. The three output interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the second board card 2 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the second board card 2 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the third board card 3 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the third board card 3 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
The connection relation between the input interface and the output interface which are the same in the board card comprises:
the first input interface of the first board card 1 is in virtual connection with the third output interface of the first board card 1, and likewise, the first input interface of the second board card 2 is in virtual connection with the third output interface of the second board card 2, and the first input interface of the third board card 3 is in virtual connection with the third output interface of the third board card 3.
The second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1, and likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2, and the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3.
The third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1, and likewise, the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2, and the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3.
In the power-on state, output pin potentials corresponding to three main board interfaces of the main board are 0, 0 and 0, so that input pin potentials corresponding to three input interfaces of the first board card 1 connected with the main board interface are 0, 0 and 0. Based on the connection relationship, the output pin potential corresponding to the three output interfaces of the first board card 1 is G, G, N. The input pin potentials corresponding to the three input interfaces of the second board card 2 are 0, 0 and 1, and based on the connection relationship, the output pin potentials corresponding to the three output interfaces of the second board card 2 are G, H, N. The input pin potentials corresponding to the three input interfaces of the third board card 3 are 0, 1 and 1, and based on the connection relationship, the output pin potential corresponding to the three output interfaces of the third board card 3 is H, H, N. Thus, the address of the first board 1 based on the motherboard expansion is 000, the address of the second board 2 in series with the first board 1 is 001, and the address of the third board 3 in series with the second board 2 is 011.
According to the embodiment, the 3-bit address is changed by setting consistent electric connection or virtual connection between the interfaces with the same configuration on the board card, so that a plurality of board cards with the same design and connected in series on the main board can be provided with the automatically allocated addresses. The motherboard of the embodiment does not need to increase ic or interface, and the board card adopts the same design, thereby avoiding the increased cost of multi-version design.
The first board card 1 and the serial second board card 2, the second board card 2 and the serial third board card 3 keep the consistent connection relation, and the connection relation specifically comprises:
the connection relation between the first board card 1 and the second board card 2 is as follows: the first output interface of the first board card 1 is electrically connected with the first input interface of the second board card 2; the second output interface of the first board card 1 is electrically connected with the second input interface of the second board card 2; the third output interface of the first board card 1 is in virtual connection with the third input interface of the second board card 2.
Likewise, the connection relationship between the second board card 2 and the third board card 3 in series is: the first output interface of the second board card 2 is electrically connected with the first input interface of the third board card 3; the second output interface of the second board card 2 is electrically connected with the second input interface of the third board card 3; the third output interface of the second board card 2 is in virtual connection with the third input interface of the third board card 3.
Based on the connection relationship, three output interfaces with output pin potential of G, G, N of the first board card 1 are sequentially connected with three input interfaces of the second board card 2, so that input pin potential of an input interface of the second board card connected with the output pin potential of the output interface of the first board card 1 is 0, and virtual connection enables potential of an input floating interface to be 1 under the action of a later power supply assembly. The three output interfaces with the output pin potential of G, H, N of the second board card 1 are sequentially connected with the three input interfaces of the third board card 3, so that the input pin potential of the input interface of the third board card 3 connected with the output pin potential of the output interface of the second board card 2 is 0, the input pin potential of the input interface of the third board card 3 connected with the output pin potential of the output interface of the second board card 2 is 1, and the virtual connection enables the input floating interface to have the potential of 1 under the action of a later power supply assembly.
In some embodiments, the power supply component includes a pull-up resistor and a power source. When the input interface is in virtual connection, the output interface correspondingly connected with the input interface is in high level; when the input interface is at a low level, the output interface correspondingly connected with the input interface is at a low level; when the input interface is at a high level, the output interface correspondingly connected with the input interface is at a high level.
It can be understood that the electrical connection between the input interface and the output interface in the board card can be provided with a resistor, and the three main board interfaces of the main board are grounded through the resistor so as to avoid surge current. Specifically, the second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1 through a resistor, and the third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1 through a resistor. Likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2 through a resistor, and the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2 through a resistor. Similarly, the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3 through a resistor, and the third input interface of the third board card 3 is electrically connected with the second output interface of the third board card 3 through a resistor.
The board card provided by the embodiment does not need to consider the setting of the i2c address, and adopts a unified design and a connection mode to realize automatic allocation of the address: after any three boards manufactured according to the design are connected to the boards in series, the addresses of the boards are sequentially and fixedly distributed as 000, 001 and 011.
Fig. 3 is a schematic diagram of an electronic device for assigning serial addresses according to still another exemplary embodiment of the present invention.
Referring to fig. 3, the electronic device for serial address allocation provided in this embodiment includes a motherboard 0 and four boards: the first board card 1, the second board card 2, the third board card 3 and the fourth board card 4.
In the connection of the interfaces, the potential of the interface with floating input is N under the condition that no pull-up resistor is pulled up; the potential of the interface with the floating input is H under the condition that a pull-up resistor is pulled up; the electric potential of the interface of the control board card is serial board card configuration addresses through designing the connection relation of the interfaces of the board card, wherein the electric potential of the interface connected with the electric potential 0 is 0 and G.
The motherboard 0 includes three motherboard interfaces, and the first board card 1, the second board card 2, the third board card 3, and the fourth board card 4 each include three input interfaces and three output interfaces.
One end of the three main board interfaces of the main board 0 is connected with the resistor and then grounded, and the other end of the three main board interfaces is respectively connected with three input interfaces of a first board card connected with the resistor in series, and the address of the first board card is 000.
The first board card 1, the second board card 2, the third board card 3 and the fourth board card 4 are provided with input interfaces and output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces.
The three input interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively as follows: the first input interface, the second input interface and the third input interface. The three output interfaces of the first board card 1 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the second board card 2 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the second board card 2 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the third board card 3 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the third board card 3 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
Similarly, the three input interfaces of the fourth board card 4 sequentially arranged from top to bottom are respectively: the first input interface, the second input interface and the third input interface. The three output interfaces of the fourth board card 4 which are sequentially arranged from top to bottom are respectively: the first output interface, the second output interface and the third output interface.
The connection relation between the input interface and the output interface which are the same in the board card comprises:
the first input interface of the first board card 1 is in virtual connection with the third output interface of the first board card 1, likewise, the first input interface of the second board card 2 is in virtual connection with the third output interface of the second board card 2, the first input interface of the third board card 3 is in virtual connection with the third output interface of the third board card 3, and the first input interface of the fourth board card 4 is in virtual connection with the third output interface of the fourth board card 4.
The second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1, likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2, the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3, and the second input interface of the fourth board card 4 is electrically connected with the first output interface of the fourth board card 4.
The third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1, likewise, the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2, the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3, and the second input interface of the fourth board card 4 is electrically connected with the first output interface of the fourth board card 4.
In the power-on state, output pin potentials corresponding to three main board interfaces of the main board are 0, 0 and 0, so that input pin potentials corresponding to three input interfaces of the first board card 1 connected with the main board interface are 0, 0 and 0. Based on the connection relationship, the output pin potential corresponding to the three output interfaces of the first board card 1 is G, G, N. The input pin potentials corresponding to the three input interfaces of the second board card 2 are 0, 0 and 1, and based on the connection relationship, the output pin potentials corresponding to the three output interfaces of the second board card 2 are G, H, N. The input pin potentials corresponding to the three input interfaces of the third board card 3 are 0, 1 and 1, and based on the connection relationship, the output pin potential corresponding to the three output interfaces of the third board card 3 is H, H, N. The input pin potentials corresponding to the three input interfaces of the fourth board card 4 are 1, 1 and 1, and based on the connection relationship, the output pin potentials corresponding to the three output interfaces of the fourth board card 4 are H, H, N. Thus, the address of the first board 1 based on the motherboard expansion is 000, the address of the second board 2 serial to the first board 1 is 001, the address of the third board 3 serial to the second board 2 is 011, and the address of the fourth board 4 serial to the third board 3 is 111.
According to the embodiment, the 3-bit address is changed by setting consistent electric connection or virtual connection between the interfaces with the same configuration on the board card, so that a plurality of board cards with the same design and connected in series on the main board can be provided with the automatically allocated addresses. The motherboard of the embodiment does not need to increase ic or interface, and the board card adopts the same design, thereby avoiding the increased cost of multi-version design.
The first board card 1 and the serial second board card 2, the second board card 2 and the serial third board card 3 keep the consistent connection relation, and the connection relation specifically comprises:
the connection relation between the first board card 1 and the second board card 2 is as follows: the first output interface of the first board card 1 is electrically connected with the first input interface of the second board card 2; the second output interface of the first board card 1 is electrically connected with the second input interface of the second board card 2; the third output interface of the first board card 1 is in virtual connection with the third input interface of the second board card 2.
Likewise, the connection relationship between the second board card 2 and the third board card 3 in series is: the first output interface of the second board card 2 is electrically connected with the first input interface of the third board card 3; the second output interface of the second board card 2 is electrically connected with the second input interface of the third board card 3; the third output interface of the second board card 2 is in virtual connection with the third input interface of the third board card 3.
Similarly, the connection relationship between the third board card 3 and the serial fourth board card 4 is: the first output interface of the third board card 3 is electrically connected with the first input interface of the fourth board card 4; the second output interface of the third board card 3 is electrically connected with the second input interface of the fourth board card 4; the third output interface of the third board card 3 is in virtual connection with the third input interface of the fourth board card 4.
Based on the connection relationship, three output interfaces with output pin potential of G, G, N of the first board card 1 are sequentially connected with three input interfaces of the second board card 2, so that input pin potential of an input interface of the second board card 2 connected with the output pin potential of the output interface of the first board card 1 is 0, and virtual connection enables potential of an input floating interface to be 1 under the action of a later power supply assembly. The three output interfaces with the output pin potential of the second board card 2 being G, H, N are sequentially connected with the three input interfaces of the third board card 3, so that the input pin potential of the input interface of the third board card 3 connected with the output pin potential of the output interface of the second board card 2 being the ground potential G is 0, the input pin potential of the input interface of the third board card 3 connected with the output pin potential of the output interface of the second board card 2 being the high potential H is 1, and the virtual connection enables the input floating interface to be 1 under the action of a later power supply assembly. The three output interfaces with the output pin potential of H, H, N of the third board card 3 are sequentially connected with the three input interfaces of the fourth board card 4, so that the input pin potential of the input interface of the fourth board card 4 connected with the output pin potential of the output interface of the third board card 1 at the high potential H is 1, and the virtual connection enables the input floating interface to have the potential of 1 under the action of a later power supply assembly.
In some embodiments, the power supply component includes a pull-up resistor and a power source. When the input interface is in virtual connection, the output interface correspondingly connected with the input interface is in high level; when the input interface is at a low level, the output interface correspondingly connected with the input interface is at a low level; when the input interface is at a high level, the output interface correspondingly connected with the input interface is at a high level.
It can be understood that the electrical connection between the input interface and the output interface in the board card can be provided with a resistor, and the three main board interfaces of the main board are grounded through the resistor so as to avoid surge current. Specifically, the second input interface of the first board card 1 is electrically connected with the first output interface of the first board card 1 through a resistor, and the third input interface of the first board card 1 is electrically connected with the second output interface of the first board card 1 through a resistor. Likewise, the second input interface of the second board card 2 is electrically connected with the first output interface of the second board card 2 through a resistor, and the third input interface of the second board card 2 is electrically connected with the second output interface of the second board card 2 through a resistor. Likewise, the second input interface of the third board card 3 is electrically connected with the first output interface of the third board card 3 through a resistor, and the third input interface of the third board card 3 is electrically connected with the second output interface of the third board card 3 through a resistor. Likewise, the second input interface of the fourth board card 4 is electrically connected with the first output interface of the fourth board card 4 through a resistor, and the third input interface of the fourth board card 4 is electrically connected with the second output interface of the fourth board card 4 through a resistor.
The electronic equipment adopting the consistent design of the board cards and the serial address allocation of the consistent connection relationship between the board cards can support automatic allocation of four different addresses at most, and when the number of the board cards exceeds four, the addresses corresponding to the board cards are repeated. The board card provided by the embodiment does not need to consider the setting of the i2c address, and the automatic allocation of the address is realized by adopting a unified design and a connection mode.
In combination with the three embodiments, the invention can support the automatic allocation of addresses of any serial boards not more than four, and the addresses of the serial boards which are sequentially and automatically allocated after the serial connection of any boards not more than four are 000, 001, 011 and 111. When the number of the serial boards is less than four, the addresses of the serial boards are corresponding to the actual number of the boards from front to back in sequence. For example, when the number of serial boards is 2, the addresses automatically allocated in sequence are 000 and 001. For another example, when the number of serial boards is 2, the addresses automatically assigned in sequence are 000, 001, 011.
The above is a specific description of the electronic device for allocating serial addresses provided by the present invention, and the present invention also provides a serial address allocation method corresponding to the foregoing electronic device for allocating serial addresses.
Fig. 4 is a flowchart of a serial address allocation method according to an exemplary embodiment of the present invention, please refer to fig. 4, wherein the serial address allocation method includes:
s401, manufacturing a main board and at least two board cards.
Wherein the motherboard comprises three motherboard interfaces; the board card comprises three input interfaces and three output interfaces; the main board interface is respectively connected with the first sub-interfaces of the board card; the first input interface of the board card is in virtual connection with the third output interface of the board card; the second input interface of the board card is electrically connected with the first output interface of the board card; the third input interface of the board card is electrically connected with the second output interface of the board card; all the board cards are provided with the input interfaces and the output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces;
s402, sequentially connecting at least two boards with the main board in series.
All adjacent board cards are connected with each other by the same connection relation between the input interface and the output interface; the connection relation between the input interface and the output interface is as follows: the first output interface of the previous board is electrically connected with the first input interface of the next board; the second output interface of the previous board is electrically connected with the second input interface of the next board; the third output interface of the previous board is in virtual connection with the third input interface of the next board.
S403, supplying power to the main board and at least two board cards, so that the at least two board cards obtain the automatically allocated addresses.
The method comprises the steps that at least two boards acquire automatic allocation addresses, and the automatic allocation address acquisition sequence is as follows: 000. 001, 011, 111.
The electronic device for allocating serial addresses adopted in this embodiment is consistent with the electronic device for allocating serial addresses provided in any one of the foregoing embodiments, and the principle and technical effects of the electronic device are similar to those of the electronic device for allocating serial addresses provided in any one of the foregoing embodiments, and are not repeated here.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the invention to the precise form disclosed, and any modifications, equivalents, improvements and alternatives falling within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An electronic device for assigning serial addresses, comprising:
the main board is provided with a plurality of grooves,
at least two of the boards are provided with a plurality of boards,
wherein the motherboard comprises three motherboard interfaces; the board card comprises three input interfaces and three output interfaces;
the main board interface is respectively connected with the first sub-interfaces of the board card;
the first input interface of the board card is in virtual connection with the third output interface of the board card;
the second input interface of the board card is electrically connected with the first output interface of the board card;
the third input interface of the board card is electrically connected with the second output interface of the board card;
the first input interface, the second input interface and the third input interface are three input interfaces which are sequentially arranged; the first output interface, the second output interface and the third output are three output interfaces corresponding to the positions of the first input interface, the second input interface and the third input interface in sequence;
all the board cards are provided with the input interfaces and the output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces.
2. The electronic device for assigning serial addresses of claim 1, wherein all adjacent boards have the same connection relationship between input interfaces and output interfaces;
the connection relation between the input interface and the output interface is as follows:
the first output interface of the previous board is electrically connected with the first input interface of the next board;
the second output interface of the previous board is electrically connected with the second input interface of the next board;
the third output interface of the previous board is in virtual connection with the third input interface of the next board.
3. The electronic device of claim 1, wherein the number of boards having different addresses in series is no more than four.
4. The electronic device for assigning serial addresses as claimed in claim 3, wherein the serial addresses of said boards of said serial of not more than four different addresses are, in order of serial connection with said motherboard: 000. 001, 011, 111.
5. The serial address assigned electronic device of claim 2, further comprising a power supply assembly correspondingly connected to each input interface of the board card, the power supply assembly comprising a pull-up resistor and a power supply.
6. The electronic device of claim 5, wherein the power supply component is configured to:
when the input interface is in virtual connection, the output interface correspondingly connected with the input interface is in high level;
when the input interface is at a low level, the output interface correspondingly connected with the input interface is at a low level;
when the input interface is at a high level, the output interface correspondingly connected with the input interface is at a high level.
7. The serial address assigned electronic device of claim 1, wherein the second input interface of the board is electrically connected to the first output interface of the board through a resistor, the third input interface of the board is electrically connected to the second output interface of the board through a resistor, and the three motherboard interfaces of the motherboard are electrically connected to ground through resistors.
8. A method of assigning serial addresses, comprising:
manufacturing a main board and at least two board cards; wherein the motherboard comprises three motherboard interfaces; the board card comprises three input interfaces and three output interfaces; the main board interface is respectively connected with the first sub-interfaces of the board card; the first input interface of the board card is in virtual connection with the third output interface of the board card; the second input interface of the board card is electrically connected with the first output interface of the board card; the third input interface of the board card is electrically connected with the second output interface of the board card; all the board cards are provided with the input interfaces and the output interfaces with the same layout, and all the board cards are internally provided with the same connection relation between the input interfaces and the output interfaces;
sequentially connecting the at least two boards with the main board in series;
and supplying power to the main board and at least two board cards, so that the at least two board cards obtain the automatically allocated addresses.
9. The method for assigning serial addresses of claim 8, wherein the method for serially connecting at least two boards sequentially to the motherboard is: all adjacent board cards are connected with each other by the same connection relation between the input interface and the output interface; the connection relation between the input interface and the output interface is as follows: the first output interface of the previous board is electrically connected with the first input interface of the next board; the second output interface of the previous board is electrically connected with the second input interface of the next board; the third output interface of the previous board is in virtual connection with the third input interface of the next board.
10. The method for assigning serial addresses according to claim 8, wherein at least two boards are made to obtain automatic assigned addresses not more than four, and the order of obtaining automatic assigned addresses is as follows: 000. 001, 011, 111.
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| CN116541335B (en) | 2023-09-19 |
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