CN116540065A - Selection circuit, storage device and circuit selection method - Google Patents
Selection circuit, storage device and circuit selection method Download PDFInfo
- Publication number
- CN116540065A CN116540065A CN202310371943.4A CN202310371943A CN116540065A CN 116540065 A CN116540065 A CN 116540065A CN 202310371943 A CN202310371943 A CN 202310371943A CN 116540065 A CN116540065 A CN 116540065A
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- 238000010187 selection method Methods 0.000 title claims abstract description 8
- 238000012360 testing method Methods 0.000 claims abstract description 30
- 238000011990 functional testing Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 238000003466 welding Methods 0.000 abstract description 3
- 230000006870 function Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a selection circuit, a storage device and a circuit selection method, comprising a first switch circuit, a second switch circuit and a first switching circuit, wherein the first switch circuit receives a first input voltage from a first input end, receives the first voltage from a first node and outputs a first output voltage at a second node; a second switching circuit that receives a second input voltage from the first input terminal, receives the first voltage from the first node, and outputs a second output voltage at the third node; the first node is electrically connected with the chip to be tested, when the first input end inputs high level, the first switch circuit is turned on, the second switch circuit is turned off, and when the first input end inputs low level, the first switch circuit is turned off, and the second switch circuit is turned on. The invention can realize the function of selecting the switch by controlling the level of the first input end, avoid repeated welding of the pins of the chip to be tested, reduce the damage of the pins and effectively improve the testing efficiency and the reliability.
Description
Technical Field
The present invention relates to the field of selection circuits, and more particularly, to a selection circuit, a memory device, and a circuit selection method.
Background
With the rapid development of the chip industry, the complexity of chips is increasing, and in order to ensure the quality of chips, multiple tests are required before shipping to ensure the integrity of the functions. Generally, chip testing includes pin connectivity testing, leakage current testing, DC testing, functional testing, and others, and there are some other specialized tests depending on the functions implemented. The purpose of the chip test is to find out the chip with problems, and meanwhile, the cost can be saved. Currently, the basic flow of chip testing is to design a peripheral circuit according to the test requirement to connect the chip itself and an ATE (automatic test equipment for integrated circuits), develop a program at the same time, program according to the test item, connect to the pins of the chip, give specific excitation conditions, and capture the response of the pins of the chip. For example, an electrical signal, or a specific current, voltage, or voltage waveform, is given, then its response is captured, and based on the test results, a determination is made as to whether the test item passed the test.
In the chip test process, multiple functional tests are sometimes required to be performed on the same pin, so that multiple functional test results are obtained. The existing test method is that pins to be tested are welded with spare resistors on a test board, the spare resistors are connected with corresponding test interfaces, and when different functional tests are carried out, the pins are required to be switched back and forth, so that the welding is switched back and forth, on one hand, the test efficiency is low, and on the other hand, the pins of a chip are easily damaged, and the correctness of the test result is affected.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defects in the prior art, and provide a selection circuit, a storage device and a circuit selection method, which can realize the function of selecting a switch by controlling the level of a first input end, avoid repeated welding of pins of a chip to be tested, reduce pin damage and effectively improve test efficiency and reliability.
In order to solve the above technical problems, the present invention provides a selection circuit for performing different functional tests on the same pin of a chip to be tested, including,
a first switching circuit that receives a first input voltage from a first input terminal, receives the first voltage from a first node, and outputs a first output voltage at a second node;
a second switching circuit that receives a second input voltage from the first input terminal, receives the first voltage from the first node, and outputs a second output voltage at the third node;
the first node is electrically connected with the chip to be tested, when the first input end inputs high level, the first switch circuit is turned on, the second switch circuit is turned off, and when the first input end inputs low level, the first switch circuit is turned off, and the second switch circuit is turned on.
Preferably, the first switch circuit includes a first MOS transistor and a first resistor, where a gate of the first MOS transistor is connected to the first input terminal and receives the first input voltage, a source of the first MOS transistor is connected to the second node, a drain of the first MOS transistor is connected to the first node and receives the first voltage, and the first resistor is disposed between the gate of the first MOS transistor and the first input terminal.
Preferably, the second switch circuit comprises a second MOS tube and a second resistor, wherein a grid electrode of the second MOS tube is connected with the first input end and receives the first input voltage, a source electrode of the second MOS tube is connected with the first node and receives the first voltage, a drain electrode of the second MOS tube is connected with the third node, and the second resistor is arranged between the grid electrode of the second MOS tube and the first input end.
Preferably, the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
Preferably, the first switch circuit includes an NPN triode, a third resistor, wherein a collector of the NPN triode is connected to the first node and receives the first voltage, a base electrode of the NPN triode is connected to the first input terminal and receives the first input voltage, an emitter of the NPN triode is connected to the second node, and the third resistor is disposed between the base electrode of the NPN triode and the first input terminal.
Preferably, the second switching circuit includes a PNP transistor, a fourth resistor, where a collector of the PNP transistor is connected to the first node and receives the first voltage, a base electrode of the PNP transistor is connected to the first input terminal and receives the first input voltage, an emitter of the PNP transistor is connected to the third node, and the fourth resistor is disposed between the base electrode of the PNP transistor and the first input terminal.
Preferably, the display device comprises an indicator light unit, wherein the indicator light unit comprises a light emitting diode unit, the light emitting diode comprises a first diode and a second diode, the first diode is arranged between a first interface and a second node, and the second diode is arranged between a second interface and a third node.
Preferably, the output interface unit comprises a first interface and a second interface, the first interface is electrically connected with the second node, and the second interface is electrically connected with the third node.
Preferably, the power supply control unit is used for outputting high level or low level, and the first input end is connected with the power supply control unit.
Preferably, the power control unit includes an MCU.
The invention also provides a memory device comprising an operating circuit and a memory cell, wherein the operating circuit is configured to operate the memory cell, and the operating circuit comprises a selection circuit as described above.
The invention also provides a circuit selection method for performing different function tests on the same pin of a chip to be tested by using the selection circuit, which comprises the following steps of,
step S1, connecting a pin of a chip to be tested with a first node of the selection circuit;
step S2, a first input end is controlled to input high level, a first switch circuit is a passage, and a second switch circuit is disconnected;
the first input end is controlled to input low level, the second switch circuit is a passage, and the first switch circuit is disconnected.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the selection circuit, the first switch circuit and the second switch circuit are arranged and connected with the first input end at the same time, one pin of a chip to be detected is electrically connected with the first node of the selection circuit, when the first input end inputs high level, the first switch circuit is conducted, the second switch circuit is disconnected, and when the first input end inputs low level, the first switch circuit is disconnected, and the second switch circuit is conducted. Therefore, the level of the first input end can be controlled, so that the function of selecting a switch is realized, the pin of the chip to be tested is prevented from being repeatedly welded, the damage to the pin is reduced, and the testing efficiency and the reliability are effectively improved.
Drawings
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings, in which
Fig. 1 is a schematic circuit diagram of a first embodiment of the present invention.
Fig. 2 is a schematic circuit diagram of a second embodiment of the present invention.
Description of the specification reference numerals: 1. a first input; 100. a first resistor; 2. a first node; 200. a second resistor; 3. a second node; 300. a third resistor; 400. a fourth resistor; 4. a third node; 5. a first interface; 6. and a second interface.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the invention and practice it.
Example 1
Referring to fig. 1-2, the present invention discloses a selection circuit for performing different functional tests on the same pin of a chip under test, including,
a first switching circuit that receives a first input voltage from a first input terminal 1, receives the first voltage from a first node 2, and outputs a first output voltage at a second node 3;
a second switching circuit that receives a second input voltage from the first input terminal 1, receives a first voltage from the first node 2, and outputs a second output voltage at the third node 4;
the first node 2 is electrically connected with a pin of the chip to be tested, when the first input end 1 inputs high level, the first switch circuit is turned on, the second switch circuit is turned off, and when the first input end 1 inputs low level, the first switch circuit is turned off, and the second switch circuit is turned on.
Therefore, it can be known that in the selection circuit to be protected, the first switch circuit and the second switch circuit are connected with the first input end at the same time, one pin of the chip to be detected is electrically connected with the first node of the selection circuit, when the first input end inputs high level, the first switch circuit is conducted, the second switch circuit is disconnected, and when the first input end inputs low level, the first switch circuit is disconnected, and the second switch circuit is conducted. Therefore, the level of the first input end can be controlled, so that the function of selecting a switch is realized, the pin of the chip to be tested is prevented from being repeatedly welded, the damage to the pin is reduced, and the testing efficiency and the reliability are effectively improved.
Specifically, the selection circuit further includes an output interface unit, where the output interface unit includes a first interface 5 and a second interface 6, and the first interface 5 and the second interface 6 are respectively used for performing different functional tests on the chip to be tested. The first interface 5 is electrically connected to the second node 3, and the second interface 6 is electrically connected to the third node 4.
Further, the first switch circuit includes a first MOS transistor Q1 and a first resistor 100, where a gate of the first MOS transistor Q1 is connected to the first input terminal 1 and receives the first input voltage, a source of the first MOS transistor Q1 is connected to the second node 3, a drain of the first MOS transistor Q1 is connected to the first node 2 and receives the first voltage from a pin of the chip to be tested, and the first resistor 100 is disposed between the gate of the first MOS transistor Q1 and the first input terminal 1.
Still further, the second switch circuit includes a second MOS transistor Q2 and a second resistor 200, where a gate of the second MOS transistor Q2 is connected to the first input terminal 1 and receives the first input voltage, a source of the second MOS transistor Q2 is connected to the first node 2 and receives the first voltage from a pin of the chip to be tested, a drain of the second MOS transistor Q2 is connected to the third node 4, and the second resistor 200 is disposed between the gate of the second MOS transistor Q2 and the first input terminal 1.
It should be noted that, the first MOS transistor Q1 is an NMOS transistor, and the second MOS transistor Q2 is a PMOS transistor.
When the first input voltage is at a high level, the NMOS tube is turned on, the PMOS tube is turned off, and the first switch circuit is turned on, so that signals of pins of the chip to be tested are communicated with the first interface 5; when the first input voltage is at a low level, the PMOS tube is turned on, the NMOS tube is turned off, and the second switch circuit is turned on, so that signals of pins of the chip to be tested are communicated with the second interface 6. The switch selection function is realized by controlling the level of the first input end, and the positions of the NMOS tube and the PMOS tube can be exchanged in the same way, and accordingly, the level of the first input end is controlled to be opposite to the level at the moment, so that the switch selection function can be realized.
On the other hand, in another embodiment of the present invention, the first switching circuit includes an NPN triode Q3, a third resistor 300, a collector of the NPN triode Q3 is connected to the first node 2, the first voltage from the pin of the chip to be tested is received, a base electrode of the NPN triode Q3 is connected to the first input terminal 1, the first input voltage is received, an emitter of the NPN triode Q3 is connected to the second node 3, and the third resistor 300 is disposed between the base electrode of the NPN triode Q3 and the first input terminal 1.
Specifically, the second switch circuit further includes a PNP triode Q4 and a fourth resistor 400, where a collector of the PNP triode Q4 is connected to the first node 2 and receives the first voltage from the pin of the chip to be tested, a base electrode of the PNP triode Q4 is connected to the first input terminal and receives the first input voltage, an emitter of the PNP triode Q4 is connected to the third node 4, and the fourth resistor is disposed between the base electrode of the PNP triode and the first input terminal 1.
Thus, when the first input voltage is at a high level, the NPN transistor Q3 is turned on, the PNP transistor Q4 is turned off, and the first switch circuit is turned on, so as to realize that signals of pins of the chip to be tested are communicated with the first interface 5; when the first input voltage is at a low level, the PNP triode Q4 is turned on, and the NPN triode Q3 is turned off, and at this time, the second switch circuit is turned on, so that signals of pins of the chip to be tested are communicated with the second interface 6. The switch selection function is realized by controlling the level of the first input end, and similarly, the positions of the NPN transistor Q3 and the PNP transistor Q4 can be interchanged, and accordingly, the level of the first input end is controlled to be opposite to the level of the first input end, so that the switch selection function can be realized.
In detail, the selection circuit further comprises an indicator light unit, the indicator light unit comprises a light emitting diode unit, the light emitting diode comprises a first diode D1 and a second diode D2, the first diode D1 is arranged between the first interface 5 and the second node 3, and the second diode D2 is arranged between the second interface 5 and the third node 4. It should be noted that the indicator lights of the first diode D1 and the second diode D2 are different in color. In this way, when the first switch circuit is turned on, the first diode D1 is turned on, and when the second switch circuit is turned on, the second diode D2 is turned on, so that a prompt effect can be achieved.
It should be noted that, the selection circuit further includes a power control unit, the power control unit is configured to output a high level or a low level, the first input end is connected to the power control unit, the power control unit includes an MCU, and the level of the first input end is controlled by software control of an MCU pin IO. In addition, the pin is reserved on the test board, and the first input end is connected to the power supply pin (VCC) to realize high level and ground (VDD) to realize low level.
Example 2
The invention also discloses a memory device comprising an operating circuit and a memory cell, wherein the operating circuit is configured to operate the memory cell, and the operating circuit comprises a selection circuit as described above.
Example 3
A method of circuit selection, characterized by: different functional tests are performed on the same pin of the chip to be tested using a selection circuit as described above, the circuit selection method comprising,
step S1, electrically connecting pins of a chip to be tested with a first node of the selection circuit;
step S2, a first input end is controlled to input a high level, a first switch circuit is a passage, a second switch circuit is disconnected, and a first diode is lightened;
the first input end is controlled to input low level, the second switch circuit is a passage, the first switch circuit is opened, and the second diode is lightened.
Further, in the step S2, the method of controlling the first input terminal to input the high level or the low level includes software control connected to the pin IO of the MCU, and in addition, the method can also be implemented by connecting the first input terminal to the power supply pin (VCC) or the ground (VDD).
In summary, in the selection circuit to be protected in the present invention, by providing the first switch circuit and the second switch circuit, the first switch circuit and the second switch circuit are simultaneously connected with the first input terminal, and electrically connect one pin of the chip to be tested with the first node of the selection circuit, when the first input terminal inputs the high level, the first switch circuit is turned on, the second switch circuit is turned off, and when the first input terminal inputs the low level, the first switch circuit is turned off, and the second switch circuit is turned on. Therefore, the level of the first input end can be controlled, so that the function of selecting a switch is realized, the pin of the chip to be tested is prevented from being repeatedly welded, the damage to the pin is reduced, and the testing efficiency and the reliability are effectively improved.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (10)
1. The utility model provides a select circuit for to test the same pin of chip that awaits measuring carries out different functional test which characterized in that: comprising the steps of (a) a step of,
a first switching circuit that receives a first input voltage from a first input terminal, receives the first voltage from a first node, and outputs a first output voltage at a second node;
a second switching circuit that receives a second input voltage from the first input terminal, receives the first voltage from the first node, and outputs a second output voltage at the third node;
the power supply control unit is used for outputting high level or low level, the first input end is connected with the power supply control unit, and the power supply control unit comprises an MCU;
the first node is electrically connected with the chip to be tested, when the first input end inputs high level, the first switch circuit is turned on, the second switch circuit is turned off, and when the first input end inputs low level, the first switch circuit is turned off, and the second switch circuit is turned on.
2. A selection circuit as claimed in claim 1, characterized in that: the first switch circuit comprises a first MOS tube and a first resistor, wherein the grid electrode of the first MOS tube is connected with the first input end and receives the first input voltage, the source electrode of the first MOS tube is connected with the second node, the drain electrode of the first MOS tube is connected with the first node and receives the first voltage, and the first resistor is arranged between the grid electrode of the first MOS tube and the first input end.
3. A selection circuit as claimed in claim 2, characterized in that: the second switch circuit comprises a second MOS tube and a second resistor, wherein the grid electrode of the second MOS tube is connected with the first input end and receives the first input voltage, the source electrode of the second MOS tube is connected with the first node and receives the first voltage, the drain electrode of the second MOS tube is connected with the third node, and the second resistor is arranged between the grid electrode of the second MOS tube and the first input end.
4. A selection circuit according to claim 3, wherein: the first MOS tube is an NMOS tube, and the second MOS tube is a PMOS tube.
5. A selection circuit as claimed in claim 1, characterized in that: the first switch circuit comprises an NPN triode and a third resistor, wherein a collector electrode of the NPN triode is connected with the first node and receives the first voltage, a base electrode of the NPN triode is connected with the first input end and receives the first input voltage, an emitter electrode of the NPN triode is connected with the second node, and the third resistor is arranged between the base electrode of the NPN triode and the first input end.
6. A selection circuit as claimed in claim 5, characterized in that: the second switch circuit comprises a PNP triode and a fourth resistor, wherein a collector electrode of the PNP triode is connected with the first node and receives the first voltage, a base electrode of the PNP triode is connected with the first input end and receives the first input voltage, an emitter electrode of the PNP triode is connected with the third node, and the fourth resistor is arranged between the base electrode of the PNP triode and the first input end.
7. A selection circuit as claimed in claim 1, characterized in that: the LED display device comprises an indicator light unit, wherein the indicator light unit comprises a light emitting diode unit, the light emitting diode unit comprises a first diode and a second diode, the first diode is arranged between a first interface and a second node, and the second diode is arranged between a second interface and a third node.
8. A selection circuit as claimed in claim 1, characterized in that: the output interface unit comprises a first interface and a second interface, the first interface is electrically connected with the second node, and the second interface is electrically connected with the third node.
9. A memory device, characterized by: comprising an operating circuit and a memory cell, wherein the operating circuit is configured to operate the memory cell, the operating circuit comprising a selection circuit according to any of claims 1-8.
10. A method of circuit selection, characterized by: different functional tests are performed on the same pin of the chip under test using a selection circuit according to any one of claims 1-8, said circuit selection method comprising,
step S1, connecting a pin of a chip to be tested with a first node of the selection circuit;
step S2, a first input end is controlled to input high level, a first switch circuit is a passage, and a second switch circuit is disconnected;
the first input end is controlled to input low level, the second switch circuit is a passage, and the first switch circuit is disconnected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310371943.4A CN116540065A (en) | 2023-04-10 | 2023-04-10 | Selection circuit, storage device and circuit selection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310371943.4A CN116540065A (en) | 2023-04-10 | 2023-04-10 | Selection circuit, storage device and circuit selection method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116540065A true CN116540065A (en) | 2023-08-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310371943.4A Pending CN116540065A (en) | 2023-04-10 | 2023-04-10 | Selection circuit, storage device and circuit selection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116540065A (en) |
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2023
- 2023-04-10 CN CN202310371943.4A patent/CN116540065A/en active Pending
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