CN1165381A - High density storage structure - Google Patents
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- CN1165381A CN1165381A CN 96105125 CN96105125A CN1165381A CN 1165381 A CN1165381 A CN 1165381A CN 96105125 CN96105125 CN 96105125 CN 96105125 A CN96105125 A CN 96105125A CN 1165381 A CN1165381 A CN 1165381A
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Abstract
A dynamic random access memory (DRAM) IC has a semiconductor substrate, which has an indentation area on it. Said indentation area has a basically vertical side extended from bottom and a FET is adjacent to the indentation area. A capacitor structure composed of bottom and top capacitor plates and capacitance dielectric is arranged in the area and over the FET, so providing larger surface of capacitor.
Description
The present invention relates to the manufacturing of SIC (semiconductor integrated circuit).Though the present invention constructs explanation as an example with the storage unit of dynamic RAM (DRAM) device, yet, be appreciated that the present invention has applicability widely.For example, the present invention can be applicable to the manufacturing of other semiconductor devices, such as Application Specific Integrated Circuit (ASICs), microprocessor (MICROs), other memory storages etc.
Manufacture view at the DRAM device, the memory capacity of each DRAM storage unit (storage capacity) exists problem always, in the DRAM storage unit, memory capacity is meant and can be stored in the maximum amount of charge in the dielectric material between electrode for capacitors on the electrode for capacitors and.Dielectric surface area between this memory capacity and described capacitance electrode is proportional.Therefore, bigger capacitor surface is long-pending corresponding to bigger memory capacity.
The planar capacitor structural design that the low-density DRAM storage unit that is used for 256Kbit DRAM is to use the about horizontal space plane identical with the triode gate to be constructed.This capacitor arrangement is to form to cover on triode source/drain zone of being limit between a triode gate and an oxide isolation region in the area of space.This planar capacitor structure can provide enough memory capacity to low-density DRAM storage unit effectively.Yet, when the size of DRAM storage unit diminishes because of the device of higher density, the design that in less memory cell size, constitutes the capacitor constructions of the enough memory capacity difficulty that becomes.
A kind of technology in order to the memory storage capabilities that increases this higher density DRAM storage unit is a stacked capacitor.This stacked capacitor makes " top " of its capacitor constructions at this effect triode gate, and not in the plane identical with this gate.Therefore, it is long-pending that this stacked capacitor can increase its capacitor surface by the top that capacitor is formed on this effect triode gate.Yet this capacitor is restricted because of making difficulty.In fact, this stacked capacitor structure makes the DRAM storage unit have extremely complicated concaveconvex shape (topography).This very complicated concaveconvex shape causes the difficulty on the manufacturing technology, thereby causes long time of delivery, lower device productive rate, and higher installation cost.
The technology of the increase high density DRAM memory cell storage memory capacity that another kind is known is ditch formula capacitor (trench capacitor).Being configured to form in the sunk area or " raceway groove " in this DRAM storage unit well region of this ditch formula capacitor.This raceway groove defines the width and the degree of depth through selecting.This raceway groove also comprises a trench sidewalls, comes to determine electrode for capacitors down thus.Cover on this trench sidewalls is this capacitor dielectric.The conductive filling material that covers on this capacitor dielectric is determined electrode for capacitors on this.The increase long-pending along with capacitor surface can get cumulative capacitor stores capacity.
Bigger capacitor surface is relevant with channel design dark or broad on the space.This channel width can't increase basically because of the substrate surface area of each storage unit is limited.So, must increase surface area by adding deep trench.Yet darker raceway groove often is difficult for making exactly because of its high aspect ratio.Restriction on the other hand is the problem that may have " soft error " because of the face that connects the more greatly area that channel design is relevant therewith.Again on the one hand be restricted to the quality that wall doping when making capacitance electrode down can influence capacitor dielectric.
From the above, need a kind of be easy to make, save cost and reliable high density memory cells structure at present.
The invention provides a kind of method and structure of capacitor of the DRAM of manufacturing integrated circuit (IC) apparatus.This capacitor of improving one's methods manufacturing need not form darker raceway groove and can possess bigger surface area.
In a specific embodiments, the invention provides a kind of dynamic RAM (DRAM) integrated circuit.This DRAM integrated circuit has a semiconductor substrate that comprises sunk area.This sunk area has the vertical avris that extends from the bottom surface.One field that comprises active/drain zone is imitated triode and is positioned at this sunk area place and adjacent with it.This DRAM integrated circuit also comprises an insulation course that covers on this sunk area.Provide in addition and one cover on this insulation course, be positioned at the following condenser armature that the triode top is imitated in the part field.This time condenser armature is connected with regions and source.This DRAM integrated circuit also comprises a capacitor dielectric that covers on this time condenser armature, and a last condenser armature that covers this dielectric layer.Described following condenser armature, capacitor dielectric and last condenser armature determine to make this capacitor constructions.
In another embodiment, provide a kind of method that forms the capacitor of dynamic RAM integrated circuit component, this method comprises provides the semiconductor substrate, forms a sunk area in this substrate.This sunk area has the vertical avris that extends from a bottom surface.This method also comprises once determining to cover the insulation course on this sunk area.The another step that is provided is adjacent to the source/drain zone of this sunk area for formation one.This method comprises forming and one covers on this insulation course, is positioned at an a part following electrical equipment of imitating on the triode and holds plate.This time condenser armature is connected with this source/drain zone.This method also comprises the formation one capacitor dielectric that covers on this time condenser armature, and forms a last condenser armature that covers on this dielectric layer.Described following condenser armature, capacitor dielectric and last condenser armature are determined this capacitor constructions.
The bitline configurations that comprises a dynamic RAM integrated circuit in the another embodiment of the present invention.Bitline configurations has a semiconductor substrate that comprises sunk area.This sunk area has the vertical avris that extends from a bottom surface.One fet is through determining to be adjacent to this sunk area.One insulation course covers on this sunk area, and a conductor then is determined in this sunk area.This conductor is connected to this source/drain zone, and determines a bit line.
Another embodiment of the invention comprises the method that forms a bitline configurations in the dynamic RAM integrated circuit.The method comprises to be provided the semiconductor substrate and form a sunk area in this semiconductor substrate.This sunk area has the vertical avris that extends from the bottom surface.This method also comprises and forming once determining covering the insulation course on this sunk area, and forms a step that is adjacent to the fet of this sunk area.One conductor is specified in this sunk area.This conductor is connected to this source/drain zone, and determines a bit line.
With reference to hereinafter describe in detail and accompanying drawing after, should characteristic of the present invention more than you know and advantage.
Fig. 1 is the hasty profile of the DRAM integrated circuit component according to the present invention.
Fig. 2 is the simple sectional drawing of the DARM bitline configurations of Fig. 1;
Fig. 3 is another sectional drawing of Fig. 2 bitline configurations;
Fig. 4 is the simple top view of the DRAM of Fig. 1; And
Fig. 5～14 are for being used for illustrating the simple manufacture method according to DRAM integrated circuit component of the present invention.
The specific embodiment explanation
I. dynamic random access memory means is constructed
Fig. 1 is the simple sectional drawing of DRAM integrated circuit (IC) apparatus 10 of the present invention.This device only for explanation example of the present invention, should not be defined in this with the scope of claim.Generally speaking, this DRAM device 10 comprises a plurality of memory cell region 12, a covering dielectric layer 14, a top metal layer (top metallization layer) 16, one passivation layer 17 and other elements.This memory cell region can be used known CMOS treatment technology to wait and make.
Each memory cell region 12 all is determined in the P type well area 22, imitates triode 18 for one and is determined in this P type well area 22.This imitates triode is a N type channel mos (MOS) device, and it comprises a gate electrode 54.This gate electrode 54 (is called word line; Word line), be covered on the thin brake-pole dielectric layer 52.Sidewall (sidewall) 56 is defined as being adjacent to gate 54 sides.Cover on this gate 54 is a lid oxide layer (cap oxide layer) 58.One inter-level dielectric (inter-layer dielectric) 60 forms to cover on this lid oxide skin(coating) 58, also covers on the source/ drain zone 38,46 of part.Each source/drain zone all comprises a N- type LDD zone 42,48 and a N+ type source/territory, polar region 40,50.As shown in the figure, N+ type source/drain zone 40 is connected to a trench type capacitor (trench capacitor) 20, is determined in this P type well area 22.
This trench type capacitor can be used as a kind of memory storage and uses, and is arranged in the electric charge of the electric capacity dielectric 30 of 28 of condenser armatures 26 and last condenser armature down in order to storage, and this electric capacity dielectric can be any suitable insulating material, such as silicon dioxide, silicon nitride etc.This electric capacity dielectric is preferably an interlayer that comprises silicon dioxide, silicon nitride and silicon dioxide, and it is known oxide-nitride thing-oxide (ox-ide-on-nitride-on-oxide; ONO).Certainly, also can use the combination of other dielectric materials according to its applicability.
This time condenser armature 26 is determined above this effect triode 18, and is covered on the insulation course 24 covering trench bottom 32 and avris 34.The thickness of this insulation course is enough to make this P type well area and following condenser armature 26 to be isolated through selection.High-quality earth silicon material can be made this insulation course to reach the insulation purpose.Yet the part 36 of this insulation course on this raceway groove avris 34 removed, so that electrical contact of regional 40 of this time capacitor 26 and this N+ type source/drain to be provided.
This time condenser armature can be any suitable conductor layer.This time condenser armature is preferably in forming process the polysilicon layer of (in-situ doped) the N type of doping impurity (for example phosphorus etc.).This time condenser armature also can be made the sandwich construction that comprises multi-metal layer, silicide layer and combination thereof etc.In another embodiment, this time condenser armature utilizes one to have polysilicon layer texture or coarse and make.This polysilicon layer (different with level and smooth polysilicon layer) with texture has kick, to increase the effective surface area of capacitor by this.As shown in the figure, the insulation course of this time condenser armature on trench bottom 32 extends, and covers on the insulation course on the raceway groove avris 34, contacts this source/drain zone 40, and extends this inter-level dielectric 60 tops, cover this effect triode 18 on.
Should go up condenser armature 28 covers on this capacitor dielectric 30.Should go up condenser armature and extend, and extend with on the capacitance dielectric layer that covers this time condenser armature from this raceway groove insulation course bottom 32.It is preferably made by the polysilicon layer of doped N-type impurity in forming process to go up condenser armature.Another selectable scheme is that condenser armature also can be made into the sandwich structure that comprises many metal levels, silicide layer and combination thereof etc. on this.Another embodiment uses a kind of by having the made last condenser armature of texture or rough polysilicon layer.This polysilicon layer (different with level and smooth compound crystal silicon layer) with texture has kick, to increase the effective surface area of capacitor by this.
As shown in the figure, condenser armature 26 under the comprising involved in the present invention, electric capacity dielectric 30, and go up the trench type capacitor structure of condenser armature 28, this trench bottom 32 is extended certainly, extends along its avris 34, and extends through this and imitate triode 18 tops.Therefore, can make longer than the known capacitor structure basically trench type capacitor structure.
Trench type capacitor of the present invention is designed to increase electric capacity and does not have a shortcoming of known channel junction structure; Before and after often being difficult for, known channel junction structure is produced on certain consistently more than the degree of depth.For example, when using the design rule of 0.25 μ m, the channel depth scope is from about 8,000 to about 12,000 , and is advisable with about 10,000 .With regard to bit line and insulation layer, this channel width is about 2,500 .With regard to capacitor, this channel width is about about 4,000 scopes.This raceway groove structure is provided with condenser armature.The thickness range of this condenser armature is about 1,000 to about 1,400 , and is advisable with about 1,200 .The following condenser armature that must be noted that a part is to determine to cover on this effect triode and the raceway groove avris.
Fig. 2 is the simplification sectional drawing of the bitline junction structure of DRAM among Fig. 1.Bitline junction structure of the present invention is an illustrated example only, and scope of the present invention should be defined in this.This section Figure 200 comprises: P type well area 22 and gate electrode 54 (or word line).One bit line 204 is formed in the raceway groove 201 with avris and bottom.Described raceway groove has an insulation course, and this insulation course comprises an end insulation course part 203 and one side side insulation layer part 202, covers around it.This insulation course is in order to isolate bit line and P type well area 22.As shown in the figure, this bit line forms in the mode perpendicular to this word line 54, and is used for being connected in each triode source/drain zone of contiguous this bit line.
Particularly, this bit line is connected in the source/drain zone 46 of this effect triode 18.Described connection sees through the contact opening 207 in this avris insulation course part 202 and forms.In other words, the avris insulation course line on the throne of a part is removed before forming, and forms one and be used to make this source/drain zone 46 contact openings that contact with this bit line 204.As use 0.25 μ m design rule (design rule), then this contact A/F is in about 2000 scopes to about 2800 , and is advisable with about 2200 .The degree of depth of this contact opening ties up to the scope of about 2200 to 2800 , and is advisable with about 2500 .
This bit line is made by a conductor material, more preferably be one in forming process the polysilicon layer of doped N-type impurity (for example phosphorus etc.).In addition, this bit line also can borrow the deposit spathic silicon layer to reach by POCl
3Diffusion with realize severe and mix or mat annealing so that implanting ions and forming.This bit line is limited by this channel width and channel depth.Corresponding to this channel depth is this bit line thickness, and it has the bottom insulation part of top insulated part and about 5000 of about 1000 .Certainly, this bit line more can be made by the other materials (such as the combination of Polycide or multiple material) of different size.
Cover on this bit line is a top layer part 205.This top insulated part 205 makes it avoid covering such as on the device elements such as gate electrode in order to isolate this bit line.The insulation course part that comprises this top layer part 205, avris insulation course part 202 and bottom insulation layer segment 203, be used for determining be looped around this bit line around, and in order to make this bit line haply and to be determined to isolate around the P type well area around this raceway groove and other device elements.As shown in the figure, this top layer 205 is connected in this avris insulation course part 202, and this avris insulation course part 202 then is connected in end insulation course part 203.
Fig. 3 is another sectional drawing 300 of Fig. 2 bitline configurations.Sectional drawing is in order to illustrate this bit line 204 via contact opening 207, with being connected of regional 46 of this source/drain.As shown in the figure, this contact opening 207 makes this bit line 204 can be connected to N
+Type source/drain zone 50.This N
+The N that the type source/the drain zone connects near providing
-Therefore the resistance that type LDD zone is lower, help the transmission of electric charge, and wherein this electric charge is that representative is sent to the signal of this bit line 204 by the source/drain zone 46 of storage unit.This bit line 204 occurs in this N with being connected of regional 46 of source/drain
+Type source/50 places, drain zone.
With this contact opening 207 adjacent be this top layer part 205 and avris insulation course part 202A.This top layer part 205 and avris insulation course be 202A partly, is connected to each other avris insulation course part 202 and bottom insulation layer segment.The combination of this kind insulation course part is isolated bit line 204 and abutment means part, but this bit line 204 is connected with the source/drain zone 46 of this triode.Each DRAM storage unit all has this kind bit line connected mode.
Fig. 4 is the simplification top view 400 of DRAM integrated circuit structure of the present invention.This top view only is an illustrated example, and the present invention should be defined in this.This top view shows that one has the matrix of Y direction and directions X.Gate electrode 54 extends on directions X, determines to cover on the P type well area 26.Through vertically being determined at electrode for capacitors 26 under each on the Y direction, be formed on this gate electrode 54 tops.A plurality of bit lines 204 extend along electrode below the gate on the Y direction 54, and perpendicular to this gate electrode 54.Each bit line all comprises a plurality of contacts 207, makes this bit line be connected to the indivedual sources/drain zone of this effect triode.
II. dynamic RAM manufacturing technology
Whole manufacture methods of the present invention are summarized as follows.
(1) provides the semiconductor substrate;
(2) photomask 1: form P type trap in this semiconductor substrate;
(3) photomask 2: form N type trap in this semiconductor substrate;
(4) formation one comprises the protective seam of bed course oxide (pad oxide) layer and silicon nitride layer;
(5) photomask 3: form active region (active area) to determine channel region;
(6) form channel region;
(7) form trench sidewalls and bottom oxidization layer;
(8) photomask 4: determine bit line contact, and remove the photoetching agent;
(9) polysilicon that mixes in the deposition forming process is to fill channel region;
(10) eat-back the polysilicon that mixes in the forming process, so that the polysilicon that mixes in the forming process remains in the raceway groove;
(11) photomask 5: determine zone, road in the non-bit line, and remove the polysilicon that mixes in the forming process in the non-bit line channel region;
(12) polysilicon that mixes in the forming process in the oxidation bit line channel region;
(13) photomask 6: photomask P type passage area and implantation passage stop area (channel stop region) are up to this trench bottom;
(14) deposition boron phosphorus silicate glass (BPSG) is to fill up the channel region in this non-bit line channel region;
(15) remove this protective seam from this active region;
(16) carry out comprehensive critical implantation (blanket threshold implant);
(17) photomask 7: shielding N type well area, and implant p type impurity in this memory cell region (or P type well area) to regulate critical voltage;
(18) form the gate oxide layer;
(19) form gate polysilicon layer or the Polycide (or Poly-1) that mixes;
(20) photomask 8: determine that the gate polysilicon layer is to form gate electrode;
(21) photomask 9: determine slightly mix drain (LDD) zone and implant N type impurity of N type;
(22) photomask 10: determine P type LDD zone and implant p type impurity;
(23) on the avris of polycrystalline silicon gate pole electrode, form sidewall spacers (side-wall spacer);
(24) photomask 11: determine N+ type source/drain zone and implant N+ type impurity;
(25) photomask 12: determine P+ type source/drain zone and implant P+ type impurity;
(26) photomask 13: cover bit line zone and word line regions with the photoetching agent, determine capacitor area;
(27) remove BPSG in the trench type capacitor zone, and remove the photoetching agent;
(28) polysilicon oxide layer in the middle of the deposition;
(29) photomask 14: determine capacitor unit joining zone and etching;
(30) deposition poly-2 layer and doping;
(31) photomask 15: determine the poly-2 layer, to form electrode for capacitors;
(32) form the cell capaciator dielectric;
(33) deposition poly-3 layer and mix (or during forming, make doped p oly-3 deposition);
(34) photomask 16: determine the poly-3 layer, to form electrode for capacitors on;
(35) deposition BPSG/NSG (non-impurity-doped silicate glass), and stream whole (flow);
(36) photomask 17: determine the contact pattern in the BPSG/NSG layer;
(37) sputter the first metal layer;
(38) photomask 18: determine the first metal layer;
(39) deposition intermetallic metal oxide (inter-metal oxide);
(40) photomask 19: determine passage (via) pattern;
(41) sputter second metal level;
(42) photomask 20: determine second metal level;
(43) heavy kind of passivation layer and polyimide coating;
(44) photomask 21: determine routing district (pad region) and fuse (fuse) open area;
(45) polyimide slaking (cure);
(46) the etch passivation floor is to determine the routing district; And
(47) sintering.
These steps provide an improvement capacitor with a shallow channel and stacked capacitor plate.Each condenser armature is all determined in this raceway groove and above the gate electrode part of this effect triode.Therefore, form a bigger capacitance meter area, thereby can improve memory capacity.The present invention also provides the bit line structure that is determined in this raceway groove.This bit line structure is not using under the complex configuration of known technology, is connected in each source/drain zone.These steps are also pure to be the explanation example, thereby the scope of the invention should not be subject to this.Below, with reference to description of drawings this method.
Fig. 5～14 show the simple manufacture method of DRAM integrated circuit (IC) apparatus of the present invention.This method is pure to be the explanation example, thereby scope of the present invention should not be subject to this, and this method is from providing semiconductor substrate 11, as shown in Figure 5.This substrate can be any wafer that integrated circuit (IC) apparatus of the present invention is used that is suitable for making.For example, be used to carry out the manufacturing technology of complementary metal oxide semiconductor (CMOS) (CMOS) device of DRAM memory storage by this wafer.But can use other manufacturing technologies according to its particular utility.
One mask is through determining with on the upper surface that covers this semiconductor substrate, to form P type well area 22.This P type well area 22 be contain P-type material by implantation impurity to this substrate and form.P type impurity comprises boron etc.This mask utilizes known technology to remove.Then, N type lane device can be formed in the P type well area.
N type trap also can be determined in this semiconductor substrate.Specifically, a mask forms with on the P type well area that covers this semiconductor substrate.Utilize an implantation step to form this interior N type well area of this semiconductor substrate.N type impurity comprises as materials such as phosphorus, arsenic.This mask utilizes known technology to remove.Then, P type lane device can be formed in the N type well area.
Dielectric layer combination 501 is determined to cover on this substrate, to form a protective seam, as shown in Figure 5.That is, this protective seam is used as a photo mask layer.This protective seam comprises the silicon nitride layer 505 that a bed course oxide skin(coating) 503 and covers the top.This bed course oxide skin(coating) thickness is 200 to 300 .This silicon nitride layer is that 1200～1800 are thick.This silicon nitride layer 505 also can freely comprise another silicon dioxide layer (not shown) that covers the top.These layers to determine a plurality of channel regions, comprise a capacitor raceway groove 20 and a bit line raceway groove 201, as shown in Figure 6 through planning.
The formation of this capacitor raceway groove 20 and bit line raceway groove 201 is to form with a dry etching technology.One example of dry etching technology can comprise reactive ion etching (re-active ion etching), plasma etching (plasma etching) etc.More known capacitor zanjon, this raceway groove is preferably more shallow, thereby makes consistently easily.As use 0.25 μ m design rule, then this capacitor channel depth scope and is advisable with about 1.0 μ m between about 0.8 to about 1.20.25 μ m.This raceway groove has the width of 0.4 μ m simultaneously.As use same design rule, and then this bit line channel depth can be suitable with this capacitor raceway groove, about 0.8 between the scope of about 1.2 μ m, and approximately to be advisable with 1.0 μ m.This raceway groove has the width of 0.25 μ m simultaneously.Certainly, the degree of depth of each raceway groove and width are decided according to its application.
One dielectric spacer material layer is to be determined in each raceway groove that comprises capacitor raceway groove 20 and bit line raceway groove 201, as shown in Figure 7.Especially, this capacitor raceway groove 20 comprises a dielectric layer 24 that covers on this trench bottom 32 and the raceway groove avris 34.This bit line raceway groove 201 has avris dielectric layer part 202 and the bottom dielectric layer segment 203 that covers respectively on this raceway groove avris and the bottom.The thermal oxide of the preferable footpath of this raceway groove silicon and being covered by an oxide layer.This oxide layer has a thickness that is enough to its covering structure and substrate and the isolation of other device elements.This oxide layer is preferable to have one from about 400 thickness to about 600 scopes, and is advisable with about 500 .But this raceway groove is the technology that is fit to of mat chemical vapour deposition technique (CVD) or other and deposit coating and go up monoxide layer or multiple dielectric layer also.Certainly, this dielectric layer material and thickness thereof are decided according to its application.
Be formed at dielectric layer neutrality line contact in this equipotential line raceway groove and be and utilize photomask and etching technique and determined.This bit line contact is the contact opening 207 in the dielectric layer that is defined as covering on this raceway groove avris.Aspect the embodiment that uses the monoxide dielectric layer, this contact opening is by comprising the upper surface of base plate of raceway groove with photoetching agent coating and making.Draw photoengraving pattern and cover the zone of exposing of these contacts applying laggard professional etiquette with formation, and wet etching this expose the zone to form the step of this bit line contact opening.Each bit line contact open mouth is that 0.25 μ m is wide and 3000 are dark.Then, use known technology to remove this lithography layer.During treatment step after a while, this contact opening provides a passage (via) structure, this bit line is connected to the source/drain zone of each effect triode.
Then, use the polysilicon packed layer 801 that mixes in the forming process to fill this raceway groove, as shown in Figure 8.Make this doped polycrystalline silicon layer in forming process carry out severe and mix, so that a specific electrical conductivity to be provided.This doping is preferably the N type that for example uses phosphorus and mixes, and about 2 * 10
20To about 6 * 10
20Atom/cm
3Concentration range in, and with 4 * 10
20Atom/cm
3Be advisable.In this bit line raceway groove, this doped polysilicon layer fills up this contact opening and covers on this substrate surface and form.This substrate surface will form this source/drain zone of imitating triode.
The doped polycrystalline silicon layer upper section is removed by means of an etching step in the forming process.This etching step is also removed polysilicon layer in some raceway grooves that mix in forming process.About 1000 of the preferable end face of the end face of this polysilicon apart from this silicon substrate.The example of this etching step comprises macroion etching, reactive ion etching etc.
The polysilicon that will mix in forming process is removed from these non-bit line channel regions.That is at this capacitor raceway groove, but not this bit line raceway groove is removed with the polysilicon that mixes in the forming process.In one embodiment, removing of the polysilicon of this doping is by the end face that applies this substrate with the photoetching agent, makes the zone that covers on this capacitor raceway groove expose and take place again.Then the polysilicon that will mix with an etching step waits in the capacitor raceway groove thus and removes.
During the polysilicon that mixes in removing forming process, it is empty that each capacitor raceway groove then becomes, and insulation course still exists.This capacitor raceway groove utilizes a filler material to fill.This filler material should be easy to use, have good shielding character, and can optionally be removed during treatment step after a while.In one embodiment, utilize BPSG 901 to fill this raceway groove, as shown in Figure 9.Certainly, look its application, also can use other materials.
The polysilicon upper section 205 that mixes in forming process in this no wire channel is to borrow thermal treatment and oxidation, as shown in Figure 9.This polysilicon layer is exposed to a high temperature and an oxidized compound, oxygen for example, water etc.The thermal treatment of doped layer makes polysilicon change into a silicon dioxide layer with insulating property (properties) in this forming process.This silicon dioxide layer has about 400 to the thickness between about 600 scopes, and is advisable with about 500 .This thickness must be enough to make this bit line and the device element that covers the top to be isolated.Certainly, also can use other technologies (for example CVD etc.) to form this silicon dioxide layer.
Then, in this substrate, form the passage stop area.In one embodiment, carry out the photo mask step of P type passage area and the cloth of passage stop area and plant step.The preferable generation to of this implantation step is corresponding to the degree of depth of this trench bottom.This passage stops cloth and plants and for example be to use the N type cloth of phosphorus etc. to plant.
This protective seam is removed from this active region, as shown in Figure 9.This protective seam comprises silicon dioxide and silicon nitride.Can use dry etching technology or wet etching, for example phosphoric acid etc. is removed this silicon nitride layer.The silicon dioxide that covers on this substrate must optionally be removed, to avoid hurting this substrate.In one embodiment, use hydrofluoric acid solution to wait and optionally remove this silicon dioxide.Certainly, look its application, can use other technology.
With this CMOS process typical N type passage mos device and P type passage PMOS device, be formed up to respectively on this P type well area and the N type well area.The DRAM storage unit is to determine in this well area.The manufacturing of this device utilizes following step to carry out.
Then critical cloth is carried out on the whole surface of this substrate plants (threshold im-plant).It is through carrying out N type impurity is covered on P type and the N type well area simultaneously comprehensively that this cloth is planted.In one embodiment, this N type impurity comprises phosphorus, arsenic etc.
One mask is to determine to cover on the N type well area so that implant p type impurity, for example boron.This P type implantation step is the critical voltage that is used for setting N type lane device in each storage unit.It is that thickness on the gate oxide layer is decided that this cloth is planted.In addition, also can before N type impurity, implant p type impurity in advance.
One gate oxide layer 52 forms to cover the end face of this P type well area, as shown in figure 10.This gate oxide layer is a high-quality oxide, and is as thin as the effective switching that is enough to promote this device.The thickness typical case of this gate oxide layer goes up at about 90A between the scope of about 100 , and is advisable with about 100 .
One to cover polysilicon layer on this oxide skin(coating) be to utilize a deposition step and form.The thickness range of this polysilicon layer or Polycide (at the WSix on the polysilicon) and is advisable with about 3000 between about 2500 to about 3500 .Simultaneously, this polysilicon layer is generally with about 4 * 10
20To 6 * 10
20Atom/cm
3(be preferably 5 * 10
20Atom/cm
3) the N type doping impurity of concentration.One implantation and annealing steps are in order to provide N type impurity in this compound crystal silicon.In addition, N type impurity is spread when polysilicon layer forms simultaneously or form, to reduce treatment step.With regard to the embodiment of Polycide gate, the thin polysilicon about 1500A of can using and mix deposits the Wsi of about 1000 again
x
The pattern of planning this compound crystal silicon layer or Polycide is in order to definite this polycrystalline silicon gate pole 54, as shown in figure 10.These are called any suitable a series of optics development step (comprising photomask, video picture, etching etc.) of the frequent mat of gate electrode of word line and form.Each gate electrode comprises the edge with perpendicular outward appearance, but also can have non-perpendicular basically outward appearance.The definite geometric configuration system of this each gate electrode is according to its application and decide.
One comprehensive cloth is planted step and is utilized each gate electrode as a photomask, N type impurity is introduced in a part of trap, to determine in this P type trap 11 N-type LDD zone 42,48.The dosage range of this N type impurity is about 1 * 10
13To 5 * 10
13Atom/cm
2Between, and with about 3 * 10
13Atom/cm
2Be advisable.The angular range of implanting from and the channel direction cross line start at greater than 0 ° (preferable about 30 °) between about 45 °.Another alternatively shields N type well area, and will make the N type to P type well area and implant, to determine N type LDD zone.This series of steps is in order to determine the N type LDD zone in the mnemon.
Then, shield P type well area, and p type impurity is imported in the N type well area.This implantation is in order to determine the P-type LDD zone in this N type well area, and P-type LDD zone comprises about 1 * 10
13To 5 * 10
13Atom/cm
2The dosage of scope, and with about 3 * 10
13Atom/cm
2Be advisable.Look its application, this P-type LDD can use the cloth with angle to plant (angleimplant) in the zone.
The source of each mos device/drain zone is to borrow last photomask and cloth to plant step and determine.The zone of P type lane device is determined in the one photoresistance photomask protection of concrete status, and makes the overseas dew of source/drain area, thinks that this N type lane device is used.N+ type impurity is implanted these expose the zone to determine this N+ type source/ drain zone 40,50, as shown in figure 10.These impurity comprise phosphorus etc.The dosage range of this N+ type impurity ties up to about 3 * 10
15Atom/cm
2To about 5 * 10
15Atom/cm
2Between, and with about 4 * 10
15Atom/cm
2Be advisable.The angular range of implanting be from and the channel direction cross line start between about 0 ° to about 7 °, and with about 0 the degree be advisable.This photoresistance photomask utilizes known techniques to remove.
Then, protect this N type lane device, and make the overseas dew of this source/drain area, with used by this P type lane device with another photoresistance photomask.The dosage range of P+ type impurity about 3 * 10
15To 5 * 10
15Atom/cm
2Between, and with about 4 * 10
15Atom/cm
2Be advisable.Then, use known technology to remove this photoresistance photomask.
Then, at photomask on this substrate top surface to determine the opening above these trench type capacitor zones.That is, cover this bit line and word line with a photoresistance photomask.This BPSG 901 is removed from these trench type capacitor zones.In one embodiment, with use the hydrofluoric acid wet etch step optionally with bpsg layer by removing in this raceway groove, and stay these insulating regions 24.In addition, also can use dry etching technology with optionally with bpsg layer by removing in this raceway groove.Then, use known technology to remove this photoresistance photomask.
One to cover on this gate electrode 54 inter-level dielectric 60 be to form with a CVD method, as shown in figure 11.This inter-level dielectric can be a suitable material that comprises TEOS etc.Should be to deposit such as the technology of APCVD, PECVD, LPCVD etc. as the inter-level dielectric of silicon dioxide etc. with one.Certainly, institute's operation technique is decided according to its application.
Then the step of carrying out is, a photoresistance photomask that covers on this substrate top surface zone that comprises the capacitor raceway groove is provided, and covers storage unit joining zone or opening with formation, is determined by etching technique, as shown in figure 11.The example of etching technique comprises plasma etching, reactive ion etching etc.In addition, also can use and select for use such as the wet etch techniques of hydrofluorite as the selective etch agent.As shown in the figure, each opening is made for the usefulness that following electrode for capacitors is connected to this effect triode source/drain zone.Also low about 2000 of this substrate surface of this aperture efficiency.This top of exposing source/drain zone can not used before next step basically in oxidation.Can use diluted acid dipping or or dry etching technology clean this source/drain zone.
Next step is that deposition one covers the following capacitor electrode layer on the exposed parts 36 in this area of isolation and this source/drain zone.This time capacitor layer also is provided on the top 1201 of this inter-level dielectric 60, uses the surface area of further increase capacitor unit.The surface area of this increase provides the increase of electric capacity.This time capacitor layer is preferable made with the polysilicon that reduces resistance by mixing through impurity severe.The introducing of this impurity is looked its applicability and is selected multiple angle cloth planting technology for use or mix during forming.In one embodiment, these impurity are the N type, for example, and phosphorus etc.
Last photomask and etching step will descend in the definite capacitor electrode pole plate 26 once of capacitor layer, as shown in figure 12.Capacitor electrode pole plate 26 is to see through this contact opening 36 to be connected to this effect triode source/drain zone 38 under this.Then, utilize known technology to remove this lithography layer.In manufacturing one, before the dielectric, utilize dry etching technology to clean this time capacitor layer.
One capacitor dielectric 28 forms to cover on this time condenser armature.This capacitor dielectric is in order to store the electric charge between condenser armature on this time condenser armature and.In one embodiment, this capacitor dielectric is a high-quality nitride/oxide composite bed.In a preferred embodiment, this capacitor dielectric comprise one cover silicon dioxide layer, on this time condenser armature cover silicon nitride layer on this silicon dioxide layer, and another cover the silicon dioxide layer of this nitride layer.This combination layer provides the characteristic of high storage capacity and is easy to and makes.
Finish this capacitor constructions after, the capacitor layer deposition is to cover on this capacitor dielectric on one.Should go up capacitor layer can be once the severe doping to reduce the polysilicon layer of resistance.Visual its applicability of this polysilicon layer and select multiple angle cloth planting technology for use or during forming, mix.Last photomask and etching step should be gone up capacitor layer and be determined at condenser armature on, as shown in figure 13.By this time condenser armature, this capacitor dielectric and this are gone up condenser armature and are determined this capacitor constructions.As shown in the figure, the capacitor constructions of a part is positioned at this effect triode and this raceway groove top is long-pending to increase capacitor surface, and using provides big electric capacity.
Thick-layer 14 depositions of BPSG/NSG are to cover on the whole base plate end face.The BPSG/NSG combination layer forms with typical CVD deposition techniques.These BPSG/NSG layers will this below device construction and the metalling (metallization) of top isolate.Use an annealing steps to flow whole this BPSG/NSG layer.Thereby this laminar surface cover is determined the contact opening with photoresistance.Utilize an engraving method and form this contact opening.Then, utilize known technology to remove this photoresistance.
One the first metal layer forms covering on these layers, and is formed in these contact openings so that be electrically connected.Photomask and etched step are planned the pattern of this first metal layer 16 in the utilization, as shown in figure 14.One intermetallic metal oxide skin(coating), 17 depositions are with on the first metal layer 16 that covers this pattern formation.This intermetallic metal oxide skin(coating) is with typical C VD deposition techniques.
Utilize known photoresistance and etching technique that one channel pattern (via pattern) is determined in this intermetallic metal oxide skin(coating).This channel pattern has the opening that supplies the first metal layer and second metal interlevel to electrically contact.Overlaying on this intermetallic metal oxide, and spraying plating is in these passages with this second metal level spraying plating.The step of one planning pattern is determined this second metal level.
Remaining manufacturing step comprises the deposition of the passivation of a silicon nitride containing layer and silicon dioxide layer.The pattern of planning this passivation layer engages routing (bondingpad) district's opening and fuse (fuse) opening to form.This opening is a mat etching technique and making.Cover on whole surface with polyimide then.Last plan the pattern on the surface that this is capped with photomask on one and etching step again.After pattern formed, slaking should the lining surface.Further step comprises brilliant figure ordering, assembling, test etc.
Though above explanation is the whole detailed description of specific embodiment, also applicable various modifications, deformation structure and equivalent manners.As, though above-mentioned explanation is the basis that is configured to illustrate with DRAM, can also waits with SRAM and realize the present invention.
Therefore, should be with above-mentioned explanation and embodiment qualification as the scope of the invention.Scope of the present invention should be determined by appended scope.
Claims (20)
1. storage arrangement, this device comprises:
The semiconductor substrate comprises a sunk area, and this protruding sunken zone has the side that is extended by a bottom surface;
Imitate triode for one, this is imitated triode and comprises that one is adjacent to the source/drain zone of this sunk area;
One insulation course covers on this sunk area;
Once condenser armature covers on this insulation course, and is positioned at this effect triode of part top, and this time condenser armature is connected to this source/draw source region;
One capacitor dielectric covers on this time condenser armature that is situated between; And
Condenser armature on one covers on this dielectric layer.
2. device as claimed in claim 1, wherein this sunk area has about 8,000 depth rangees to about 12,000 .
3. device as claimed in claim 1, wherein this time condenser armature has about 1,000 thickness range to about 1,400 .
4. device as claimed in claim 1, wherein this time condenser armature has the thickness of about 1,200 .
5. device as claimed in claim 1, wherein this time condenser armature is the polysilicon layer of a doping (in-situ doped) in forming process.
6. device as claimed in claim 1 wherein should be gone up the polysilicon layer that condenser armature is a doping (in-situ doped) in forming process.
7. device as claimed in claim 1, wherein this capacitor dielectric comprises an oxide layer.
8. device as claimed in claim 1, wherein this capacitor dielectric comprises an oxide layer and a nitration case.
9. device as claimed in claim 1, wherein this effect triode is-the MOS triode.
10. method that forms the audion of storage arrangement, this method comprises:
The semiconductor substrate is provided;
Form a sunk area, this sunk area has the side that is extended by a bottom surface;
Form once determining to cover the insulation course on this sunk area;
Formation one is adjacent to the source/drain zone of this sunk area;
Formation one covers on this insulation course and is positioned at the following condenser armature of this effect triode top of a part, and this time condenser armature is connected to this source/drain zone;
Form a capacitor dielectric that covers on this time condenser armature; And
Form a last condenser armature that covers on this dielectric layer.
11. as the method for claim 10, wherein this sunk area has about 8,000 depth rangees to about 12,000 .
12. as the method for claim 10, wherein this time condenser armature has about 1,000 thickness range to about 1,400 .
13. as the method for claim 10, its this time condenser armature has the thickness less than about 1,200 .
14. as the method for claim 10, its this time condenser armature is the polysilicon layer of a doping (in-situ doped) in forming process.
15. as the method for claim 10, it should go up the polysilicon layer that condenser armature is a doping (in-situ doped) in forming process.
16. as the method for claim 10, wherein this capacitor dielectric comprises an oxide layer.
17. as the method for claim 10, wherein this capacitor dielectric comprises an oxide layer and a nitration case.
18. as the method for claim 10, wherein this imitates triode system-MOS triode.
19. a dynamic RAM integrated circuit, this integrated circuit component comprises:
The semiconductor substrate comprises a sunk area, and this sunk area has the side that is extended by a bottom surface;
Imitate triode for one, this is imitated triode and comprises that one is adjacent to the source/drain zone of this sunk area;
One insulation course is through determining to cover on this sunk area; And
One conductor determines that in this sunk area this conductor is connected to this source/drain zone.
20. form the method for bit line in the dynamic RAM integrated circuit component, this method comprises:
The semiconductor substrate is provided;
Form a sunk area in this semiconductor substrate, this sunk area has the side that is extended by a bottom surface;
Form once determining to cover the insulation course on this sunk area;
Form one and imitate triode, this is imitated triode and comprises that one is adjacent to the source/drain zone of this sunk area; And
Form a conductor that is determined in this sunk area, this conductor is connected to this source/drain zone.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96105125 CN1126166C (en) | 1996-05-10 | 1996-05-10 | High density storage structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96105125 CN1126166C (en) | 1996-05-10 | 1996-05-10 | High density storage structure |
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| CN1165381A true CN1165381A (en) | 1997-11-19 |
| CN1126166C CN1126166C (en) | 2003-10-29 |
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| CN 96105125 Expired - Fee Related CN1126166C (en) | 1996-05-10 | 1996-05-10 | High density storage structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101004522B (en) * | 2006-01-16 | 2010-09-29 | 精工爱普生株式会社 | Electrooptical device, electronic apparatus, and projector |
| CN101621028B (en) * | 2008-07-02 | 2011-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing defects in memory cell capacitor |
| US10923391B2 (en) | 2017-02-16 | 2021-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with contact pad |
| CN112802521A (en) * | 2019-11-13 | 2021-05-14 | 华邦电子股份有限公司 | Method for curing resistive random access memory |
-
1996
- 1996-05-10 CN CN 96105125 patent/CN1126166C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101004522B (en) * | 2006-01-16 | 2010-09-29 | 精工爱普生株式会社 | Electrooptical device, electronic apparatus, and projector |
| CN101621028B (en) * | 2008-07-02 | 2011-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing defects in memory cell capacitor |
| US10923391B2 (en) | 2017-02-16 | 2021-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with contact pad |
| TWI734856B (en) * | 2017-02-16 | 2021-08-01 | 台灣積體電路製造股份有限公司 | A semiconductor structure and a method of fabricating the same |
| US11410878B2 (en) | 2017-02-16 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with contact pad and method of making |
| US11784089B2 (en) | 2017-02-16 | 2023-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with contact pad and method of making |
| CN112802521A (en) * | 2019-11-13 | 2021-05-14 | 华邦电子股份有限公司 | Method for curing resistive random access memory |
| CN112802521B (en) * | 2019-11-13 | 2024-02-23 | 华邦电子股份有限公司 | Method for curing resistance random access memory |
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| Publication number | Publication date |
|---|---|
| CN1126166C (en) | 2003-10-29 |
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