The specific embodiment explanation
I. dynamic random access memory means is constructed
Fig. 1 is the simple sectional drawing of DRAM integrated circuit (IC) apparatus 10 of the present invention.This device only for explanation example of the present invention, should not be defined in this with the scope of claim.Generally speaking, this DRAM device 10 comprises a plurality of memory cell region 12, a covering dielectric layer 14, a top metal layer (top metallization layer) 16, one passivation layer 17 and other elements.This memory cell region can be used known CMOS treatment technology to wait and make.
Each memory cell region 12 all is determined in the P type well area 22, and a fet 18 is determined in this P type well area 22.This fet is a N type channel mos (MOS) device, and it comprises a gate electrode 54.This gate electrode 54 (is called word line; Word line), be covered on the thin brake-pole dielectric layer 52.Sidewall (sidewall) 56 is defined as being adjacent to gate 54 sides.Cover on this gate 54 is a lid oxide layer (cap oxide layer) 58.One inter-level dielectric (inter-layer dielectric) 60 forms to cover on this lid oxide skin(coating) 58, also covers on the source or drain region 38,46 of part.Each source or drain region all comprise a N-type LDD zone 42,48 and a N+ type source or a drain region 40,50.As shown in the figure, N+ type source or drain region 40 are connected to a trench type capacitor (trench capacitor) 20, are determined in this P type well area 22.
This trench type capacitor can be used as a kind of storage device and uses, and is arranged in the electric charge of the electric capacity dielectric 30 of 28 of condenser armatures 26 and last condenser armature down in order to storage, and this electric capacity dielectric can be any suitable insulating material, such as silicon dioxide, silicon nitride etc.This electric capacity dielectric is preferably an interlayer that comprises silicon dioxide, silicon nitride and silicon dioxide, and it is known oxide-nitride-oxide (oxide-on-nitride-on-oxide; ONO).Certainly, also can use the combination of other dielectric materials according to its applicability.
This time condenser armature 26 is determined above this fet 18, and is covered on the insulating barrier 24 covering trench bottom 32 and avris 34.The thickness of this insulating barrier is enough to make this P type well area and following condenser armature 26 to be isolated through selection.High-quality earth silicon material can be made this insulating barrier to reach the insulation purpose.Yet the part 36 of this insulating barrier on this raceway groove avris 34 removed, so that electrical contact of 40 of this time capacitor 26 and this N+ type source or drain regions to be provided.
This time condenser armature can be any suitable conductor layer.This time condenser armature is preferably in forming process the polysilicon layer of (in-situ doped) the N type of doping impurity (for example phosphorus etc.).This time condenser armature also can be made the sandwich that comprises multi-metal layer, silicide layer and combination thereof etc.In another embodiment, this time condenser armature utilizes one to have polysilicon layer texture or coarse and make.This polysilicon layer (different with level and smooth polysilicon layer) with texture has kick, to increase the effective surface area of capacitor by this.As shown in the figure, the insulating barrier of this time condenser armature on trench bottom 32 extends, and covers on the insulating barrier on the raceway groove avris 34, contacts this source or drain region 40, and extends this inter-level dielectric 60 tops, cover this fet 18 on.
Should go up condenser armature 28 covers on this capacitor dielectric 30.Should go up condenser armature and extend, and extend with on the capacitance dielectric layer that covers this time condenser armature from this raceway groove insulating barrier bottom 32.It is preferably made by the polysilicon layer of doped N-type impurity in forming process to go up condenser armature.Another selectable scheme is that condenser armature also can be made into the sandwich structure that comprises many metal levels, silicide layer and combination thereof etc. on this.Another embodiment uses a kind of by having the made last condenser armature of texture or rough polysilicon layer.This polysilicon layer (different with level and smooth compound crystal silicon layer) with texture has kick, to increase the effective surface area of capacitor by this.
As shown in the figure, condenser armature 26 under the comprising involved in the present invention, electric capacity dielectric 30, and go up the trench type capacitor structure of condenser armature 28, this trench bottom 32 is extended certainly, extends along its avris 34, and extends through these fet 18 tops.Therefore, can make longer than the known capacitor structure basically trench type capacitor structure.
Trench type capacitor of the present invention is designed to increase electric capacity and does not have a shortcoming of known channel junction structure; Before and after often being difficult for, known channel junction structure is produced on certain consistently more than the degree of depth.For example, when using the design rule of 0.25 μ m, the channel depth scope is from about 8,000 to about 12,000 , and is advisable with about 10,000 .With regard to bit line and insulation layer, this channel width is about 2,500 .With regard to capacitor, this channel width is about about 4,000 scopes.This raceway groove structure is provided with condenser armature.The thickness range of this condenser armature is about 1,000 to about 1,400 , and is advisable with about 1,200 .The following condenser armature that must be noted that a part is to determine to cover on this fet and the raceway groove avris.
Fig. 2 is the simplification sectional drawing of the bitline junction structure of DRAM among Fig. 1.Bitline junction structure of the present invention is an illustrated example only, and scope of the present invention should be defined in this.This section Figure 200 comprises: P type well area 22 and gate electrode 54 (or word line).One bit line 204 is formed in the raceway groove 201 with avris and bottom.Described raceway groove has an insulating barrier, and this insulating barrier comprises an end insulating barrier part 203 and one side side insulation layer part 202, covers around it.This insulating barrier is in order to isolate bit line and P type well area 22.As shown in the figure, this bit line forms in the mode perpendicular to this word line 54, and is used for being connected in each triode source or drain region of contiguous this bit line.
Particularly, this bit line is connected in the source or the drain region 46 of this fet 18.Described connection sees through the contact opening 207 in this avris insulating barrier part 202 and forms.In other words, the avris insulating barrier line on the throne of a part is removed before forming, and forms one and be used to contact opening that this source or drain region 46 are contacted with this bit line 204.As use 0.25 μ m design rule (design rule), then this contact A/F is in about 2000 scopes to about 2800 , and is advisable with about 2200 .The degree of depth of this contact opening ties up to the scope of about 2200 to 2800 , and is advisable with about 2500 .
This bit line is made by a conductor material, more preferably be one in forming process the polysilicon layer of doped N-type impurity (for example phosphorus etc.).In addition, this bit line also can borrow the deposit spathic silicon layer to reach by POCl
3Diffusion with realize severe and mix or mat annealing so that implanting ions and forming.This bit line is limited by this channel width and channel depth.Corresponding to this channel depth is this bit line thickness, and it has the bottom insulation part of top insulated part and about 5000 of about 1000 .Certainly, this bit line more can be made by the other materials (such as the combination of Polycide or multiple material) of different size.
Cover on this bit line is a top layer part 205.This top insulated part 205 makes it avoid covering such as on the device elements such as gate electrode in order to isolate this bit line.The insulating barrier part that comprises this top layer part 205, avris insulating barrier part 202 and bottom insulation layer segment 203, be used for determining be looped around this bit line around, and in order to make this bit line haply and to be determined to isolate around the P type well area around this raceway groove and other device elements.As shown in the figure, this top layer 205 is connected in this avris insulating barrier part 202, and this avris insulating barrier part 202 then is connected in end insulating barrier part 203.
Fig. 3 is another sectional drawing 300 of Fig. 2 bitline configurations.Sectional drawing is in order to illustrating this bit line 204 via contact opening 207, with being connected of 46 of this source or drain regions.As shown in the figure, this contact opening 207 makes this bit line 204 can be connected to N
+Type source or drain region 50.This N
+The N that connects near type source or drain region provide
-Therefore the resistance that type LDD zone is lower, help the transmission of electric charge, and wherein this electric charge is the signal that representative is sent to this bit line 204 by the source or the drain region 46 of memory cell.Being connected of 46 of this bit line 204 and source or drain regions occurs in this N
+Type source or 50 places, drain region.
With this contact opening 207 adjacent be this top layer part 205 and avris insulating barrier part 202A.This top layer part 205 and avris insulating barrier be 202A partly, is connected to each other avris insulating barrier part 202 and bottom insulation layer segment.The combination of this kind insulating barrier part is isolated bit line 204 and abutment means part, but this bit line 204 is connected with the source or the drain region 46 of this triode.Each DRAM memory cell all has this kind bit line connected mode.
Fig. 4 is the simplification top view 400 of DRAM integrated circuit structure of the present invention.This top view only is an illustrated example, and the present invention should be defined in this.This top view shows that one has the matrix of Y direction and directions X.Gate electrode 54 extends on directions X, determines to cover on the P type well area 22.Through vertically being determined at electrode for capacitors 26 under each on the Y direction, be formed on this gate electrode 54 tops.A plurality of bit lines 204 extend along electrode below the gate on the Y direction 54, and perpendicular to this gate electrode 54.Each bit line all comprises a plurality of contacts 207, makes this bit line be connected to the indivedual sources or the drain region of this fet.
II. dynamic random access memory manufacturing technology
Whole manufacture methods of the present invention are summarized as follows.
(1) provides the semiconductor substrate;
(2) photomask 1: form P type trap in this semiconductor substrate;
(3) photomask 2: form N type trap in this semiconductor substrate;
(4) formation one comprises the protective layer of bed course oxide (pad oxide) layer and silicon nitride layer;
(5) photomask 3: form active region (active area) to determine channel region;
(6) form channel region;
(7) form trench sidewalls and bottom oxidization layer;
(8) photomask 4: determine bit line contact, and remove the photoetching agent;
(9) polysilicon that mixes in the deposition forming process is to fill channel region;
(10) eat-back the polysilicon that mixes in the forming process, so that the polysilicon that mixes in the forming process remains in the raceway groove;
(11) photomask 5: determine non-bit line channel region, and remove the polysilicon that mixes in the forming process in the non-bit line channel region;
(12) polysilicon that mixes in the forming process in the oxidation bit line channel region;
(13) photomask 6: photomask P type passage area and implantation passage stop area (channel stop region) are up to this trench bottom;
(14) deposition boron phosphorus silicate glass (BPSG) is to fill up the channel region in this non-bit line channel region;
(15) remove this protective layer from this active region;
(16) carry out comprehensive critical implantation (blanket threshold implant);
(17) photomask 7: shielding N type well area, and implant p type impurity in this memory cell region (or P type well area) to regulate critical voltage;
(18) form the gate oxide layer;
(19) form gate polysilicon layer or the Polycide (or Poly-1) that mixes;
(20) photomask 8: determine that the gate polysilicon layer is to form gate electrode;
(21) photomask 9: determine slightly mix drain (LDD) zone and implant N type impurity of N type;
(22) photomask 10: determine P type LDD zone and implant p type impurity;
(23) on the avris of polycrystalline silicon gate pole electrode, form sidewall spacers (sidewall spacer);
(24) photomask 11: determine N+ type source or drain region and implant N+ type impurity;
(25) photomask 12: determine P+ type source or drain region and implant P+ type impurity;
(26) photomask 13: cover bit line zone and word line regions with the photoetching agent, determine capacitor area;
(27) remove BPSG in the trench type capacitor zone, and remove the photoetching agent;
(28) polysilicon oxide layer in the middle of the deposition;
(29) photomask 14: determine capacitor unit joining zone and etching;
(30) deposition poly-2 layer and doping;
(31) photomask 15: determine the poly-2 layer, to form electrode for capacitors;
(32) form the cell capaciator dielectric;
(33) deposition poly-3 layer and mix (or during forming, make doped p oly-3 deposition);
(34) photomask 16: determine the poly-3 layer, to form electrode for capacitors on;
(35) deposition BPSG/NSG (non-impurity-doped silicate glass), and stream whole (flow);
(36) photomask 17: determine the contact pattern in the BPSG/NSG layer;
(37) sputter the first metal layer;
(38) photomask 18: determine the first metal layer;
(39) deposition intermetallic metal oxide (inter-metal oxide);
(40) photomask 19: determine passage (via) pattern;
(41) sputter second metal level;
(42) photomask 20: determine second metal level;
(43) heavy kind of passivation layer and polyimide coating;
(44) photomask 21: determine routing district (pad region) and fuse (fuse) open area;
(45) polyimides slaking (cure);
(46) the etch passivation floor is to determine the routing district; And
(47) sintering.
These steps provide an improvement capacitor with a shallow channel and stacked capacitor plate.Each condenser armature is all determined in this raceway groove and above the gate electrode part of this fet.Therefore, form a bigger capacitance meter area, thereby can improve memory capacity.The present invention also provides the bit line structure that is determined in this raceway groove.This bit line structure is not using under the complex configuration of known technology, is connected in each source or drain region.These steps are also pure to be the explanation example, thereby the scope of the invention should not be subject to this.Below, with reference to description of drawings this method.
Fig. 5~14 show the simple manufacture method of DRAM integrated circuit (IC) apparatus of the present invention.This method is pure to be the explanation example, thereby scope of the present invention should not be subject to this, and this method is from providing semiconductor substrate 11, as shown in Figure 5.This substrate can be any wafer that integrated circuit (IC) apparatus of the present invention is used that is suitable for making.For example, be used to carry out the manufacturing technology of complementary metal oxide semiconductors (CMOS) (CMOS) device of DRAM storage device by this wafer.But can use other manufacturing technologies according to its particular utility.
One mask is through determining with on the upper surface that covers this semiconductor substrate, to form P type well area 22.This P type well area 22 be contain P-type material by implantation impurity to this substrate and form.P type impurity comprises boron etc.This mask utilizes known technology to remove.Then, N type lane device can be formed in the P type well area.
N type trap also can be determined in this semiconductor substrate.Specifically, a mask forms with on the P type well area that covers this semiconductor substrate.Utilize an implantation step to form this interior N type well area of this semiconductor substrate.N type impurity comprises as materials such as phosphorus, arsenic.This mask utilizes known technology to remove.Then, P type lane device can be formed in the N type well area.
Dielectric layer combination 501 is determined to cover on this substrate, to form a protective layer, as shown in Figure 5.That is, this protective layer is used as a photo mask layer.This protective layer comprises the silicon nitride layer 505 that a bed course oxide skin(coating) 503 and covers the top.This bed course oxide skin(coating) thickness is 200 to 300 .This silicon nitride layer is that 1200~1800 are thick.This silicon nitride layer 505 also can freely comprise another silicon dioxide layer (not shown) that covers the top.These layers to determine a plurality of channel regions, comprise a capacitor raceway groove 20 and a bit line raceway groove 201, as shown in Figure 6 through planning.
The formation of this capacitor raceway groove 20 and bit line raceway groove 201 is to form with a dry etching technology.One example of dry etching technology can comprise reactive ion etching (reactive ion etching), plasma etching (plasma etching) etc.More known capacitor zanjon, this raceway groove is preferably more shallow, thereby makes consistently easily.As use 0.25 μ m design rule, then this capacitor channel depth scope and is advisable with about 1.0 μ m between about 0.8 to about 1.20.25 μ m.This raceway groove has the width of 0.4 μ m simultaneously.As use same design rule, and then this bit line channel depth can be suitable with this capacitor raceway groove, about 0.8 between the scope of about 1.2 μ m, and approximately to be advisable with 1.0 μ m.This raceway groove has the width of 0.25 μ m simultaneously.Certainly, the degree of depth of each raceway groove and width are decided according to its application.
One dielectric spacer material layer is to be determined in each raceway groove that comprises capacitor raceway groove 20 and bit line raceway groove 201, as shown in Figure 7.Especially, this capacitor raceway groove 20 comprises a dielectric layer 24 that covers on this trench bottom 32 and the raceway groove avris 34.This bit line raceway groove 201 has avris dielectric layer part 202 and the bottom dielectric layer segment 203 that covers respectively on this raceway groove avris and the bottom.The thermal oxidation of the preferable footpath of this raceway groove silicon and being covered by an oxide layer.This oxide layer has a thickness that is enough to its covering structure and substrate and the isolation of other device elements.This oxide layer is preferable to have one from about 400 thickness to about 600 scopes, and is advisable with about 500 .But this raceway groove is the technology that is fit to of mat chemical vapour deposition technique (CVD) or other and deposit coating and go up monoxide layer or multiple dielectric layer also.Certainly, this dielectric layer material and thickness thereof are decided according to its application.
Be formed at dielectric layer neutrality line contact in this equipotential line raceway groove and be and utilize photomask and etching technique and determined.This bit line contact is the contact opening 207 in the dielectric layer that is defined as covering on this raceway groove avris.Aspect the embodiment that uses the monoxide dielectric layer, this contact opening is by comprising the upper surface of base plate of raceway groove with photoetching agent coating and making.Draw photoengraving pattern and cover the zone of exposing of these contacts applying laggard professional etiquette with formation, and wet etching this expose the zone to form the step of this bit line contact opening.Each bit line contact open mouth is that 0.25 μ m is wide and 3000 are dark.Then, use known technology to remove this lithography layer.During treatment step after a while, this contact opening provides a passage (via) structure, this bit line is connected to the source or the drain region of each fet.
Then, use the polysilicon packed layer 801 that mixes in the forming process to fill this raceway groove, as shown in Figure 8.Make this doped polycrystalline silicon layer in forming process carry out severe and mix, so that a specific electrical conductivity to be provided.This doping is preferably the N type that for example uses phosphorus and mixes, and about 2 * 10
20To about 6 * 10
20Atom/cm
3Concentration range in, and with 4 * 10
20Atom/cm
3Be advisable.In this bit line raceway groove, this doped polysilicon layer fills up this contact opening and covers on this substrate surface and form.This substrate surface will form the source or the drain region of this fet.
The doped polycrystalline silicon layer upper section is removed by means of an etching step in the forming process.This etching step is also removed polysilicon layer in some raceway grooves that mix in forming process.About 1000 of the preferable end face of the end face of this polysilicon apart from this silicon substrate.The example of this etching step comprises macroion etching, reactive ion etching etc.
The polysilicon that will mix in forming process is removed from these non-bit line channel regions.That is at this capacitor raceway groove, but not this bit line raceway groove is removed with the polysilicon that mixes in the forming process.In one embodiment, removing of the polysilicon of this doping is by the end face that applies this substrate with the photoetching agent, makes the zone that covers on this capacitor raceway groove expose and take place again.Then the polysilicon that will mix with an etching step waits in the capacitor raceway groove thus and removes.
During the polysilicon that mixes in removing forming process, it is empty that each capacitor raceway groove then becomes, and insulating barrier still exists.This capacitor raceway groove utilizes a filler material to fill.This filler material should be easy to use, have good shielding character, and can optionally be removed during treatment step after a while.In one embodiment, utilize BPSG901 to fill this raceway groove, as shown in Figure 9.Certainly, look its application, also can use other materials.
The polysilicon upper section 205 that mixes in forming process in this no wire channel is to borrow heat treatment and oxidation, as shown in Figure 9.This polysilicon layer is exposed to a high temperature and an oxidized compound, oxygen for example, water etc.The heat treatment of doped layer makes polysilicon change into a silicon dioxide layer with insulating property (properties) in this forming process.This silicon dioxide layer has about 400 to the thickness between about 600 scopes, and is advisable with about 500 .This thickness must be enough to make this bit line and the device element that covers the top to be isolated.Certainly, also can use other technologies (for example CVD etc.) to form this silicon dioxide layer.
Then, in this substrate, form the passage stop area.In one embodiment, carry out the photo mask step of P type passage area and the cloth of passage stop area and plant step.The preferable generation to of this implantation step is corresponding to the degree of depth of this trench bottom.This passage stops cloth and plants and for example be to use the N type cloth of phosphorus etc. to plant.
This protective layer is removed from this active region, as shown in Figure 9.This protective layer comprises silicon dioxide and silicon nitride.Can use dry etching technology or wet etching, for example phosphoric acid etc. is removed this silicon nitride layer.The silicon dioxide that covers on this substrate must optionally be removed, to avoid hurting this substrate.In one embodiment, use hydrofluoric acid solution to wait and optionally remove this silicon dioxide.Certainly, look its application, can use other technology.
With this CMOS process typical N type passage mos device and P type passage PMOS device, be formed up to respectively on this P type well area and the N type well area.The DRAM memory cell is to determine in this well area.The manufacturing of this device utilizes following step to carry out.
Then critical cloth is carried out on the whole surface of this substrate plants (thresholdimplant).It is through carrying out N type impurity is covered on P type and the N type well area simultaneously comprehensively that this cloth is planted.In one embodiment, this N type impurity comprises phosphorus, arsenic etc.
One mask is to determine to cover on the N type well area so that implant p type impurity, for example boron.This P type implantation step is the critical voltage that is used for setting N type lane device in each memory cell.It is that thickness on the gate oxide layer is decided that this cloth is planted.In addition, also can before N type impurity, implant p type impurity in advance.
One gate oxide layer 52 forms to cover the end face of this P type well area, as shown in figure 10.This gate oxide layer is a high-quality oxide, and is as thin as the effective switching that is enough to promote this device.The thickness typical case of this gate oxide layer goes up at about 90A between the scope of about 100 , and is advisable with about 100 .
One to cover polysilicon layer on this oxide skin(coating) be to utilize a deposition step and form.The thickness range of this polysilicon layer or Polycide (at the WSix on the polysilicon) and is advisable with about 3000 between about 2500 to about 3500 .Simultaneously, this polysilicon layer is generally with about 4 * 10
20To 6 * 10
20Atom/cm
3(be preferably 5 * 10
20Atom/cm
3) the N type doping impurity of concentration.One implantation and annealing steps are in order to provide N type impurity in this compound crystal silicon.In addition, N type impurity is spread when polysilicon layer forms simultaneously or form, to reduce treatment step.With regard to the embodiment of Polycide gate, the thin polysilicon about 1500A of can using and mix deposits the Wsi of about 1000 again
x
The pattern of planning this compound crystal silicon layer or Polycide is in order to definite this polycrystalline silicon gate pole 54, as shown in figure 10.These are called any suitable a series of optics development step (comprising photomask, video picture, etching etc.) of the frequent mat of gate electrode of word line and form.Each gate electrode comprises the edge with perpendicular outward appearance, but also can have non-perpendicular basically outward appearance.The definite geometry system of this each gate electrode is according to its application and decide.
One comprehensive cloth is planted step and is utilized each gate electrode as a photomask, N type impurity is introduced in a part of trap, to determine in this P type trap 11 N-type LDD zone 42,48.The dosage range of this N type impurity is about 1 * 10
18To 5 * 10
13Atom/cm
2Between, and with about 3 * 10
13Atom/cm
2Be advisable.The angular range of implanting from and the channel direction cross line start at greater than 0 ° (preferable about 30 °) between about 45 °.Another alternatively shields N type well area, and will make the N type to P type well area and implant, to determine N type LDD zone.This series of steps is in order to determine the N type LDD zone in the mnemon.
Then, shield P type well area, and p type impurity is imported in the N type well area.This implantation is in order to determine the P-type LDD zone in this N type well area, and P-type LDD zone comprises about 1 * 10
13To 5 * 10
13Atom/cm
2The dosage of scope, and with about 3 * 10
13Atom/cm
2Be advisable.Look its application, this P-type LDD can use the cloth with angle to plant (angleimplant) in the zone.
Sidewall spacers 56 is to determine on the edge of each polycrystalline silicon gate pole 54.These sidewall spacers 56 generally form by depositing a dielectric materials layer, make fine and closely wovenization of this layer and removing steps such as this layer horizontal surface.This layer is made such as materials such as silicon dioxide, silicon nitride, its combinations by one.The step that this makes fine and closely wovenization of dielectric materials layer is in order to seal this benefit crystal silicon gate 54, to isolate with each layer (for example dielectric material of silicon dioxide, silicon nitride, its combination etc.) that covers thereon.The non-grade of being carried out on this fine and closely wovenization dielectric layer is this layer horizontal surface that forms sidewall spacers in order to remove to etching.This non-grade is removed the horizontal surface of dielectric material to etching step, and stays this sidewall spacers.This non-grade comprises such as technology such as reactive ion etching, plasma etchings to etching step.
The source of each mos device or drain region are to borrow last photomask and cloth to plant step and determine.The zone of P type lane device is determined in the one photoresistance photomask protection of concrete status, and source or drain region are exposed, and thinks that this N type lane device is used.N+ type impurity is implanted these expose the zone to determine this N+ type source or drain region 40,50, as shown in figure 10.These impurity comprise phosphorus etc.The dosage range of this N+ type impurity ties up to about 3 * 10
15Atom/cm
2To about 5 * 10
15Atom/cm
2Between, and with about 4 * 10
15Atom/cm
2Be advisable.The angular range of implanting be from and the channel direction cross line start between about 0 ° to about 7 °, and with about 0 the degree be advisable.This photoresistance photomask utilizes known techniques to remove.
Then, protect this N type lane device with another photoresistance photomask, and this source or drain region are exposed, with used by this P type lane device.The dosage range of P+ type impurity about 3 * 10
15To 5 * 10
15Atom/cm
2Between, and with about 4 * 10
15Atom/cm
2Be advisable.Then, use known technology to remove this photoresistance photomask.
Then, at photomask on this substrate top surface to determine the opening above these trench type capacitor zones.That is, cover this bit line and word line with a photoresistance photomask.This BPSG901 is removed from these trench type capacitor zones.In one embodiment, with use the hydrofluoric acid wet etch step optionally with bpsg layer by removing in this raceway groove, and stay these insulating regions 24.In addition, also can use dry etching technology with optionally with bpsg layer by removing in this raceway groove.Then, use known technology to remove this photoresistance photomask.
One to cover on this gate electrode 54 inter-level dielectric 60 be to form with a CVD method, as shown in figure 11.This inter-level dielectric can be a suitable material that comprises TEOS etc.Should be to deposit such as the technology of APCVD, PECVD, LPCVD etc. as the inter-level dielectric of silicon dioxide etc. with one.Certainly, institute's operation technique is decided according to its application.
Then the step of carrying out is, a photoresistance photomask that covers on this substrate top surface zone that comprises the capacitor raceway groove is provided, and covers memory cell joining zone or opening with formation, is determined by etching technique, as shown in figure 11.The example of etching technique comprises plasma etching, reactive ion etching etc.In addition, also can use and select for use such as the wet etch techniques of hydrofluoric acid as the selective etch agent.As shown in the figure, each opening is made for the usefulness that following electrode for capacitors is connected to this fet source or drain region.Also low about 2000 of this substrate surface of this aperture efficiency.This top of exposing source or drain region can not used before next step basically in oxidation.Can use diluted acid dipping or or dry etching technology clean this source or drain region.
Next step is that deposition one covers the following capacitor electrode layer on the exposed parts 36 of this area of isolation and this source or drain region.This time capacitor layer also is provided on the top 1201 of this inter-level dielectric 60, uses the surface area of further increase capacitor unit.The surface area of this increase provides the increase of electric capacity.This time capacitor layer is preferable made with the polysilicon that reduces resistance by mixing through impurity severe.The introducing of this impurity is looked its applicability and is selected multiple angle cloth planting technology for use or mix during forming.In one embodiment, these impurity are the N type, for example, and phosphorus etc.
Last photomask and etching step will descend in the definite capacitor electrode pole plate 26 once of capacitor layer, as shown in figure 12.Capacitor electrode pole plate 26 is to see through this contact opening 36 to be connected to this fet source or drain region 38 under this.Then, utilize known technology to remove this lithography layer.In manufacturing one, before the dielectric, utilize dry etching technology to clean this time capacitor layer.
One capacitor dielectric 30 forms to cover on this time condenser armature.This capacitor dielectric is in order to store the electric charge between condenser armature on this time condenser armature and.In one embodiment, this capacitor dielectric is a high-quality nitride/oxide composite bed.In a preferred embodiment, this capacitor dielectric comprise one cover silicon dioxide layer, on this time condenser armature cover silicon nitride layer on this silicon dioxide layer, and another cover the silicon dioxide layer of this nitride layer.This combination layer provides the characteristic of high storage capacity and is easy to and makes.
Finish this capacitor constructions after, the capacitor layer deposition is to cover on this capacitor dielectric on one.Should go up capacitor layer can be once the severe doping to reduce the polysilicon layer of resistance.Visual its applicability of this polysilicon layer and select multiple angle cloth planting technology for use or during forming, mix.Last photomask and etching step should be gone up capacitor layer and be determined at condenser armature on, as shown in figure 13.By this time condenser armature, this capacitor dielectric and this are gone up condenser armature and are determined this capacitor constructions.As shown in the figure, the capacitor constructions of a part is positioned at this fet and this raceway groove top is long-pending to increase capacitor surface, and using provides big electric capacity.
Thick-layer 14 depositions of BPSG/NSG are to cover on the whole base plate end face.The BPSG/NSG combination layer forms with typical CVD deposition techniques.These BPSG/NSG layers will this below device construction and the metalling (metallization) of top isolate.Use an annealing steps to flow whole this BPSG/NSG layer.Thereby this laminar surface cover is determined the contact opening with photoresistance.Utilize an engraving method and form this contact opening.Then, utilize known technology to remove this photoresistance.
One the first metal layer forms covering on these layers, and is formed in these contact openings so that be electrically connected.Photomask and etched step are planned the pattern of this first metal layer 16 in the utilization, as shown in figure 14.One intermetallic metal oxide skin(coating), 17 depositions are with on the first metal layer 16 that covers this pattern formation.This intermetallic metal oxide skin(coating) is with typical C VD deposition techniques.
Utilize known photoresistance and etching technique that one channel pattern (via pattern) is determined in this intermetallic metal oxide skin(coating).This channel pattern has the opening that supplies the first metal layer and second metal interlevel to electrically contact.Overlaying on this intermetallic metal oxide, and spraying plating is in these passages with this second metal level spraying plating.The step of one planning pattern is determined this second metal level.
Remaining manufacturing step comprises the deposition of the passivation of a silicon nitride containing layer and silicon dioxide layer.The pattern of planning this passivation layer engages routing (bondingpad) district's opening and fuse (fuse) opening to form.This opening is a mat etching technique and making.Cover on whole surface with polyimides then.Last plan the pattern on the surface that this is capped with photomask on one and etching step again.After pattern formed, slaking should the lining surface.Further step comprises brilliant figure ordering, assembling, test etc.
Though above explanation is the whole detailed description of specific embodiment, also applicable various modifications, deformation structure and equivalent manners.As, though above-mentioned explanation is the basis that is configured to illustrate with DRAM, can also waits with SRAM and realize the present invention.
Therefore, should be with above-mentioned explanation and embodiment qualification as the scope of the invention.Scope of the present invention should be determined by appended scope.