CN112802521A - Method for curing resistive random access memory - Google Patents
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- CN112802521A CN112802521A CN201911106194.2A CN201911106194A CN112802521A CN 112802521 A CN112802521 A CN 112802521A CN 201911106194 A CN201911106194 A CN 201911106194A CN 112802521 A CN112802521 A CN 112802521A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000032683 aging Effects 0.000 claims description 16
- 230000005070 ripening Effects 0.000 claims description 16
- 230000001351 cycling effect Effects 0.000 claims description 15
- 230000035800 maturation Effects 0.000 claims description 10
- 230000000875 corresponding effect Effects 0.000 claims description 8
- 230000004044 response Effects 0.000 claims description 7
- 230000002596 correlated effect Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
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- 238000004519 manufacturing process Methods 0.000 description 1
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- 230000006386 memory function Effects 0.000 description 1
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- 238000007493 shaping process Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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Abstract
The invention provides a method for curing a Resistive Random Access Memory (RRAM), which comprises the following steps: obtaining a first RRAM, wherein the first RRAM comprises a plurality of memory cells; performing a forming operation and a first reset operation on the first RRAM to form a plurality of specific memory cells in the memory cells; reading the specific number of the specific memory cells, and determining a curing cycle parameter according to the specific number; performing a curing operation on the first RRAM based on the curing cycle parameter to cure the first RRAM to a second RRAM.
Description
Technical Field
The present invention relates to a method for manufacturing a Resistive Random Access Memory (RRAM), and more particularly, to a method for aging a RRAM.
Background
RRAM is a nonvolatile memory in which RRAM cells each include an upper electrode plate, a lower electrode plate, and a dielectric material layer sandwiched between the upper and lower electrode plates. The layer of dielectric material is typically insulating, and conductive paths (commonly referred to as Conductive Filaments (CF)) can be formed through the layer of dielectric material by applying a suitable voltage across the upper electrode plate to shape the memory cell. Once formed, the conductive filaments can be reset (reset) by applying an appropriate voltage across the upper electrode plate (i.e., causing portions of the conductive filaments to break or rupture, resulting in a High Resistance State (HRS) on the RRAM cell.
Thereafter, the RRAM cell may be subjected to a set operation (set) by applying an appropriate voltage across the upper electrode plate (i.e., the conductive wire is reformed, resulting in a Low Resistance State (LRS) on the RRAM cell). The resistance state (LRS or HRS) of the RRAM can be controlled by repeated set and reset operations, and the LRS and HRS can be used to indicate a "0" or "1" digital signal, thereby providing related memory functions.
However, RRAMs have been subject to data retention (data retention) problems. Generally, the LRS channel formation of RRAM is more mature and generally better meets the relevant reliability criteria after process development. However, for HRS channels, the lattice arrangement of oxygen vacancies is often changed or diffused by thermal energy, so that some of the oxygen vacancies are not connected, and the current is still maintained at a high level. Also, since the design trend of the RRAM in recent years tends to be low power design, it is an important issue for those skilled in the art how to design a mechanism capable of establishing a stable channel in the RRAM.
Disclosure of Invention
The present invention provides a matured RRAM, which can solve the above problems.
The invention provides a method for curing a resistance random access memory, which comprises the following steps: obtaining a first resistance random access memory, wherein the first resistance random access memory comprises a plurality of memory cells; performing a forming operation and a first reset operation on the first resistance random access memory to form a plurality of specific memory cells in the memory cells, wherein a memory cell current of each specific memory cell is greater than a preset threshold value; reading the specific number of the specific memory cells, and determining a curing cycle parameter according to the specific number; a maturing operation is performed on the first resistance random access memory based on the maturing cycle parameter to mature the first resistance random access memory into a second resistance random access memory.
Based on the above, the present invention can obtain the specific number of the specific memory cells after the forming operation and the first reset operation are performed on the RRAM, and accordingly adaptively determine the aging cycle number of the aging operation. Therefore, the channel structure in each memory cell can be more stable, and the retention performance of RRAM data is improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a flow chart illustrating a method of maturing RRAM in accordance with one embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory cell structure with/without maturing operation according to an embodiment of the present invention
The reference numbers illustrate:
210. 220, and (2) a step of: memory cell
S110 to S160: step (ii) of
Detailed Description
Referring to fig. 1, a flowchart of a method for maturing RRAM according to an embodiment of the present invention is shown. First, in step S110, a first RRAM may be acquired. In the present embodiment, the first RRAM is, for example, an unprocessed RRAM that has not undergone any shaping operation, setting operation, and resetting operation, or any RRAM that can be an implementation object of the method of the present invention, but the present invention is not limited thereto. Moreover, the first RRAM may include a plurality of memory cells (or memory cells), and the structure of each memory cell may refer to the aforementioned RRAM cell, so the related details are not repeated herein.
Next, in step S120, a forming operation and a first reset operation may be performed on the first RRAM to form a plurality of specific memory cells in the memory cells. In one embodiment, after performing the forming operation and the first reset operation on the first RRAM, the cell current of each memory cell is measured, and whether the cell circuit of each memory cell fails (fail) is determined, for example, whether the cell circuit of each memory cell is greater than a predetermined threshold (e.g., 3 μ a). One or more memory cells having a cell current greater than a predetermined threshold may then be defined as the particular memory cell.
In one embodiment, if the cell current of a memory cell does not decrease sufficiently in response to the first reset operation, it indicates that the resistance state of the memory cell is not correspondingly switched to HRS. Thus, this memory cell (i.e., the particular memory cell) may also be referred to as a fail bit
Thereafter, in step S130, the specific number of the specific memory cells can be read, and the ripening cycle parameter is determined according to the specific number. In the embodiment, the specific number of the specific memory cells may be counted, and in the case that the specific memory cells may be referred to as error bits, the specific number may be referred to as a Fail Bit Count (FBC), but the invention is not limited thereto. In other words, the concept of obtaining the specific number can be understood as obtaining the FBC of the first RRAM (after the first reset operation), but the invention is not limited thereto.
In embodiments of the invention, the maturation cycle parameters may be positively correlated to a specific amount. That is, the larger the number of specific memory cells, the higher the ripening cycle parameter.
In a first embodiment, the above-described maturation cycle parameter may be characterized as a number of maturation cycles. In this case, a specific ratio of the specific number to the total number of the memory cells in the first RRAM may be obtained first, and this specific ratio may be understood as a ratio of the specific memory cells in all the memory cells, but may not be limited thereto. Thereafter, it can be determined whether the specific ratio is greater than a first threshold (e.g., 80%). If so, it means that a significant number of memory cells in the first RRAM are not successfully switched to HRS, and therefore the number of maturing cycles can be set to the first value (e.g., 50 times) correspondingly.
On the other hand, if the specific ratio is not greater than the first threshold, it can be determined whether the specific ratio is less than the first threshold and greater than a second threshold (e.g., 50%). If so, it means that a certain number of memory cells in the first RRAM are not successfully switched to HRS, and therefore the number of maturing cycles can be set to a second value (e.g. 20 times) slightly lower than the first value correspondingly.
In another embodiment, if the specific ratio is not less than the first threshold and is greater than the second threshold, it can be determined whether the specific ratio is less than the second threshold and is greater than a third threshold (e.g., 20%). If so, it means that most of the memory cells in the first RRAM have been successfully switched to HRS, so the number of maturing cycles can be set to a third value (e.g. 0 times) slightly lower than the second value.
In addition, in the second embodiment, the curing cycle parameter can be further characterized as a curing voltage. In this case, a specific ratio of the specific number to the total number of memory cells in the first RRAM may be obtained first. Thereafter, it can be determined whether the specific ratio is greater than a first threshold (e.g., 80%). If so, it means that a significant number of memory cells in the first RRAM are not successfully switched to HRS, and therefore the maturing voltage can be set to the first voltage (e.g., a number greater than 0.4V) accordingly.
On the other hand, if the specific ratio is not greater than the first threshold, it can be determined whether the specific ratio is less than the first threshold and greater than a second threshold (e.g., 50%). If so, it means that a certain number of memory cells in the first RRAM are not successfully switched to HRS, and therefore the maturing voltage can be correspondingly set to a second voltage (e.g., a value higher than 0.2V) slightly lower than the first voltage.
In another embodiment, if the specific ratio is not less than the first threshold and is greater than the second threshold, it can be determined whether the specific ratio is less than the second threshold and is greater than a third threshold (e.g., 20%). If so, it means that most of the memory cells in the first RRAM are successfully switched to HRS, so the maturing voltage can be set to a third voltage (e.g., a value higher than 0.1V) slightly lower than the second voltage.
Next, in step S140, a maturing operation may be performed on the first RRAM based on the maturing cycle parameter to mature the first RRAM into a second RRAM.
In the first embodiment, one ripening operation may sequentially include a set operation and a reset operation (which may be abbreviated as a pre-cycle) performed based on a ripening voltage, wherein the ripening voltage may take a voltage value higher than a general operating voltage. That is, after determining the ripening cycle parameter (i.e., the number of ripening cycles) through step S130, a corresponding number of pre-cycles may be performed on the first RRAM to ripen the first RRAM into the second RRAM. For example, if the number of cure cycles is 50, the first RRAM may be pre-cycled 50 times based on the cure voltage accordingly. For another example, if the number of aging cycles is 20, the first RRAM may be pre-cycled 20 times based on the aging voltage accordingly, but the present invention may not be limited thereto.
In the second embodiment, after determining the maturing cycle parameter (i.e., maturing voltage) through step S130, a pre-cycle corresponding to a preset number of times may be performed on the first RRAM to mature the first RRAM into the second RRAM. For example, if the maturing voltage is 0.4V and the preset number of times is 10, the first RRAM may be pre-cycled 10 times based on the maturing voltage having a value of 0.4V, accordingly. For another example, if the maturing voltage is 0.2V and the preset number of times is 10, the first RRAM may be pre-cycled 10 times based on the maturing voltage having a value of 0.2V, accordingly, but the present invention may not be limited thereto.
In view of the above, the present invention can obtain the specific number of the specific memory cells after the forming operation and the first reset operation of the RRAM, and adaptively determine the aging cycle parameters of the aging operation. When the specific amount is larger, a higher maturation cycle parameter (e.g. a higher maturation voltage or number of maturation cycles) is used, whereas a lower maturation cycle parameter is used. Therefore, the channel structure (i.e. CF structure) in each memory cell can be more stable, thereby improving the performance of RRAM data retention.
Further, after step S140, step S150 may be sequentially performed to perform a pre-loop operation on the second RRAM based on the pre-loop voltage to convert the second RRAM into a third RRAM. In this embodiment, the pre-cycling voltage may be the same as the normal operating voltage, i.e., a voltage less than the aging voltage. In one embodiment, the difference between the slaking voltage and the pre-cycling voltage may be greater than 0.2V. In another embodiment, the ripening voltage may be up to 5% higher than the pre-cycling voltage, but may not be limited thereto.
In one embodiment, the pre-cycling operation may sequentially include a set operation and a reset operation performed based on the pre-cycling voltage, for example. That is, after the first RRAM is aged into the second RRAM by performing the aging operation corresponding to the number of aging cycles based on the higher aging voltage, the second RRAM may be pre-cycled again based on the lower pre-cycling voltage to convert the second RRAM into the third RRAM.
Thereafter, in step S160, a corresponding write operation or read operation may be performed on the third RRAM according to the write command or the read command. That is, after the third RRAM is obtained through steps S110 to S150, the third RRAM can be used for performing general write and read operations.
In order to make the concept of the present invention easier to understand, the following description is further made with the aid of FIG. 2. FIG. 2 is a schematic diagram of a memory cell structure with/without maturation operation according to an embodiment of the present invention.
In the present embodiment, it is assumed that the memory cell 210 is not subjected to the aging process proposed by the present invention, and the memory cell 220 is subjected to the aging process proposed by the present invention. As can be seen in fig. 2, after the memory cell 210 is fired (bake), a relatively weak CF structure is formed due to the relatively loose distribution of the oxygen vacancy lattice (shown as circles) in the CF. In this case, the CF in the memory cell 210 is likely to cause the oxygen vacancy lattice to move easily due to thermal energy, thereby increasing the possibility of CF disconnection. Therefore, the memory cell 210 will perform poorly in terms of High Temperature Data Retention (HTDR).
On the other hand, as can be seen from fig. 2, after the memory cell 220 is fired, a more robust CF structure is formed because the oxygen vacancy lattice distribution in CF is denser. In this case, the CF in the memory cell 220 is less likely to cause oxygen vacancy lattice movement due to thermal energy, thereby reducing the possibility of CF disconnection. Therefore, the memory cell 220 will perform better in terms of HTDR.
In summary, the present invention can obtain a specific number of specific memory cells (e.g., FBC) after performing the forming operation and the first reset operation on the RRAM, and adaptively determine the number of aging cycles of the aging operation (which may be positively correlated to the FBC, for example). Therefore, the channel structure in each memory cell can be more stable, and the retention performance of RRAM data is improved.
In addition, the invention can determine the appropriate aging cycle number according to the specific number of the specific memory cells, thereby generating the RRAM with a better CF structure with better efficiency. In addition, the method of the present invention is simple and easy to design, and thus is suitable for designing RRAM chip to perform self-test and repair of RRAM, and the process will not affect the performance of subsequent write/read operations except aged memory cells.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (17)
1. A method of maturing a resistive random access memory, comprising:
obtaining a first resistance random access memory, wherein the first resistance random access memory comprises a plurality of memory cells;
performing a forming operation and a first reset operation on the first resistance random access memory to form a plurality of specific memory cells in the plurality of memory cells, wherein the memory cell current of each specific memory cell is greater than a preset threshold value;
reading the specific number of the specific storage units, and determining a curing cycle parameter according to the specific number;
performing a maturing operation on the first resistive random access memory based on the maturing cycle parameter to mature the first resistive random access memory into a second resistive random access memory.
2. The method of claim 1, wherein the ripening cycle parameter is a number of ripening cycles, and performing the ripening operation on the first resistance random access memory based on the ripening cycle parameter comprises:
performing the maturing operation corresponding to the number of maturing cycles on the first resistance random access memory based on a maturing voltage.
3. The method of claim 2, further comprising:
performing a pre-cycling operation on the second resistive random access memory based on a pre-cycling voltage to convert the second resistive random access memory into a third resistive random access memory.
4. The method of claim 2, wherein the maturing operation sequentially comprises a set operation and a reset operation performed based on the maturing voltage.
5. The method of claim 3, wherein the curing voltage is greater than the pre-cycling voltage.
6. The method of claim 3, wherein the difference between the pre-cycling voltage and the aging voltage is greater than 0.2V.
7. The method of claim 3, wherein the maturation voltage is up to 5% greater than the pre-cycling voltage.
8. The method of claim 3, wherein the pre-cycling operations sequentially comprise a set operation and a reset operation performed based on the pre-cycling voltage.
9. The method of claim 2, wherein determining the ripening cycle parameter in dependence on the specified amount comprises:
obtaining a specific ratio of the specific number to a total number of the plurality of memory cells;
setting the number of curing cycles as a first value in response to the specific proportion being greater than a first threshold value;
and setting the number of the curing cycles to be a second value in response to the specific ratio being smaller than the first threshold value and larger than a second threshold value, wherein the first value is larger than the second value.
10. The method of claim 9, further comprising:
and setting the number of curing cycles to be a third value in response to the specific ratio being smaller than the second threshold value and larger than a third threshold value, wherein the third value is smaller than the second value.
11. The method of claim 3, further comprising:
and executing corresponding write operation or read operation on the third resistance random access memory according to the write instruction or the read instruction.
12. The method of claim 1, wherein the maturing cycle parameter is a maturing voltage, and performing the maturing operation on the first resistive random access memory based on the maturing cycle parameter comprises:
performing the ripening operation on the first resistance random access memory corresponding to a preset number of times based on the ripening voltage.
13. The method of claim 12, wherein determining the ripening cycle parameter in dependence on the specified amount comprises:
obtaining a specific ratio of the specific number to a total number of the plurality of memory cells;
setting the curing voltage as a first voltage in response to the specific proportion being greater than a first threshold value;
and setting the curing voltage to be a second voltage in response to the specific ratio being smaller than the first threshold and larger than a second threshold, wherein the first voltage is larger than the second voltage.
14. The method of claim 13, further comprising:
in response to the specific ratio being less than the second threshold and greater than a third threshold, setting the maturing voltage to a third voltage, wherein the third voltage is less than the second voltage.
15. The method of claim 13, further comprising:
performing a pre-cycling operation on the second resistive random access memory based on a pre-cycling voltage to convert the second resistive random access memory into a third resistive random access memory.
16. The method of claim 15, further comprising:
and executing corresponding write operation or read operation on the third resistance random access memory according to the write instruction or the read instruction.
17. The method of claim 1, wherein the maturation cycle parameter is positively correlated to the specific amount.
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