CN116529866A - 用于集成电路封装的通用无电活性装置 - Google Patents

用于集成电路封装的通用无电活性装置 Download PDF

Info

Publication number
CN116529866A
CN116529866A CN202180071393.3A CN202180071393A CN116529866A CN 116529866 A CN116529866 A CN 116529866A CN 202180071393 A CN202180071393 A CN 202180071393A CN 116529866 A CN116529866 A CN 116529866A
Authority
CN
China
Prior art keywords
integrated circuit
layer
substrate
metallization layer
attachment surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180071393.3A
Other languages
English (en)
Inventor
X·布吕诺
T·戈瑟兰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN116529866A publication Critical patent/CN116529866A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H01L2224/32058—Shape in side view being non uniform along the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32106—Disposition relative to the bonding area, e.g. bond pad the layer connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

可以采用通用虚设装置，而不是利用匹配集成电路封装的电子基板的凸块层的虚设装置，来制作集成电路封装。在一个实施例中，通用虚设装置可以包括具有附接表面的装置基板和位于附接表面上的金属化层，其中，金属化层用于形成与集成电路封装的电子基板的连接。在具体实施例中，金属化层可以是在整个附接表面上延伸的单一结构。在另一个实施例中，金属化层可以被图案化以实现通用虚设装置与电子基板之间的间隙控制。

Description

用于集成电路封装的通用无电活性装置
优先权要求
本申请要求享有于2020年11月20日提交的名称为“用于集成电路封装的通用无电活性装置”的序列号17/100,449的美国专利申请的优先权，并且其通过引用以其全文并入本申请。
技术领域
本说明书的实施例一般涉及集成电路封装或组装制作的领域，并且更具体地，涉及无电活性(electrically inactive)或“虚设”装置在集成电路封装或组装的构造中的使用。
背景技术
集成电路行业正在不断地努力生产更快、更小且更薄的电子装置和封装，以用于各种电子产品中，这些电子产品包括但不限于计算机服务器和便携式产品，例如，便携式计算机、电子平板电脑、蜂窝电话和数码相机等。
实现这些目标的一种途径是对集成电路装置进行更紧密的封装。被称为堆叠复合管芯的一种这样的布置包括附接到电子基板的多个无源或有源的集成电路装置，其中电子基板上的模制材料层基本上围绕或环绕多个集成电路装置。尽管这样的集成电路封装可能是对集成电路装置进行封装的有效方式，但是其具有比单片硅更高的翘曲，因为集成电路装置本身之间以及模制材料层与电子装置之间的热膨胀系数不同。这样的翘曲可能导致模制材料层的分层和/或开裂，这可能导致集成电路封装的故障。来自温度梯度的翘曲可能发生在集成电路封装的操作和/或制造过程(例如来自集成电路封装到电子板的热压接合)的温度循环期间。
一种防止翘曲或将翘曲最小化的技术是通过优化集成电路装置的位置以及使用无电活性或虚设装置。无电活性或虚设装置仅是惰性半导体基板。换言之，如本领域技术人员将理解的，无电活性或虚设装置在集成电路封装内不执行电功能，并且可以仅是用于匹配集成电路封装的有源集成电路装置中使用的材料的无电路半导体材料。
一般地，如本领域技术人员将理解的，为了准备将虚设装置附接到电子板，像所有有源集成电路装置一样，针对每个集成电路封装平面图并且经过所有标准步骤(包括但不限于平坦化、材料沉积、光刻循环步骤、镀覆等)来制作虚设装置，以便匹配无电活性/虚设装置与电子板之间的焊料凸块层。然后无电活性/虚设装置被制备并且连同有源集成电路装置一起附接，包括但不限于助焊剂/焊料形成、热压接合、底部填充等。然而，以这种方式制备虚设装置增加了每个产品(即，集成电路封装)所需的流片和掩模的数量，这增加了复杂度并降低了集成电路封装的制作中的布局改变的灵活性。
附图说明
在说明书的结论部分中特别指出并且清楚地要求保护本公开的主题。结合附图，根据以下描述和所附权利要求，本公开的前述特征和其他特征将变得更加充分地显而易见。应当理解，附图仅描绘了根据本公开的若干实施例，并且因此不应被认为是对其范围的限制。将通过使用附图以额外的具体性和细节来描述本公开，使得可以更容易地确定本公开的优点，其中：
图1是根据本说明书的一个实施例的通用虚设装置的侧视横截面图。
图2是图1的插入物2的视图，示出了根据本说明书的实施例的无活性装置基板上的堆叠金属化层。
图3是根据本说明书的实施例的集成电路封装的侧视横截面图。
图4是根据本说明书的实施例的通用虚设装置的斜视图。
图5是根据本说明书的实施例的具有图案化的金属化层的通用虚设装置的斜视图。
图6是根据本说明书的实施例的通用虚设装置的图案化的金属化层的平面图。
图7是根据本说明书的实施例的制作集成电路封装的工艺的流程图。
图8是根据本说明书的一个实施例的电子系统。
具体实施方式
在以下具体实施方式中，参考了附图，附图以说明的方式示出了在其中可以实践所要求保护的主题的具体实施例。这些实施例被足够详细地描述以使本领域技术人员能够实践本主题。应当理解，尽管各个实施例不同，但它们不一定是相互排斥的。例如，本文中结合一个实施例描述的特定特征、结构或特性可以在其他实施例内实施，而不脱离所要求保护的主题的精神和范围。在本说明书内对“一个实施例”或“实施例”的引用表示结合该实施例描述的特定特征、结构或特性被包括在涵盖于本说明书内的至少一个实施方式中。因此，短语“一个实施例”或“在实施例中”的使用不一定是指相同的实施例。另外，应当理解，可以修改每个公开的实施例内的各个元件的位置或布置，而不脱离所要求保护的主题的精神和范围。因此，以下具体实施方式不应当被理解为是限制性的，并且本主题的范围仅由适当解释的所附权利要求以及所附权利要求所赋予的等同物的全部范围来限定。在附图中，遍及若干视图，相同的附图标记指代相同或相似的元件或功能性，并且其中描绘的元件不一定是彼此成比例的，而是可以将各个元件放大或缩小以便更容易地理解本说明书的上下文中的元件。
如本文所用，术语“在……之上”、“到”、“在……之间”和“在……上”可以指一个层相对于其他层的相对位置。在另一层“之上”或“上”或接合“到”另一层的一个层可以直接与其他层接触或可以具有一个或多个居间层。在层“之间”的一个层可以直接与这些层接触或者可以具有一个或多个居间层。
术语“封装”一般是指一个或多个管芯的自包含式载体，其中，管芯附接到封装基板，并且为了保护可以被包封，其中，在管芯与位于封装基板的外部部分上的引线、引脚或凸块之间具有集成的或导线接合的互连。封装可以含有单一管芯或者多个管芯，从而提供具体功能。封装通常安装在印刷电路板上，以用于与其他封装的集成电路和分立部件互连，从而形成更大的电路。
这里，术语“核心的”一般是指构建在包括非柔性硬质材料的板、卡或晶圆上的集成电路封装的基板。典型地，小的印刷电路板用作核心，集成电路装置和分立的无源部件可以焊接在核心上。典型地，核心具有从一侧延伸到另一侧的过孔，从而允许核心的一侧上的电路系统直接耦合到核心的相对侧上的电路系统。核心还可以充当用于构建导体层和电介质材料层的平台。
这里，术语“无核心的”一般是指没有核心的集成电路封装的基板。由于与高密度互连相比，贯穿过孔具有相对大的尺寸和间距，所以缺乏核心允许更高密度的封装架构。
这里，术语“连接盘侧(land side)”，如果在本文中使用，一般是指集成电路封装的基板的最接近于附接到印刷电路板、母板或其他封装的平面的一侧。这与术语“管芯侧”形成对比，“管芯侧”是集成电路封装的基板的附接管芯或多个管芯的一侧。
这里，术语“电介质”一般是指构成封装基板的结构的任何数量的非导电材料。出于本公开的目的，电介质材料可以作为层压膜的层或者作为模制在安装于基板上的集成电路管芯之上的树脂而被并入到集成电路封装中。
这里，术语“金属化”一般是指在封装基板的电介质材料之上形成并且穿过该电介质材料的金属层。金属层一般被图案化，从而形成金属结构(例如迹线和接合焊盘)。对封装基板的金属化可以被限制到单一层或在由电介质的层分隔开的多个层中。
这里，术语“接合焊盘”一般是指终止集成电路封装和管芯中的集成的迹线和过孔的金属化结构。术语“焊料焊盘”有时可以代替“接合焊盘”，并且具有相同的含义。
这里，术语“焊料凸块”一般是指形成在接合焊盘上的焊料层。焊料层典型地具有圆形形状，因此被称为术语“焊料凸块”。
这里，术语“基板”一般是指包括电介质和金属化结构的平面平台。基板机械地支撑并且电耦合单一平台上的一个或多个IC管芯，其中一个或多个IC管芯被可模制的电介质材料包封。基板一般包括作为两侧上的接合互连的焊料凸块。基板的一般被称为“管芯侧”的一侧包括用于芯片或管芯接合的焊料凸块。基板的一般被称为“连接盘侧”的相对侧包括用于将封装接合到印刷电路板的焊料凸块。
这里，术语“组装”一般是指将一组零件组合为单一功能单元。零件可以是分离的，并且被机械地组装到功能单元中，在功能单元中，零件可以是可移除的。在另一实例中，零件可以被永久地接合在一起。在一些实例中，零件被集成在一起。
在整个说明书中并且在权利要求书中，术语“连接”表示在被连接的事物之间的直接连接，例如电、机械或磁连接，而没有任何中间装置。
术语“连接”表示直接或间接连接，例如连接的事物之间的直接电、机械、磁或流体连接，或者通过一个或多个无源或有源中间装置的间接连接。
术语“电路”或“模块”可以指被布置为彼此协作以提供期望的功能的一个或多个无源和/或有源部件。术语“信号”可以指至少一个电流信号、电压信号、磁信号或数据/时钟信号。“一”和“所述”的含义包括复数引用。“在……中”的含义包括“在……中”和“在……上”。
竖直取向是在z方向上，并且应当理解，对“顶部”、“底部”、“上方”和“下方”的复述是指具有通常含义的z维度上的相对位置。然而，应当理解，实施例不必限制于图中所示的取向或配置。
术语“基本上”、“接近”、“近似”、“接近”和“大约”一般是指在目标值的+/-10％内(除非特别说明)。除非另有说明，否则使用序数形容词“第一”、“第二”和“第三”等来描述共同对象仅指示正被引用的类似对象的不同实例，并且不旨在暗示如此描述的对象必须在时间上、空间上、在等级上或以任何其他方式处于给定序列中。
出于本公开的目的，短语“A和/或B”和“A或B”表示(A)、(B)或(A和B)。出于本公开的目的，短语“A、B和/或C”表示(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或者(A、B和C)。
标记为“横截面的”、“轮廓”和“平面”的视图对应于笛卡尔坐标系内的正交平面。因此，横截面视图和轮廓视图是在x-z平面中截取的，并且平面视图是在x-y平面中截取的。典型地，在x-z平面中的轮廓视图是横截面视图。在适当的情况下，附图用轴标记以指示图的取向。
出于本公开的目的，术语“高深宽比”表示结构具有大于大约2的高度(z方向)与宽度(x方向)之比。
本说明书的实施例涉及一种用于集成电路封装的通用虚设装置以及用于形成该通用虚设装置的工艺，而不是利用匹配集成电路封装的电子基板的凸块层的虚设装置。在一个实施例中，通用虚设装置可以包括具有附接表面的装置基板和位于附接表面上的金属化层，其中，利用金属化层来形成与集成电路封装的电子基板的连接。在具体实施例中，金属化层可以是在整个附接表面上延伸的单一结构。在另一个实施例中，金属化层可以被图案化以实现通用虚设装置与电子基板之间的间隙控制。
图1示出了通用虚设装置110，其包括具有附接表面122和相对的背侧表面124的无活性装置基板120以及位于无活性装置基板120的附接表面122上的金属化层130。在本说明书的一个实施例中，无活性装置基板120可以包括半导体材料，其包括但不限于硅、锗等。在本说明书的另一个实施例中，金属化层130可以用“背侧金属化”工艺形成。如本领域技术人员将理解的，背侧金属化一般形成于集成电路封装中的有源集成电路装置的背侧表面上以增强导热性。出于本说明书的目的，术语“无活性装置基板”被定义为表示不具有电或电路系统功能的基板。
在本说明书的一个实施例中，如图2所示，金属化层130可以包括位于无活性装置基板120上的层(被示出为第一层132、第二层134、第三层136和第四层138)的堆叠体。如将要讨论的，这些层可以用于粘附和/或阻挡目的，其中最外或第四层138用于确保良好的润湿和对焊料(未示出)的附接强度，焊料将用于将通用虚设装置110附接到电子基板(未示出)。如此，在本说明书的一个实施例中，最外或第四层138可以是适当的低氧化金属，其包括但不限于金、银和镍。这些层，例如第一层132、第二层134、第三层136和第四层138可以通过任何适当的方法形成，所述方法包括但不限于电子束蒸发、溅射沉积、闪速涂覆等。当然，可以理解，如将讨论的，金属化层130可以是任何数量的层，并且如果单一层既可以粘附到无活性装置基板120又可以为焊料附接提供可润湿表面，则金属化层130可以只是一层。
在本说明书的具体实施例中，第一层132可以是电介质材料，例如氮化硅。在本说明书的另一个具体实施例中，第二层134可以包括钛。在本说明书的又一个具体实施例中，第三层136可以是镍钒合金。在本说明书的再一个具体实施例中，最后或第四层138可以是金。
图3示出了根据本说明书的实施例的具有以一般被称为倒装芯片或受控塌陷芯片连接(“C4”)构造的构造附接到电子基板150的至少一个集成电路装置(被示出为第一集成电路装置1401和第二集成电路装置1402)和至少一个通用虚设装置110的集成电路封装100。
第一集成电路装置1401和第二集成电路装置1402可以是任何适当的有源装置，其包括但不限于微处理器、芯片组、图形装置、无线装置、存储器装置、专用集成电路、它们的组合、它们的堆叠体等。如图所示，第一集成电路装置1401和第二集成电路装置1402均可以具有附接表面或第一表面142。
在图3所示的本说明书的实施例中，第一集成电路装置1401、第二集成电路装置1402和通用虚设装置110可以采用多个装置到基板互连160附接到电子基板150。在本说明书的一个实施例中，装置到基板互连160可以在位于电子基板150的第一表面152上的接合焊盘156与位于第一集成电路装置1401和第二集成电路装置1402的第一表面142上的接合焊盘148之间，以及在位于电子基板150的第一表面152上的接合焊盘156与通用虚设装置110的金属化层130之间延伸。
在一个实施例中，装置到基板互连160可以是由锡、铅/锡合金(例如，63％锡/37％铅焊料)和高锡含量合金(例如，90％或更多的锡，诸如锡/铋合金、共晶锡/银合金、三元锡/银/铜合金、共晶锡/铜合金和类似合金)形成的焊料球。装置到基板互连160可以与它们相应的有源集成电路装置(即第一集成电路装置1401和第二集成电路装置1402)内的集成电路系统(未示出)电通信。
在第一集成电路装置1401与电子基板150之间、第二集成电路装置1402与电子基板150之间以及通用虚设装置110与电子基板150之间可以设置电绝缘底部填充材料170，例如环氧树脂。如本领域技术人员将理解的，底部填充材料170可以作为粘性液体分配在集成电路装置1401和1402的第一表面142与电子基板150之间，以及通用虚设装置110的金属化层130与电子基板150之间，并且然后采用固化工艺硬化。底部填充材料170也可以是本领域已知的模制底部填充材料。如本领域技术人员将理解的，底部填充材料170可以提供结构完整性并且可以防止污染。
电子基板150可以是任何适当的装置，包括无源装置(例如，内插器、电路板等)、有源装置((例如，具有集成电路系统)，例如微处理器、芯片组、图形装置、无线装置、存储器装置、专用集成电路、它们的组合、它们的堆叠体等)，或者如图3所示嵌入在无源电子基板150中的有源装置190的组合。
当电子基板150完全或部分是无源装置时，其可以包括多个电介质材料层(未示出)，其可以包括堆积膜和/或阻焊剂层，并且可以由适当的电介质材料组成，包括但不限于双马来酰亚胺三嗪树脂、阻燃4级材料、聚酰亚胺材料、二氧化硅填充的环氧树脂材料、玻璃增强环氧树脂材料等，以及低k和超低k电介质(介电常数小于大约3.6)，包括但不限于掺碳电介质、掺氟电介质、多孔电介质和有机聚合物电介质等。电子基板150还可以包括延伸穿过电子基板150的导电布线158或“金属化部”(以虚线示出)。电子基板150的第一表面152上的接合焊盘156可以与导电布线158电接触，并且导电布线158可以延伸穿过电子基板150并且电连接到电子基板150的第二表面154上的接合焊盘162。然而，由于通用虚设装置110是无电活性的，通用虚设装置110附接到的接合焊盘156不需要附接到导电布线158。
如本领域技术人员将理解的，导电布线158可以是导电迹线(未示出)和延伸穿过多个电介质材料层(未示出)的导电过孔(未示出)的组合。这些导电迹线和导电过孔在本领域中是公知的，并且为了清楚起见未在图3中示出。导电迹线和导电过孔可以由任何适当的导电材料制成，包括但不限于金属(例如铜、银、镍、金、铝)、它们的合金等。如本领域技术人员将理解的，电子基板150可以是有核心的基板或无核心的基板。
如本领域技术人员将理解的，电子基板150可以将集成电路装置接合焊盘148的精细间距(接合焊盘之间的中心到中心距离)重新布线为电子基板150的第二表面154上的接合焊盘162的相对较宽的间距。在本说明书的一个实施例中，外部互连164可以设置在位于电子基板150的第二表面154上的接合焊盘162上。外部互连164可以是任何适当的导电材料，包括但不限于金属填充的环氧树脂和焊料，例如，锡、铅/锡合金(例如，63％锡/37％铅焊料)和高锡含量合金(例如，90％或更多的锡，例如，锡/铋合金、共晶锡/银合金、三元锡/银/铜合金、共晶锡/铜合金和类似合金)。外部互连164可以用于将集成电路组件100附接到外部基板(未示出)，例如，母板。
当电子基板150是有源装置时，其可以是任何适当的装置，包括但不限于微处理器、芯片组、图形装置、无线装置、存储器装置、专用集成电路、它们的组合、它们的堆叠体等。第一集成电路装置1401和第二集成电路装置1402可以电附接到位于电子基板150(作为有源装置)的第二表面154上的贯穿硅过孔(未示出)。贯穿硅过孔在本领域中是公知的，并且为了清楚和简洁的目的将不在本文中讨论或图示。
如图3中进一步所示，可以在电子基板150上以及在第一集成电路装置1401、第二集成电路装置1402和通用虚设装置110之上形成模制材料层180。模制材料层180可以是任何适当的材料，例如环氧树脂。如本领域技术人员将理解的，模制材料层180可以提供结构完整性并且可以防止污染。
在本说明书的一个实施例中，如图4所示，金属化层130可以在无活性装置基板120的整个附接表面上延伸。在本说明书的另一个实施例中，如图5所示，可以在无活性装置基板120的附接表面122上对金属化层130进行图案化。在本说明书的具体实施例中，可以通过形成在无活性装置基板120的整个附接表面122上的金属化层130(如图4所示)，然后例如通过激光烧蚀来烧蚀掉金属化层130的选定部分以形成期望的图案，从而实现图案化。用于形成图5的图案化的金属化层130的进一步具体实施例可以包括在形成金属化层130之前在无活性装置基板120的附接表面122上对油墨坝状物(ink dam)(未示出)进行图案化，在形成金属化层130之前在无活性装置基板120的附接表面122上对阻焊剂材料(未示出)进行图案化，并且使用光掩模和临时镀覆抗蚀剂在选定区域上镀覆金属化层130。如本领域技术人员将理解的，如图6所示，图案之间的形状、间距P和间隔S将影响“芯片间隙”，例如金属化层130与电子基板150的第一表面152之间的距离D(见图3)。通过使用图案化的芯片间隙控制在本领域中是公知的，并且为了清楚和简明的目的将不在本文中讨论。此外，应当理解，电子基板150上的接合焊盘156的任何图案与虚设装置110的金属化层130的任何图案不必彼此相关，并且均可以基于便利来独立设计或优化。此外，如本领域的技术人员将理解的，虚设管芯110内的区可以具有金属化层130的图案化的区域，基于这些独立的图案如何排列，金属化层130的图案化的区域具有相对稀疏的数量、相对密集的数量或者甚至与电子基板150没有连接。
与以有源集成电路装置的方式制作的虚设装置相比，本说明书的实施例可以具有明显的优势。本说明书的实施例具有通用设计，这表示如本领域技术人员将理解的，将没有用于掩模的凸块布局或流片。这可以降低布局的复杂度并且改进改变的灵活性。此外，本说明书的实施例对于具有混合间距和/或混合临界尺寸的集成电路封装可以具有优势，因为难以针对这样的应用对已知的虚设装置设计进行优化。此外，本说明书的通用虚设装置的附接不需要接合焊盘或对其图案化，并且将不需要精确的放置。从制造的角度来看，通用虚设装置将不需要用于无活性装置基板的高级材料，并且由于将不存在保质期，所以可以提前制作，但是出于库存目的的单个化除外。
图7是制作集成电路封装的工艺200的流程图。如方框210中所阐述的，可以形成具有附接表面的无活性装置基板。如方框220中所阐述的，可以在无活性装置基板的附接表面上形成金属化层。如方框230中所阐述的，可以形成有源集成电路装置。如方框240中所阐述的，可以形成电子基板。如方框250中所阐述的，金属化层可以通过多个焊料互连中的至少一个焊料互连附接到电子基板。如方框260中所阐述的，有源集成电路装置可以采用多个焊料互连中的至少一个其他焊料互连电附接到电子基板。
图8示出了根据本说明书的一个实施方式的电子或计算装置300。计算装置300可以包括其中布置有板302的外壳301。计算装置300可以包括多个集成电路部件，包括但不限于处理器304、至少一个通信芯片306A、306B、易失性存储器308(例如，DRAM)、非易失性存储器310(例如，ROM)、闪速存储器312、图形处理器或CPU 314、数字信号处理器(未示出)、密码处理器(未示出)、芯片组316、天线、显示器(触摸屏显示器)、触摸屏控制器、电池、音频编码解码器(未示出)、视频编码解码器(未示出)、功率放大器(AMP)、全球定位系统(GPS)装置、罗盘、加速度计(未示出)、陀螺仪(未示出)、扬声器、相机和大容量存储装置(未示出)(例如硬盘驱动器、压缩光盘(CD)、数字多功能光盘(DVD)等)。集成电路部件中的任何集成电路部件可以物理耦合和电耦合到板302。在一些实施方式中，集成电路部件中的至少一个集成电路部件可以是处理器304的一部分。
通信芯片实现了用于向计算装置传输数据和从计算装置传输数据的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经调制的电磁辐射通过非固态介质来传送数据的电路、装置、系统、方法、技术、通信信道等。该术语并不暗示相关联的装置不含有任何导线，尽管在一些实施例中，它们可能不含有。通信芯片可以实施多种无线标准或协议中的任何无线标准或协议，其包括但不限于Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生产物以及任何其他被指定为3G、4G、5G和更高版本的无线协议。计算装置可以包括多个通信芯片。例如，第一通信芯片可以专用于较短程的无线通信，例如Wi-Fi和蓝牙，并且第二通信芯片可以专用于较长程的无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等。
术语“处理器”可以指对来自寄存器和/或存储器的电子数据进行处理以将该电子数据变换成可以被存储在寄存器和/或存储器中的其他电子数据的任何装置或装置的部分。
集成电路部件中的至少一个集成电路部件可以包括集成电路封装，该集成电路封装包括：电子基板；至少一个通用虚设装置，其包括具有附接表面和位于附接表面上的金属化层的无活性装置基板，其中，金属化层采用多个焊料互连中的至少一个焊料互连附接到电子基板；以及至少一个有源集成电路装置，其中，至少一个有源集成电路装置采用多个焊料互连中的至少一个其他焊料互连附接到电子基板。
在各种实施方式中，计算装置可以是膝上型电脑、上网本、笔记本、超极本、智能电话、平板电脑、个人数字助理(PDA)、超移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数码相机、便携式音乐播放器或数字录像机。在其他实施方式中，计算装置可以是处理数据的任何其他电子装置。
应当理解，本说明书的主题不必限于图1-图8中所示的特定应用。如本领域技术人员将理解的，本主题可以应用于其他集成电路装置和组装应用以及任何适当的电子应用。
以下示例涉及其他实施例并且示例中的细节可以在一个或多个实施例中的任何地方使用，其中，示例1是集成电路封装，包括：电子基板；具有附接表面的无活性装置基板；位于无活性装置基板的附接表面上的金属化层，其中，金属化层采用多个焊料互连中的至少一个焊料互连附接到电子基板；以及有源集成电路装置，其中，有源集成电路装置采用多个焊料互连中的至少一个其他焊料互连电附接到电子基板。
在示例2中，根据示例1所述的主题可以可选地包括：金属化层在无活性装置基板的整个附接表面上延伸。
在示例3中，根据示例1所述的主题可以可选地包括：金属化层在无活性装置基板的附接表面上是被图案化的。
在示例4中，根据示例1至3中任何一项所述的主题可以可选地包括：金属化层是多个材料层。
在示例5中，根据示例4所述的主题可以任选地包括：多个层具有包括低氧化金属的最外层。
在示例6中，根据示例4所述的主题可以可选地包括：多个材料层包括位于无活性装置基板上的氮化硅层、位于氮化硅层上的钛层、位于钛层上的镍/钒合金以及位于镍/钒合金层上的金层。
在示例7中，根据示例1至6中任何一项所述的主题可以任选地包括：无活性装置基板包括硅和锗中的至少一种。
示例8是一种电子系统，包括电子板以及电附接到电子板上的集成电路封装，其中，集成电路封装包括：电子基板；具有附接表面的无活性装置基板；位于无活性装置基板的附接表面上的金属化层，其中，金属化层采用多个焊料互连中的至少一个焊料互连附接到电子基板；以及有源集成电路装置，其中，有源集成电路装置采用多个焊料互连中的至少一个其他焊料互连电附接到电子基板。
在示例9中，根据示例8所述的主题可以可选地包括：金属化层在无活性装置基板的整个附接表面上延伸。
在示例10中，根据示例8所述的主题可以可选地包括：金属化层在无活性装置基板的附接表面上是被图案化的。
在示例11中，根据示例8至10中任何一项所述的主题可以可选地包括：金属化层是多个材料层。
在示例12中，根据示例11所述的主题可以任选地包括：多个材料层具有包括低氧化金属的最外层。
在示例13中，根据示例11所述的主题可以可选地包括：多个材料层包括位于无活性装置基板上的氮化硅层、位于氮化硅层上的钛层、位于钛层上的镍/钒合金以及位于镍/钒合金层上的金层。
示例14是一种制作集成电路封装的方法，包括：形成具有附接表面的无活性装置基板，在位于无活性装置基板的附接表面上形成金属化层，形成有源集成电路装置，形成电子基板，采用多个焊料互连中的至少一个焊料互连将金属化层附接到电子基板，以及采用多个焊料互连中的至少一个其他焊料互连将有源集成电路装置电附接到电子基板。
在示例15中，根据示例14所述的主题可以可选地包括：形成在无活性装置基板的整个附接表面上延伸的金属化层。
在示例16中，根据示例14所述的主题可以可选地包括：形成至少一个通用虚设装置包括对在无活性装置基板的附接表面上的金属化层进行图案化。
在示例17中，根据示例16所述的主题可以可选地包括：对在无活性装置基板的附接表面上的金属化层进行图案化包括：形成在无活性装置基板的整个附接表面上延伸的金属化层并且烧蚀掉金属化层的选定部分。
在示例18中，根据示例14至17中任何一项所述的主题可以可选地包括：形成金属化层包括形成多个材料层。
在示例19中，根据示例18所述的主题可以任选地包括：形成多个材料层包括形成包括低氧化金属的最外层。
在示例20中，根据示例18所述的主题可以可选地包括：形成多个材料层包括形成位于无活性装置基板上的氮化硅层、形成位于氮化硅层上的钛层、形成位于钛层上的镍/钒合金以及形成位于镍/钒合金层上的金层。
因此，已经详细描述了本发明的具体实施例，应当理解，由所附权利要求限定的本发明不受上述说明书中阐述的特定细节的限制，因为在不脱离本发明的精神或范围的情况下，本发明的许多明显变化是可能的。

Claims (22)

1.一种集成电路封装，包括：
电子基板；
无活性装置基板，其具有附接表面；
金属化层，其位于所述无活性装置基板的所述附接表面上，其中，所述金属化层采用多个焊料互连中的至少一个焊料互连附接到所述电子基板；以及
有源集成电路装置，其中，所述有源集成电路装置采用所述多个焊料互连中的至少一个其他焊料互连电附接到所述电子基板。
2.根据权利要求1所述的集成电路封装，其中，所述金属化层在所述无活性装置基板的整个所述附接表面上延伸。
3.根据权利要求1所述的集成电路封装，其中，所述金属化层在所述无活性装置基板的所述附接表面上是被图案化的。
4.根据权利要求1至3中任何一项所述的集成电路封装，其中，所述金属化层包括多个材料层。
5.根据权利要求4所述的集成电路封装，其中，所述多个材料层包括最外层，所述最外层包括低氧化金属。
6.根据权利要求4所述的集成电路封装，其中，所述多个材料层包括位于所述无活性装置基板上的氮化硅层、位于所述氮化硅层上的钛层、位于所述钛层上的镍/钒合金以及位于所述镍/钒合金层上的金层。
7.根据权利要求1至3中任何一项所述的集成电路封装，其中，所述无活性装置基板包括硅和锗中的至少一种。
8.一种电子系统，包括：
电子板；以及
集成电路封装，其电附接到所述电子板，其中，所述集成电路封装包括：
电子基板；
无活性装置基板，其具有附接表面；
金属化层，其位于所述无活性装置基板的所述附接表面上，其中，所述金属化层采用多个焊料互连中的至少一个焊料互连附接到所述电子基板；以及
集成电路装置，其中，所述集成电路装置采用所述多个焊料互连中的至少一个其他焊料互连电附接到所述电子基板。
9.根据权利要求8所述的电子系统，其中，所述金属化层在所述无活性装置基板的整个所述附接表面上延伸。
10.根据权利要求8所述的电子系统，其中，所述金属化层在所述无活性装置基板的所述附接表面上是被图案化的。
11.根据权利要求8至10中任何一项所述的电子系统，其中，所述金属化层包括多个材料层。
12.根据权利要求11所述的电子系统，其中，所述多个材料层包括最外层，所述最外层包括低氧化金属。
13.根据权利要求11所述的电子系统，其中，所述多个材料层包括位于所述无活性装置基板上的氮化硅层、位于所述氮化硅层上的钛层、位于所述钛层上的镍/钒合金以及位于所述镍/钒合金层上的金层。
14.根据权利要求8至10中任何一项所述的电子系统，其中，所述无活性装置基板包括硅和锗中的至少一种。
15.一种制作集成电路封装的方法，包括：
形成具有附接表面的无活性装置基板；
在位于所述无活性装置基板上的所述附接表面上形成金属化层；
形成有源集成电路装置；
形成电子基板；
采用多个焊料互连中的至少一个焊料互连将所述金属化层附接到所述电子基板；以及
采用所述多个焊料互连中的至少一个其他焊料互连将所述有源集成电路装置电附接到所述电子基板。
16.根据权利要求15所述的方法，其中，形成所述金属化层包括形成在所述无活性装置基板的整个所述附接表面上延伸的所述金属化层。
17.根据权利要求15所述的方法，其中，形成所述金属化层包括对在所述无活性装置基板的所述附接表面上的所述金属化层进行图案化。
18.根据权利要求17所述的方法，其中，对在所述无活性装置基板的所述附接表面上的所述金属化层进行图案化包括：形成在所述无活性装置基板的整个所述附接表面上延伸的所述金属化层并且烧蚀掉所述金属化层的选定部分。
19.根据权利要求15至18中任何一项所述的方法，其中，形成所述金属化层包括形成多个材料层。
20.根据权利要求19所述的方法，其中，形成所述多个材料层包括形成包括低氧化金属的最外层。
21.根据权利要求19所述的方法，其中，形成所述多个材料层包括形成位于所述无活性装置基板上的氮化硅层、形成位于所述氮化硅层上的钛层、形成位于所述钛层上的镍/钒合金以及形成位于所述镍/钒合金层上的金层。
22.根据权利要求15至18中任何一项所述的方法，其中，形成所述无活性装置基板包括由硅和锗中的至少一种形成所述无活性装置。
CN202180071393.3A 2020-11-20 2021-09-09 用于集成电路封装的通用无电活性装置 Pending CN116529866A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/100,449 2020-11-20
US17/100,449 US20220165625A1 (en) 2020-11-20 2020-11-20 Universal electrically inactive devices for integrated circuit packages
PCT/US2021/049603 WO2022108644A1 (en) 2020-11-20 2021-09-09 Universal electrically inactive devices for integrated circuit packages

Publications (1)

Publication Number Publication Date
CN116529866A true CN116529866A (zh) 2023-08-01

Family

ID=81658586

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180071393.3A Pending CN116529866A (zh) 2020-11-20 2021-09-09 用于集成电路封装的通用无电活性装置

Country Status (6)

Country Link
US (1) US20220165625A1 (zh)
EP (1) EP4248492A4 (zh)
CN (1) CN116529866A (zh)
NL (1) NL2029424B1 (zh)
TW (1) TW202236586A (zh)
WO (1) WO2022108644A1 (zh)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
WO2011014409A1 (en) * 2009-07-30 2011-02-03 Megica Corporation System-in packages
US9613931B2 (en) * 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US10115688B2 (en) * 2015-05-29 2018-10-30 Infineon Technologies Ag Solder metallization stack and methods of formation thereof
US10153222B2 (en) * 2016-11-14 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US9865567B1 (en) * 2017-02-02 2018-01-09 Xilinx, Inc. Heterogeneous integration of integrated circuit device and companion device
US10431517B2 (en) * 2017-08-25 2019-10-01 Advanced Micro Devices, Inc. Arrangement and thermal management of 3D stacked dies
US10636746B2 (en) * 2018-02-26 2020-04-28 International Business Machines Corporation Method of forming an electronic package
US10770364B2 (en) * 2018-04-12 2020-09-08 Xilinx, Inc. Chip scale package (CSP) including shim die
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
US11587843B2 (en) * 2018-12-13 2023-02-21 Intel Corporation Thermal bump networks for integrated circuit device assemblies
US10818651B2 (en) * 2019-01-29 2020-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure

Also Published As

Publication number Publication date
WO2022108644A1 (en) 2022-05-27
NL2029424B1 (en) 2023-06-13
EP4248492A4 (en) 2024-10-16
TW202236586A (zh) 2022-09-16
EP4248492A1 (en) 2023-09-27
NL2029424A (en) 2022-07-01
US20220165625A1 (en) 2022-05-26

Similar Documents

Publication Publication Date Title
CN112530906A (zh) 用于集成电路封装的有机插入器
US20240331921A1 (en) Electronic substrates having embedded inductors
NL2028989B1 (en) Electronic substrates having embedded inductors
US20220293327A1 (en) Coreless electronic substrates having embedded inductors
US20220093535A1 (en) Electronic substrates having embedded inductors
US11749585B2 (en) High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package
US11823972B2 (en) Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
CN114762107A (zh) 用于集成电路设备的金属化层中的跳层级过孔
US12087682B2 (en) Power delivery structures
US11817349B2 (en) Conductive route patterning for electronic substrates
US11621208B2 (en) Thermal management solutions that reduce inductive coupling between stacked integrated circuit devices
US20220165625A1 (en) Universal electrically inactive devices for integrated circuit packages
US20220139792A1 (en) Electronic substrates having heterogeneous dielectric layers
US12027466B2 (en) Conductive route patterning for electronic substrates
US20220051986A1 (en) Stepped electronic substrate for integrated circuit packages
US20230197547A1 (en) Edge-aligned template structure for integrated circuit packages
EP4203020A1 (en) Edge-aligned template structure for integrated circuit packages
US20240355725A1 (en) Power delivery structures
EP4009353A2 (en) Underfilled integrated circuit assembly with substrate having opening therein and method of underfilling an integrated circuit assembly
CN115394744A (zh) 用于电子衬底的混合导电过孔

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination